From: Andy Gross <agross@codeaurora.org>
To: Vinod Koul <vinod.koul@intel.com>,
Dan Williams <dan.j.williams@intel.com>
Cc: dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
Andy Gross <agross@codeaurora.org>
Subject: [PATCH v2 2/2] dmaengine: qcom_bam_dma: Add device tree binding
Date: Fri, 10 Jan 2014 13:07:54 -0600 [thread overview]
Message-ID: <1389380874-22753-3-git-send-email-agross@codeaurora.org> (raw)
In-Reply-To: <1389380874-22753-1-git-send-email-agross@codeaurora.org>
Add device tree binding support for the QCOM BAM DMA driver.
Signed-off-by: Andy Gross <agross@codeaurora.org>
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 52 ++++++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
new file mode 100644
index 0000000..6a48188
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
@@ -0,0 +1,52 @@
+QCOM BAM DMA controller
+
+Required properties:
+- compatible: Must be "qcom,bam-v1.4.0" for MSM8974 V1
+ Must be "qcom,bam-v1.4.1" for MSM8974 V2
+- reg: Address range for DMA registers
+- interrupts: single interrupt for this controller
+- #dma-cells: must be <3>
+- clocks: required clock
+- clock-names: name of clock
+
+Example:
+
+ uart-bam: dma@f9984000 = {
+ compatible = "qcom,bam-v1.4.1";
+ reg = <0xf9984000 0x15000>;
+ interrupts = <0 94 0>;
+ clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <3>;
+ };
+
+Client:
+Required properties:
+- dmas: List of dma channel requests
+- dma-names: Names of aforementioned requested channels
+
+Clients must use the format described in the dma.txt file, using a four cell
+specifier for each channel.
+
+The four cells in order are:
+ 1. A phandle pointing to the DMA controller
+ 2. The channel number
+ 3. The execution environment value for this channel. This is used to indicate
+ the trustzone index used during register access.
+ 4. Direction of the fixed unidirectional channel
+ 0 - Memory to Device
+ 1 - Device to Memory
+ 2 - Device to Device
+
+Example:
+ serial@f991e000 {
+ compatible = "qcom,msm-uart";
+ reg = <0xf991e000 0x1000>
+ <0xf9944000 0x19000>;
+ interrupts = <0 108 0>;
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+
+ dmas = <&uart-bam 0 0 1>, <&uart-bam 1 0 0>;
+ dma-names = "rx", "tx";
+ };
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
prev parent reply other threads:[~2014-01-10 19:07 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-10 19:07 [PATCH v2 0/2] Add Qualcomm BAM dmaengine driver Andy Gross
2014-01-10 19:07 ` [PATCH v2 1/2] dmaengine: add Qualcomm BAM dma driver Andy Gross
2014-01-13 10:31 ` Shevchenko, Andriy
2014-01-20 23:31 ` Andy Gross
2014-01-14 19:43 ` Stephen Boyd
2014-01-20 23:20 ` Andy Gross
2014-01-17 22:49 ` Arnd Bergmann
2014-01-20 22:52 ` Andy Gross
2014-01-21 8:03 ` Arnd Bergmann
2014-01-21 23:01 ` Andy Gross
2014-01-21 23:12 ` Arnd Bergmann
2014-01-23 20:17 ` Kumar Gala
2014-01-23 22:50 ` Andy Gross
2014-01-10 19:07 ` Andy Gross [this message]
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