* [PATCH] Change timer interrupt to edge sensitive
@ 2018-08-02 11:41 Silvan Murer
2018-08-07 19:23 ` Silvan Murer
0 siblings, 1 reply; 4+ messages in thread
From: Silvan Murer @ 2018-08-02 11:41 UTC (permalink / raw)
To: devicetree, thor.thayer; +Cc: dinguyen, Silvan Murer
Signed-off-by: Silvan Murer <silvan.murer@gmail.com>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 791ca15..52a7025 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -748,7 +748,7 @@
timer@ffffc600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xffffc600 0x100>;
- interrupts = <1 13 0xf04>;
+ interrupts = <1 13 0xf01>;
clocks = <&mpu_periph_clk>;
};
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] Change timer interrupt to edge sensitive
2018-08-02 11:41 [PATCH] Change timer interrupt to edge sensitive Silvan Murer
@ 2018-08-07 19:23 ` Silvan Murer
2018-08-07 22:03 ` Thor Thayer
0 siblings, 1 reply; 4+ messages in thread
From: Silvan Murer @ 2018-08-07 19:23 UTC (permalink / raw)
To: thor.thayer, devicetree; +Cc: dinguyen
Hi Thor,
Did you saw my patch? I think the default configuration for the timer interrupt should be <1 13 0xf01>
Otherwise, the driver get the error "GIC: PPI13 is secure or misconfigured"
Base on the ARM documentation it is a edge sensitive trigger:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407f/CCHEIGIC.html
Or do I understand something wrong?
Best regards,
Silvan
On 02.08.2018 13:41, Silvan Murer wrote:
> Signed-off-by: Silvan Murer <silvan.murer@gmail.com>
> ---
> arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
> index 791ca15..52a7025 100644
> --- a/arch/arm/boot/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
> @@ -748,7 +748,7 @@
> timer@ffffc600 {
> compatible = "arm,cortex-a9-twd-timer";
> reg = <0xffffc600 0x100>;
> - interrupts = <1 13 0xf04>;
> + interrupts = <1 13 0xf01>;
> clocks = <&mpu_periph_clk>;
> };
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] Change timer interrupt to edge sensitive
2018-08-07 19:23 ` Silvan Murer
@ 2018-08-07 22:03 ` Thor Thayer
2018-08-15 15:11 ` Dinh Nguyen
0 siblings, 1 reply; 4+ messages in thread
From: Thor Thayer @ 2018-08-07 22:03 UTC (permalink / raw)
To: Silvan Murer, devicetree; +Cc: dinguyen
Hi Silvan,
On 08/07/2018 02:23 PM, Silvan Murer wrote:
> Hi Thor,
>
> Did you saw my patch? I think the default configuration for the timer interrupt should be <1 13 0xf01>
>
> Otherwise, the driver get the error "GIC: PPI13 is secure or misconfigured"
>
> Base on the ARM documentation it is a edge sensitive trigger:
> http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407f/CCHEIGIC.html
>
> Or do I understand something wrong?
>
This looks correct. In fact, our socfpga.dtsi base file uses the rising
edge.
> Best regards,
> Silvan
>
>
> On 02.08.2018 13:41, Silvan Murer wrote:
>> Signed-off-by: Silvan Murer <silvan.murer@gmail.com>
>> ---
>> arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
>> index 791ca15..52a7025 100644
>> --- a/arch/arm/boot/dts/socfpga_arria10.dtsi
>> +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
>> @@ -748,7 +748,7 @@
>> timer@ffffc600 {
>> compatible = "arm,cortex-a9-twd-timer";
>> reg = <0xffffc600 0x100>;
>> - interrupts = <1 13 0xf04>;
>> + interrupts = <1 13 0xf01>;
>> clocks = <&mpu_periph_clk>;
>> };
>>
>
Reviewed-by: Thor Thayer <thor.thayer@linux.intel.com>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] Change timer interrupt to edge sensitive
2018-08-07 22:03 ` Thor Thayer
@ 2018-08-15 15:11 ` Dinh Nguyen
0 siblings, 0 replies; 4+ messages in thread
From: Dinh Nguyen @ 2018-08-15 15:11 UTC (permalink / raw)
To: thor.thayer, Silvan Murer, devicetree
On 08/07/2018 05:03 PM, Thor Thayer wrote:
> Hi Silvan,
>
> On 08/07/2018 02:23 PM, Silvan Murer wrote:
>> Hi Thor,
>>
>> Did you saw my patch? I think the default configuration for the timer
>> interrupt should be <1 13 0xf01>
>>
>> Otherwise, the driver get the error "GIC: PPI13 is secure or
>> misconfigured"
>>
>> Base on the ARM documentation it is a edge sensitive trigger:
>> http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407f/CCHEIGIC.html
>>
>> Or do I understand something wrong?
>>
> This looks correct. In fact, our socfpga.dtsi base file uses the rising
> edge.
>
>> Best regards,
>> Silvan
>>
>>
>> On 02.08.2018 13:41, Silvan Murer wrote:
>>> Signed-off-by: Silvan Murer <silvan.murer@gmail.com>
>>> ---
>>> arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi
>>> b/arch/arm/boot/dts/socfpga_arria10.dtsi
>>> index 791ca15..52a7025 100644
>>> --- a/arch/arm/boot/dts/socfpga_arria10.dtsi
>>> +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
>>> @@ -748,7 +748,7 @@
>>> timer@ffffc600 {
>>> compatible = "arm,cortex-a9-twd-timer";
>>> reg = <0xffffc600 0x100>;
>>> - interrupts = <1 13 0xf04>;
>>> + interrupts = <1 13 0xf01>;
>>> clocks = <&mpu_periph_clk>;
>>> };
>>>
>>
> Reviewed-by: Thor Thayer <thor.thayer@linux.intel.com>
>
Applied!
Thanks,
Dinh
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-08-15 18:03 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-08-02 11:41 [PATCH] Change timer interrupt to edge sensitive Silvan Murer
2018-08-07 19:23 ` Silvan Murer
2018-08-07 22:03 ` Thor Thayer
2018-08-15 15:11 ` Dinh Nguyen
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).