Re: [PATCH v2 1/4] riscv: add UltraRISC SoC family Kconfig support

Jia Wang
2026-04-08T01:47:17Z

On 2026-04-07 17:29 +0100, Conor Dooley wrote:
> On Tue, Apr 07, 2026 at 10:40:52AM +0800, Jia Wang wrote:
> > The first SoC in the UltraRISC series is UR-DP1000, containing octa
> > UltraRISC C100 cores.
>
> Not gonna lie, I find it odd that pcie is where this platform starts
> off, but sure. What's the plan for adding the rest of the platform?
>

Hi Conor,

Thanks for the question.

Our next step is to upstream the pinctrl driver together with the related
DTS updates. The pinctrl series only affects the SoC’s low-speed peripheral
interfaces. For GMAC, SPI, I2C, and GPIO, we plan to use the existing
kernel drivers, so no new controller drivers are needed
> >
> > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > ---
> > arch/riscv/Kconfig.socs | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index d621b85dd63b..98708569ec6a 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -84,6 +84,15 @@ config ARCH_THEAD
> > help
> > This enables support for the RISC-V based T-HEAD SoCs.
> >
> > +config ARCH_ULTRARISC
> > + bool "UltraRISC RISC-V SoCs"
> > + help
> > + This enables support for UltraRISC SoC platform hardware,
> > + including boards based on the UR-DP1000.
>
> > + UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports
> > + the RV64GCBHX ISA. It supports Hardware Virtualization
> > + and RISC-V RV64 ISA H(v1.0) Extension.
>
> Delete this section IMO, doesn't provide any real value. Don't need nor
> want the marketing brochure in the help text. The first sentence is
> sufficient.
>

I’ll drop the SoC description part from the Kconfig help text as you
suggested.

> > +
> > config ARCH_VIRT
> > bool "QEMU Virt Machine"
> > select POWER_RESET
> >
> > --
> > 2.34.1
> >

Best regards,
Jia Wang