From mboxrd@z Thu Jan 1 00:00:00 1970 From: Carlo Caione Subject: [PATCH v4 0/3] ARM: sun7i/sun6i: irqchip: Irqchip driver for NMI Date: Thu, 27 Feb 2014 20:34:19 +0100 Message-ID: <1393529662-8663-1-git-send-email-carlo@caione.org> Reply-To: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Return-path: List-Post: , List-Help: , List-Archive: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Subscribe: , List-Unsubscribe: , To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org, maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: Carlo Caione List-Id: devicetree@vger.kernel.org Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI. Three register are present to (un)mask, control and acknowledge NMI. These two patches add a new irqchip driver in cascade with GIC. Changes since v1: - added binding document Changes since v2: - fixed trigger type in DTS - new explanations in binding documentation - added support for A31 (sun6i) Changes since v3: - changed compatibles Carlo Caione (3): ARM: sun7i/sun6i: irqchip: Add irqchip driver for NMI controller ARM: sun7i/sun6i: dts: Add NMI irqchip support ARM: sun7i/sun6i: irqchip: Update the documentation .../allwinner,sun67i-sc-nmi.txt | 27 +++ arch/arm/boot/dts/sun6i-a31.dtsi | 9 + arch/arm/boot/dts/sun7i-a20.dtsi | 9 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sunxi-nmi.c | 228 +++++++++++++++++++++ 5 files changed, 274 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt create mode 100644 drivers/irqchip/irq-sunxi-nmi.c -- 1.8.3.2