From mboxrd@z Thu Jan 1 00:00:00 1970 From: Boris BREZILLON Subject: [PATCH 05/11] ARM: at91/dt: move sama5d3 SoC to the new main/slow clk model Date: Tue, 18 Mar 2014 21:18:38 +0100 Message-ID: <1395173924-3648-6-git-send-email-b.brezillon.dev@gmail.com> References: <1395173924-3648-1-git-send-email-b.brezillon.dev@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1395173924-3648-1-git-send-email-b.brezillon.dev@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Nicolas Ferre , Mike Turquette , Alexandre Belloni , Jean-Jacques Hiblot Cc: devicetree@vger.kernel.org, Boris BREZILLON , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Boris BREZILLON , linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org Replace the old main and clk definitions (fixed rate clk) by the new main and slow clk subtree definition (ck = mux(rc_osc, osc)). Signed-off-by: Boris BREZILLON --- arch/arm/boot/dts/sama5d3.dtsi | 61 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 55 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 3d5faf8..015797d 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -59,6 +59,18 @@ }; clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + adc_op_clk: adc_op_clk{ compatible = "fixed-clock"; #clock-cells = <0>; @@ -760,18 +772,29 @@ #size-cells = <0>; #interrupt-cells = <1>; - clk32k: slck { - compatible = "fixed-clock"; + main_rc_osc: main_rc_osc { + compatible = "atmel,at91sam9x5-clk-main-rc-osc"; #clock-cells = <0>; - clock-frequency = <32768>; + interrupt-parent = <&pmc>; + interrupts = ; + clock-frequency = <12000000>; + clock-accuracy = <50000000>; }; - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; #clock-cells = <0>; interrupt-parent = <&pmc>; interrupts = ; - clocks = <&clk32k>; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91sam9x5-clk-main"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = ; + clocks = <&main_rc_osc &main_osc>; }; plla: pllack { @@ -1100,6 +1123,32 @@ status = "disabled"; }; + sckc@fffffe50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffe50 0x4>; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-accuracy = <50000000>; + atmel,startup-time-usec = <75>; + }; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + clocks = <&slow_xtal>; + atmel,startup-time-usec = <1200000>; + }; + + clk32k: slowck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc &slow_osc>; + }; + }; + rtc@fffffeb0 { compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffeb0 0x30>; -- 1.7.9.5