Re: [PATCHv2 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV

[Thor Thayer <tthayer-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>]

On Mon, 2014-04-21 at 12:27 +0200, Pavel Machek wrote:
> Hi!
> 
> > From: Thor Thayer <tthayer-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>
> > 
> > Added EDAC support for reporting ECC errors of CycloneV
> > and ArriaV SDRAM controller.
> > - The SDRAM Controller registers are used by the FPGA bridge so
> >   these are accessed through the syscon interface.
> > - The configuration of the SDRAM memory size for the EDAC framework
> >   is discovered from the SDRAM Controller registers.
> > - Documentation of the bindings in devicetree/bindings/arm/altera/
> >   socfpga-sdram-edac.txt
> > - Correction of single bit errors, detection of double bit errors.
> > 
> > ---
> > v2: Use the SDRAM controller registers to calculate memory size
> >     instead of the Device Tree. Update To & Cc list. Add maintainer 
> >     information.
> 
> I'd reduce number of *s in the messages, otherwise
> 
> Reviewed-by: Pavel Machek <pavel-+ZI9xUNit7I@public.gmane.org>
> 
> for whole series.
> 								Pavel
> 
Hi Pavel.

Noted - I will make the change. Thank you for reviewing.

Thor

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