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From: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
To: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-omap-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: rogerq-l0cyMroinI0@public.gmane.org,
	balajitk-l0cyMroinI0@public.gmane.org,
	Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>,
	Rajendra Nayak <rnayak-l0cyMroinI0@public.gmane.org>,
	Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>,
	Paul Walmsley <paul-DWxLp4Yu+b8AvxtiuMwx3w@public.gmane.org>
Subject: [PATCH 03/17] phy: ti-pipe3: add external clock support for PCIe PHY
Date: Tue, 6 May 2014 19:03:49 +0530	[thread overview]
Message-ID: <1399383244-14556-4-git-send-email-kishon@ti.com> (raw)
In-Reply-To: <1399383244-14556-1-git-send-email-kishon-l0cyMroinI0@public.gmane.org>

APLL used by PCIE phy can either use external clock as input or the clock
from DPLL. Added support for the APLL to use external clock as input here.

Cc: Rajendra Nayak <rnayak-l0cyMroinI0@public.gmane.org>
Cc: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
Cc: Paul Walmsley <paul-DWxLp4Yu+b8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
---
 Documentation/devicetree/bindings/phy/ti-phy.txt |    4 ++
 drivers/phy/phy-ti-pipe3.c                       |   75 ++++++++++++++--------
 2 files changed, 52 insertions(+), 27 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt
index bc9afb5..d50f8ee 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -76,6 +76,10 @@ Required properties:
    * "dpll_ref_m2" - external dpll ref clk
    * "phy-div" - divider for apll
    * "div-clk" - apll clock
+   * "apll_mux" - mux for pcie apll
+   * "refclk_ext" - external reference clock for pcie apll
+ - ti,ext-clk: To specifiy if PCIE apll should use external clock. Applicable
+   only to PCIE PHY.
 
 Optional properties:
  - ctrl-module : phandle of the control module used by PHY driver to power on
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index d43019d..5513aa0 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -293,7 +293,7 @@ static int ti_pipe3_probe(struct platform_device *pdev)
 	struct device_node *control_node;
 	struct platform_device *control_pdev;
 	const struct of_device_id *match;
-	struct clk *clk;
+	struct clk *clk, *pclk;
 
 	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
 	if (!phy) {
@@ -302,6 +302,20 @@ static int ti_pipe3_probe(struct platform_device *pdev)
 	}
 	phy->dev		= &pdev->dev;
 
+	control_node = of_parse_phandle(node, "ctrl-module", 0);
+	if (!control_node) {
+		dev_err(&pdev->dev, "Failed to get control device phandle\n");
+		return -EINVAL;
+	}
+
+	control_pdev = of_find_device_by_node(control_node);
+	if (!control_pdev) {
+		dev_err(&pdev->dev, "Failed to get control device\n");
+		return -EINVAL;
+	}
+
+	phy->control_dev = &control_pdev->dev;
+
 	if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
 		match = of_match_device(of_match_ptr(ti_pipe3_id_table),
 					&pdev->dev);
@@ -345,19 +359,40 @@ static int ti_pipe3_probe(struct platform_device *pdev)
 	}
 
 	if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
-		clk = devm_clk_get(phy->dev, "dpll_ref");
-		if (IS_ERR(clk)) {
-			dev_err(&pdev->dev, "unable to get dpll ref clk\n");
-			return PTR_ERR(clk);
+		if (!of_property_read_bool(node, "ti,ext-clk")) {
+			clk = devm_clk_get(phy->dev, "dpll_ref");
+			if (IS_ERR(clk)) {
+				dev_err(&pdev->dev,
+					"unable to get dpll ref clk\n");
+				return PTR_ERR(clk);
+			}
+			clk_set_rate(clk, 1500000000);
+
+			clk = devm_clk_get(phy->dev, "dpll_ref_m2");
+			if (IS_ERR(clk)) {
+				dev_err(&pdev->dev,
+					"unable to get dpll ref m2 clk\n");
+				return PTR_ERR(clk);
+			}
+			clk_set_rate(clk, 100000000);
+		} else {
+			omap_control_pcie_tx_rx_control(phy->control_dev,
+						OMAP_CTRL_PCIE_PHY_RX_ACSPCIE);
+
+			clk = clk_get(phy->dev, "apll_mux");
+			if (IS_ERR(clk)) {
+				dev_err(&pdev->dev, "unable to get apll mux clk\n");
+				return PTR_ERR(clk);
+			}
+
+			pclk = clk_get(phy->dev, "refclk_ext");
+			if (IS_ERR(pclk)) {
+				dev_err(&pdev->dev, "unable to get ext ref clk for apll\n");
+				return PTR_ERR(pclk);
+			}
+
+			clk_set_parent(clk, pclk);
 		}
-		clk_set_rate(clk, 1500000000);
-
-		clk = devm_clk_get(phy->dev, "dpll_ref_m2");
-		if (IS_ERR(clk)) {
-			dev_err(&pdev->dev, "unable to get dpll ref m2 clk\n");
-			return PTR_ERR(clk);
-		}
-		clk_set_rate(clk, 100000000);
 
 		clk = devm_clk_get(phy->dev, "phy-div");
 		if (IS_ERR(clk)) {
@@ -375,20 +410,6 @@ static int ti_pipe3_probe(struct platform_device *pdev)
 		phy->div_clk = ERR_PTR(-ENODEV);
 	}
 
-	control_node = of_parse_phandle(node, "ctrl-module", 0);
-	if (!control_node) {
-		dev_err(&pdev->dev, "Failed to get control device phandle\n");
-		return -EINVAL;
-	}
-
-	control_pdev = of_find_device_by_node(control_node);
-	if (!control_pdev) {
-		dev_err(&pdev->dev, "Failed to get control device\n");
-		return -EINVAL;
-	}
-
-	phy->control_dev = &control_pdev->dev;
-
 	omap_control_phy_power(phy->control_dev, 0);
 
 	platform_set_drvdata(pdev, phy);
-- 
1.7.9.5

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  parent reply	other threads:[~2014-05-06 13:33 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-05-06 13:33 [PATCH 00/17] PCIe support for DRA7xx Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 01/17] phy: phy-omap-pipe3: Add support for PCIe PHY Kishon Vijay Abraham I
2014-05-14 12:57   ` Roger Quadros
2014-05-06 13:33 ` [PATCH 04/17] phy: pipe3: insert delay to enumerate in GEN2 mode Kishon Vijay Abraham I
2014-05-14 13:20   ` Roger Quadros
2014-05-06 13:33 ` [PATCH 05/17] pci: host: pcie-dra7xx: add support for pcie-dra7xx controller Kishon Vijay Abraham I
2014-05-06 13:44   ` Marek Vasut
     [not found]     ` <201405061544.28738.marex-ynQEQJNshbs@public.gmane.org>
2014-05-07  8:21       ` Kishon Vijay Abraham I
2014-05-09  9:43       ` Pavel Machek
     [not found]   ` <1399383244-14556-6-git-send-email-kishon-l0cyMroinI0@public.gmane.org>
2014-05-06 13:54     ` Arnd Bergmann
2014-05-07  8:44       ` Kishon Vijay Abraham I
2014-05-07  9:30         ` Arnd Bergmann
2014-05-09 11:29           ` Kishon Vijay Abraham I
2014-05-06 16:35   ` Jason Gunthorpe
2014-05-07  9:22     ` Kishon Vijay Abraham I
2014-05-07  9:25       ` Arnd Bergmann
2014-05-08  8:56         ` Jingoo Han
2014-05-08  9:16           ` Arnd Bergmann
2014-05-06 13:33 ` [PATCH 06/17] pci: host: pcie-designware: Use *base-mask* for configuring the iATU Kishon Vijay Abraham I
2014-05-06 13:59   ` Arnd Bergmann
2014-05-08  9:05     ` Jingoo Han
2014-05-08  9:18       ` Arnd Bergmann
2014-05-09 11:50         ` Kishon Vijay Abraham I
2014-05-12  1:44           ` Jingoo Han
2014-05-13 12:31         ` Kishon Vijay Abraham I
     [not found]           ` <537210BF.2050100-l0cyMroinI0@public.gmane.org>
2014-05-13 12:47             ` Arnd Bergmann
2014-05-13 13:26               ` Kishon Vijay Abraham I
     [not found]                 ` <53721D7F.9070200-l0cyMroinI0@public.gmane.org>
2014-05-13 13:27                   ` Arnd Bergmann
2014-05-13 13:34                     ` Arnd Bergmann
2014-05-14  5:44                       ` Kishon Vijay Abraham I
2014-05-14 12:45                         ` Arnd Bergmann
2014-05-14 15:04                           ` Kishon Vijay Abraham I
2014-05-16  9:00                           ` Kishon Vijay Abraham I
2014-05-19 12:45                             ` Arnd Bergmann
     [not found] ` <1399383244-14556-1-git-send-email-kishon-l0cyMroinI0@public.gmane.org>
2014-05-06 13:33   ` [PATCH 02/17] phy: omap-control: add external clock support for PCIe PHY Kishon Vijay Abraham I
     [not found]     ` <1399383244-14556-3-git-send-email-kishon-l0cyMroinI0@public.gmane.org>
2014-05-14 13:02       ` Roger Quadros
2014-05-06 13:33   ` Kishon Vijay Abraham I [this message]
2014-05-14 13:16     ` [PATCH 03/17] phy: ti-pipe3: " Roger Quadros
2014-05-14 15:19       ` Kishon Vijay Abraham I
2014-05-14 15:34         ` Nishanth Menon
2014-05-15  9:15           ` Kishon Vijay Abraham I
2014-05-15  9:25             ` Roger Quadros
2014-05-15 11:46               ` Nishanth Menon
2014-05-15 11:59                 ` Kishon Vijay Abraham I
2014-05-15 12:12                   ` Nishanth Menon
2014-05-15 12:18                     ` Kishon Vijay Abraham I
2014-05-15 12:33                       ` Nishanth Menon
2014-05-15 12:42                         ` Kishon Vijay Abraham I
2014-05-27  6:11                         ` Kishon Vijay Abraham I
2014-05-28  1:54                         ` Mike Turquette
2014-05-28 15:52                           ` Nishanth Menon
2014-05-06 13:33   ` [PATCH 07/17] ARM: dts: DRA7: Add divider table to optfclk_pciephy_div clock Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 08/17] ARM: dts: DRA7: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 09/17] arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 10/17] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 11/17] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY Kishon Vijay Abraham I
     [not found]   ` <1399383244-14556-12-git-send-email-kishon-l0cyMroinI0@public.gmane.org>
2014-05-14 13:23     ` Roger Quadros
2014-05-14 15:19       ` Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 12/17] ARM: dts: dra7: Add dt data for PCIe PHY control module Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 13/17] ARM: dts: dra7: Add dt data for PCIe PHY Kishon Vijay Abraham I
2014-05-06 13:34 ` [PATCH 14/17] ARM: dts: dra7: Add dt data for PCIe controller Kishon Vijay Abraham I
2014-05-06 13:34 ` [PATCH 15/17] ARM: OMAP: Enable PCI for DRA7 Kishon Vijay Abraham I
2014-05-06 13:34 ` [TEMP PATCH 16/17] pci: host: pcie-dra7xx: use reset framework APIs to reset PCIe Kishon Vijay Abraham I
2014-05-06 13:41   ` Dan Murphy
2014-05-06 13:34 ` [TEMP PATCH 17/17] ARM: dts: dra7: Add *resets* property for PCIe dt node Kishon Vijay Abraham I
2014-05-06 13:40   ` Dan Murphy

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