* [PATCH] arm64: dts: qcom: sm6115: Set up CPU cooling maps @ 2023-04-18 11:56 Konrad Dybcio 2023-04-18 13:02 ` Bjorn Andersson 0 siblings, 1 reply; 6+ messages in thread From: Konrad Dybcio @ 2023-04-18 11:56 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: Marijn Suijten, linux-arm-msm, devicetree, linux-kernel, Konrad Dybcio Set up CPU cooling maps to ensure the thermal framework is aware of the connection between the CPUs and the TSENS sensors. All of the maps refer to all 4 CPUs within a given cluster at a time, as that's what can be considered the smallest DVFS target unit - they all share the same voltage line and clock source. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 137 +++++++++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 631ca327e064..36ff913c1a60 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -12,6 +12,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&intc>; @@ -47,6 +48,8 @@ CPU0: cpu@0 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; + L2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -63,6 +66,7 @@ CPU1: cpu@1 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; }; CPU2: cpu@2 { @@ -75,6 +79,7 @@ CPU2: cpu@2 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; }; CPU3: cpu@3 { @@ -87,6 +92,7 @@ CPU3: cpu@3 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; }; CPU4: cpu@100 { @@ -99,6 +105,8 @@ CPU4: cpu@100 { dynamic-power-coefficient = <282>; next-level-cache = <&L2_1>; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; + L2_1: l2-cache { compatible = "cache"; cache-level = <2>; @@ -115,6 +123,7 @@ CPU5: cpu@101 { enable-method = "psci"; next-level-cache = <&L2_1>; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; }; CPU6: cpu@102 { @@ -127,6 +136,7 @@ CPU6: cpu@102 { enable-method = "psci"; next-level-cache = <&L2_1>; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; }; CPU7: cpu@103 { @@ -139,6 +149,7 @@ CPU7: cpu@103 { enable-method = "psci"; next-level-cache = <&L2_1>; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; }; cpu-map { @@ -2471,6 +2482,24 @@ cpu4-thermal { polling-delay = <0>; thermal-sensors = <&tsens0 6>; + cooling-maps { + map0 { + trip = <&cpu4_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&cpu4_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { cpu4_alert0: trip-point0 { temperature = <90000>; @@ -2497,6 +2526,24 @@ cpu5-thermal { polling-delay = <0>; thermal-sensors = <&tsens0 7>; + cooling-maps { + map0 { + trip = <&cpu5_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&cpu5_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { cpu5_alert0: trip-point0 { temperature = <90000>; @@ -2523,6 +2570,24 @@ cpu6-thermal { polling-delay = <0>; thermal-sensors = <&tsens0 8>; + cooling-maps { + map0 { + trip = <&cpu6_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&cpu6_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { cpu6_alert0: trip-point0 { temperature = <90000>; @@ -2549,6 +2614,24 @@ cpu7-thermal { polling-delay = <0>; thermal-sensors = <&tsens0 9>; + cooling-maps { + map0 { + trip = <&cpu7_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&cpu7_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { cpu7_alert0: trip-point0 { temperature = <90000>; @@ -2575,6 +2658,24 @@ cpu45-thermal { polling-delay = <0>; thermal-sensors = <&tsens0 10>; + cooling-maps { + map0 { + trip = <&cpu45_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&cpu45_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { cpu45_alert0: trip-point0 { temperature = <90000>; @@ -2601,6 +2702,24 @@ cpu67-thermal { polling-delay = <0>; thermal-sensors = <&tsens0 11>; + cooling-maps { + map0 { + trip = <&cpu67_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&cpu67_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { cpu67_alert0: trip-point0 { temperature = <90000>; @@ -2627,6 +2746,24 @@ cpu0123-thermal { polling-delay = <0>; thermal-sensors = <&tsens0 12>; + cooling-maps { + map0 { + trip = <&cpu0123_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&cpu0123_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { cpu0123_alert0: trip-point0 { temperature = <90000>; --- base-commit: 4aa1da8d99724f6c0b762b58a71cee7c5e2e109b change-id: 20230418-topic-cool_bengal-2f5f3f47269c Best regards, -- Konrad Dybcio <konrad.dybcio@linaro.org> ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: dts: qcom: sm6115: Set up CPU cooling maps 2023-04-18 11:56 [PATCH] arm64: dts: qcom: sm6115: Set up CPU cooling maps Konrad Dybcio @ 2023-04-18 13:02 ` Bjorn Andersson 2023-04-18 13:01 ` Konrad Dybcio 0 siblings, 1 reply; 6+ messages in thread From: Bjorn Andersson @ 2023-04-18 13:02 UTC (permalink / raw) To: Konrad Dybcio Cc: Andy Gross, Rob Herring, Krzysztof Kozlowski, Marijn Suijten, linux-arm-msm, devicetree, linux-kernel On Tue, Apr 18, 2023 at 01:56:56PM +0200, Konrad Dybcio wrote: > Set up CPU cooling maps to ensure the thermal framework is aware of > the connection between the CPUs and the TSENS sensors. > > All of the maps refer to all 4 CPUs within a given cluster at a time, > as that's what can be considered the smallest DVFS target unit - they > all share the same voltage line and clock source. > Generally software based CPU cooling is considered too slow to cope with CPU core temperature changes, and the limits hardware working together with OSM/EPSS will do a better job maintaining appropriate core temperature levels. Is there a reason why this can't be used/relied upon on this platform? PS. Amending this mechanism with software based cooling to keep the system at a reasonable/lower temperature is a good idea. Regards, Bjorn > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm6115.dtsi | 137 +++++++++++++++++++++++++++++++++++ > 1 file changed, 137 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi > index 631ca327e064..36ff913c1a60 100644 > --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi > @@ -12,6 +12,7 @@ > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/power/qcom-rpmpd.h> > +#include <dt-bindings/thermal/thermal.h> > > / { > interrupt-parent = <&intc>; > @@ -47,6 +48,8 @@ CPU0: cpu@0 { > enable-method = "psci"; > next-level-cache = <&L2_0>; > qcom,freq-domain = <&cpufreq_hw 0>; > + #cooling-cells = <2>; > + > L2_0: l2-cache { > compatible = "cache"; > cache-level = <2>; > @@ -63,6 +66,7 @@ CPU1: cpu@1 { > enable-method = "psci"; > next-level-cache = <&L2_0>; > qcom,freq-domain = <&cpufreq_hw 0>; > + #cooling-cells = <2>; > }; > > CPU2: cpu@2 { > @@ -75,6 +79,7 @@ CPU2: cpu@2 { > enable-method = "psci"; > next-level-cache = <&L2_0>; > qcom,freq-domain = <&cpufreq_hw 0>; > + #cooling-cells = <2>; > }; > > CPU3: cpu@3 { > @@ -87,6 +92,7 @@ CPU3: cpu@3 { > enable-method = "psci"; > next-level-cache = <&L2_0>; > qcom,freq-domain = <&cpufreq_hw 0>; > + #cooling-cells = <2>; > }; > > CPU4: cpu@100 { > @@ -99,6 +105,8 @@ CPU4: cpu@100 { > dynamic-power-coefficient = <282>; > next-level-cache = <&L2_1>; > qcom,freq-domain = <&cpufreq_hw 1>; > + #cooling-cells = <2>; > + > L2_1: l2-cache { > compatible = "cache"; > cache-level = <2>; > @@ -115,6 +123,7 @@ CPU5: cpu@101 { > enable-method = "psci"; > next-level-cache = <&L2_1>; > qcom,freq-domain = <&cpufreq_hw 1>; > + #cooling-cells = <2>; > }; > > CPU6: cpu@102 { > @@ -127,6 +136,7 @@ CPU6: cpu@102 { > enable-method = "psci"; > next-level-cache = <&L2_1>; > qcom,freq-domain = <&cpufreq_hw 1>; > + #cooling-cells = <2>; > }; > > CPU7: cpu@103 { > @@ -139,6 +149,7 @@ CPU7: cpu@103 { > enable-method = "psci"; > next-level-cache = <&L2_1>; > qcom,freq-domain = <&cpufreq_hw 1>; > + #cooling-cells = <2>; > }; > > cpu-map { > @@ -2471,6 +2482,24 @@ cpu4-thermal { > polling-delay = <0>; > thermal-sensors = <&tsens0 6>; > > + cooling-maps { > + map0 { > + trip = <&cpu4_alert0>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + > + map1 { > + trip = <&cpu4_alert1>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + > trips { > cpu4_alert0: trip-point0 { > temperature = <90000>; > @@ -2497,6 +2526,24 @@ cpu5-thermal { > polling-delay = <0>; > thermal-sensors = <&tsens0 7>; > > + cooling-maps { > + map0 { > + trip = <&cpu5_alert0>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + > + map1 { > + trip = <&cpu5_alert1>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + > trips { > cpu5_alert0: trip-point0 { > temperature = <90000>; > @@ -2523,6 +2570,24 @@ cpu6-thermal { > polling-delay = <0>; > thermal-sensors = <&tsens0 8>; > > + cooling-maps { > + map0 { > + trip = <&cpu6_alert0>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + > + map1 { > + trip = <&cpu6_alert1>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + > trips { > cpu6_alert0: trip-point0 { > temperature = <90000>; > @@ -2549,6 +2614,24 @@ cpu7-thermal { > polling-delay = <0>; > thermal-sensors = <&tsens0 9>; > > + cooling-maps { > + map0 { > + trip = <&cpu7_alert0>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + > + map1 { > + trip = <&cpu7_alert1>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + > trips { > cpu7_alert0: trip-point0 { > temperature = <90000>; > @@ -2575,6 +2658,24 @@ cpu45-thermal { > polling-delay = <0>; > thermal-sensors = <&tsens0 10>; > > + cooling-maps { > + map0 { > + trip = <&cpu45_alert0>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + > + map1 { > + trip = <&cpu45_alert1>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + > trips { > cpu45_alert0: trip-point0 { > temperature = <90000>; > @@ -2601,6 +2702,24 @@ cpu67-thermal { > polling-delay = <0>; > thermal-sensors = <&tsens0 11>; > > + cooling-maps { > + map0 { > + trip = <&cpu67_alert0>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + > + map1 { > + trip = <&cpu67_alert1>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + > trips { > cpu67_alert0: trip-point0 { > temperature = <90000>; > @@ -2627,6 +2746,24 @@ cpu0123-thermal { > polling-delay = <0>; > thermal-sensors = <&tsens0 12>; > > + cooling-maps { > + map0 { > + trip = <&cpu0123_alert0>; > + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + > + map1 { > + trip = <&cpu0123_alert1>; > + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + > trips { > cpu0123_alert0: trip-point0 { > temperature = <90000>; > > --- > base-commit: 4aa1da8d99724f6c0b762b58a71cee7c5e2e109b > change-id: 20230418-topic-cool_bengal-2f5f3f47269c > > Best regards, > -- > Konrad Dybcio <konrad.dybcio@linaro.org> > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: dts: qcom: sm6115: Set up CPU cooling maps 2023-04-18 13:02 ` Bjorn Andersson @ 2023-04-18 13:01 ` Konrad Dybcio 2023-04-18 15:51 ` Bjorn Andersson 0 siblings, 1 reply; 6+ messages in thread From: Konrad Dybcio @ 2023-04-18 13:01 UTC (permalink / raw) To: Bjorn Andersson Cc: Andy Gross, Rob Herring, Krzysztof Kozlowski, Marijn Suijten, linux-arm-msm, devicetree, linux-kernel On 18.04.2023 15:02, Bjorn Andersson wrote: > On Tue, Apr 18, 2023 at 01:56:56PM +0200, Konrad Dybcio wrote: >> Set up CPU cooling maps to ensure the thermal framework is aware of >> the connection between the CPUs and the TSENS sensors. >> >> All of the maps refer to all 4 CPUs within a given cluster at a time, >> as that's what can be considered the smallest DVFS target unit - they >> all share the same voltage line and clock source. >> > > Generally software based CPU cooling is considered too slow to cope with > CPU core temperature changes, and the limits hardware working together > with OSM/EPSS will do a better job maintaining appropriate core > temperature levels. > > Is there a reason why this can't be used/relied upon on this platform? I haven't set up LMH yet and the default limits, at least with my dubious meta build, seem to let the board go to 75degC with just 4 cores working.. Not sure if there's a voltage droop when I let it go full throttle or something, but pushing it to the limit definitely causes the board to be (even) less stable.. > > > PS. Amending this mechanism with software based cooling to keep the > system at a reasonable/lower temperature is a good idea. We don't like burned chips around here! Konrad > > Regards, > Bjorn > >> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> >> --- >> arch/arm64/boot/dts/qcom/sm6115.dtsi | 137 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 137 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi >> index 631ca327e064..36ff913c1a60 100644 >> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi >> @@ -12,6 +12,7 @@ >> #include <dt-bindings/gpio/gpio.h> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> #include <dt-bindings/power/qcom-rpmpd.h> >> +#include <dt-bindings/thermal/thermal.h> >> >> / { >> interrupt-parent = <&intc>; >> @@ -47,6 +48,8 @@ CPU0: cpu@0 { >> enable-method = "psci"; >> next-level-cache = <&L2_0>; >> qcom,freq-domain = <&cpufreq_hw 0>; >> + #cooling-cells = <2>; >> + >> L2_0: l2-cache { >> compatible = "cache"; >> cache-level = <2>; >> @@ -63,6 +66,7 @@ CPU1: cpu@1 { >> enable-method = "psci"; >> next-level-cache = <&L2_0>; >> qcom,freq-domain = <&cpufreq_hw 0>; >> + #cooling-cells = <2>; >> }; >> >> CPU2: cpu@2 { >> @@ -75,6 +79,7 @@ CPU2: cpu@2 { >> enable-method = "psci"; >> next-level-cache = <&L2_0>; >> qcom,freq-domain = <&cpufreq_hw 0>; >> + #cooling-cells = <2>; >> }; >> >> CPU3: cpu@3 { >> @@ -87,6 +92,7 @@ CPU3: cpu@3 { >> enable-method = "psci"; >> next-level-cache = <&L2_0>; >> qcom,freq-domain = <&cpufreq_hw 0>; >> + #cooling-cells = <2>; >> }; >> >> CPU4: cpu@100 { >> @@ -99,6 +105,8 @@ CPU4: cpu@100 { >> dynamic-power-coefficient = <282>; >> next-level-cache = <&L2_1>; >> qcom,freq-domain = <&cpufreq_hw 1>; >> + #cooling-cells = <2>; >> + >> L2_1: l2-cache { >> compatible = "cache"; >> cache-level = <2>; >> @@ -115,6 +123,7 @@ CPU5: cpu@101 { >> enable-method = "psci"; >> next-level-cache = <&L2_1>; >> qcom,freq-domain = <&cpufreq_hw 1>; >> + #cooling-cells = <2>; >> }; >> >> CPU6: cpu@102 { >> @@ -127,6 +136,7 @@ CPU6: cpu@102 { >> enable-method = "psci"; >> next-level-cache = <&L2_1>; >> qcom,freq-domain = <&cpufreq_hw 1>; >> + #cooling-cells = <2>; >> }; >> >> CPU7: cpu@103 { >> @@ -139,6 +149,7 @@ CPU7: cpu@103 { >> enable-method = "psci"; >> next-level-cache = <&L2_1>; >> qcom,freq-domain = <&cpufreq_hw 1>; >> + #cooling-cells = <2>; >> }; >> >> cpu-map { >> @@ -2471,6 +2482,24 @@ cpu4-thermal { >> polling-delay = <0>; >> thermal-sensors = <&tsens0 6>; >> >> + cooling-maps { >> + map0 { >> + trip = <&cpu4_alert0>; >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >> + }; >> + >> + map1 { >> + trip = <&cpu4_alert1>; >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >> + }; >> + }; >> + >> trips { >> cpu4_alert0: trip-point0 { >> temperature = <90000>; >> @@ -2497,6 +2526,24 @@ cpu5-thermal { >> polling-delay = <0>; >> thermal-sensors = <&tsens0 7>; >> >> + cooling-maps { >> + map0 { >> + trip = <&cpu5_alert0>; >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >> + }; >> + >> + map1 { >> + trip = <&cpu5_alert1>; >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >> + }; >> + }; >> + >> trips { >> cpu5_alert0: trip-point0 { >> temperature = <90000>; >> @@ -2523,6 +2570,24 @@ cpu6-thermal { >> polling-delay = <0>; >> thermal-sensors = <&tsens0 8>; >> >> + cooling-maps { >> + map0 { >> + trip = <&cpu6_alert0>; >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >> + }; >> + >> + map1 { >> + trip = <&cpu6_alert1>; >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >> + }; >> + }; >> + >> trips { >> cpu6_alert0: trip-point0 { >> temperature = <90000>; >> @@ -2549,6 +2614,24 @@ cpu7-thermal { >> polling-delay = <0>; >> thermal-sensors = <&tsens0 9>; >> >> + cooling-maps { >> + map0 { >> + trip = <&cpu7_alert0>; >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >> + }; >> + >> + map1 { >> + trip = <&cpu7_alert1>; >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >> + }; >> + }; >> + >> trips { >> cpu7_alert0: trip-point0 { >> temperature = <90000>; >> @@ -2575,6 +2658,24 @@ cpu45-thermal { >> polling-delay = <0>; >> thermal-sensors = <&tsens0 10>; >> >> + cooling-maps { >> + map0 { >> + trip = <&cpu45_alert0>; >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >> + }; >> + >> + map1 { >> + trip = <&cpu45_alert1>; >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >> + }; >> + }; >> + >> trips { >> cpu45_alert0: trip-point0 { >> temperature = <90000>; >> @@ -2601,6 +2702,24 @@ cpu67-thermal { >> polling-delay = <0>; >> thermal-sensors = <&tsens0 11>; >> >> + cooling-maps { >> + map0 { >> + trip = <&cpu67_alert0>; >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >> + }; >> + >> + map1 { >> + trip = <&cpu67_alert1>; >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >> + }; >> + }; >> + >> trips { >> cpu67_alert0: trip-point0 { >> temperature = <90000>; >> @@ -2627,6 +2746,24 @@ cpu0123-thermal { >> polling-delay = <0>; >> thermal-sensors = <&tsens0 12>; >> >> + cooling-maps { >> + map0 { >> + trip = <&cpu0123_alert0>; >> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >> + }; >> + >> + map1 { >> + trip = <&cpu0123_alert1>; >> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >> + }; >> + }; >> + >> trips { >> cpu0123_alert0: trip-point0 { >> temperature = <90000>; >> >> --- >> base-commit: 4aa1da8d99724f6c0b762b58a71cee7c5e2e109b >> change-id: 20230418-topic-cool_bengal-2f5f3f47269c >> >> Best regards, >> -- >> Konrad Dybcio <konrad.dybcio@linaro.org> >> ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: dts: qcom: sm6115: Set up CPU cooling maps 2023-04-18 13:01 ` Konrad Dybcio @ 2023-04-18 15:51 ` Bjorn Andersson 2023-05-31 14:55 ` Konrad Dybcio 0 siblings, 1 reply; 6+ messages in thread From: Bjorn Andersson @ 2023-04-18 15:51 UTC (permalink / raw) To: Konrad Dybcio Cc: Andy Gross, Rob Herring, Krzysztof Kozlowski, Marijn Suijten, linux-arm-msm, devicetree, linux-kernel On Tue, Apr 18, 2023 at 03:01:47PM +0200, Konrad Dybcio wrote: > > > On 18.04.2023 15:02, Bjorn Andersson wrote: > > On Tue, Apr 18, 2023 at 01:56:56PM +0200, Konrad Dybcio wrote: > >> Set up CPU cooling maps to ensure the thermal framework is aware of > >> the connection between the CPUs and the TSENS sensors. > >> > >> All of the maps refer to all 4 CPUs within a given cluster at a time, > >> as that's what can be considered the smallest DVFS target unit - they > >> all share the same voltage line and clock source. > >> > > > > Generally software based CPU cooling is considered too slow to cope with > > CPU core temperature changes, and the limits hardware working together > > with OSM/EPSS will do a better job maintaining appropriate core > > temperature levels. > > > > Is there a reason why this can't be used/relied upon on this platform? > I haven't set up LMH yet and the default limits, at least with my dubious > meta build, seem to let the board go to 75degC with just 4 cores working.. > > Not sure if there's a voltage droop when I let it go full throttle or > something, but pushing it to the limit definitely causes the board to be > (even) less stable.. > > > > > > > PS. Amending this mechanism with software based cooling to keep the > > system at a reasonable/lower temperature is a good idea. > We don't like burned chips around here! > Limits hardware will help you with that, software based cooling will help avoid burning the user. Regards, Bjorn > Konrad > > > > Regards, > > Bjorn > > > >> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > >> --- > >> arch/arm64/boot/dts/qcom/sm6115.dtsi | 137 +++++++++++++++++++++++++++++++++++ > >> 1 file changed, 137 insertions(+) > >> > >> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi > >> index 631ca327e064..36ff913c1a60 100644 > >> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi > >> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi > >> @@ -12,6 +12,7 @@ > >> #include <dt-bindings/gpio/gpio.h> > >> #include <dt-bindings/interrupt-controller/arm-gic.h> > >> #include <dt-bindings/power/qcom-rpmpd.h> > >> +#include <dt-bindings/thermal/thermal.h> > >> > >> / { > >> interrupt-parent = <&intc>; > >> @@ -47,6 +48,8 @@ CPU0: cpu@0 { > >> enable-method = "psci"; > >> next-level-cache = <&L2_0>; > >> qcom,freq-domain = <&cpufreq_hw 0>; > >> + #cooling-cells = <2>; > >> + > >> L2_0: l2-cache { > >> compatible = "cache"; > >> cache-level = <2>; > >> @@ -63,6 +66,7 @@ CPU1: cpu@1 { > >> enable-method = "psci"; > >> next-level-cache = <&L2_0>; > >> qcom,freq-domain = <&cpufreq_hw 0>; > >> + #cooling-cells = <2>; > >> }; > >> > >> CPU2: cpu@2 { > >> @@ -75,6 +79,7 @@ CPU2: cpu@2 { > >> enable-method = "psci"; > >> next-level-cache = <&L2_0>; > >> qcom,freq-domain = <&cpufreq_hw 0>; > >> + #cooling-cells = <2>; > >> }; > >> > >> CPU3: cpu@3 { > >> @@ -87,6 +92,7 @@ CPU3: cpu@3 { > >> enable-method = "psci"; > >> next-level-cache = <&L2_0>; > >> qcom,freq-domain = <&cpufreq_hw 0>; > >> + #cooling-cells = <2>; > >> }; > >> > >> CPU4: cpu@100 { > >> @@ -99,6 +105,8 @@ CPU4: cpu@100 { > >> dynamic-power-coefficient = <282>; > >> next-level-cache = <&L2_1>; > >> qcom,freq-domain = <&cpufreq_hw 1>; > >> + #cooling-cells = <2>; > >> + > >> L2_1: l2-cache { > >> compatible = "cache"; > >> cache-level = <2>; > >> @@ -115,6 +123,7 @@ CPU5: cpu@101 { > >> enable-method = "psci"; > >> next-level-cache = <&L2_1>; > >> qcom,freq-domain = <&cpufreq_hw 1>; > >> + #cooling-cells = <2>; > >> }; > >> > >> CPU6: cpu@102 { > >> @@ -127,6 +136,7 @@ CPU6: cpu@102 { > >> enable-method = "psci"; > >> next-level-cache = <&L2_1>; > >> qcom,freq-domain = <&cpufreq_hw 1>; > >> + #cooling-cells = <2>; > >> }; > >> > >> CPU7: cpu@103 { > >> @@ -139,6 +149,7 @@ CPU7: cpu@103 { > >> enable-method = "psci"; > >> next-level-cache = <&L2_1>; > >> qcom,freq-domain = <&cpufreq_hw 1>; > >> + #cooling-cells = <2>; > >> }; > >> > >> cpu-map { > >> @@ -2471,6 +2482,24 @@ cpu4-thermal { > >> polling-delay = <0>; > >> thermal-sensors = <&tsens0 6>; > >> > >> + cooling-maps { > >> + map0 { > >> + trip = <&cpu4_alert0>; > >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > >> + }; > >> + > >> + map1 { > >> + trip = <&cpu4_alert1>; > >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > >> + }; > >> + }; > >> + > >> trips { > >> cpu4_alert0: trip-point0 { > >> temperature = <90000>; > >> @@ -2497,6 +2526,24 @@ cpu5-thermal { > >> polling-delay = <0>; > >> thermal-sensors = <&tsens0 7>; > >> > >> + cooling-maps { > >> + map0 { > >> + trip = <&cpu5_alert0>; > >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > >> + }; > >> + > >> + map1 { > >> + trip = <&cpu5_alert1>; > >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > >> + }; > >> + }; > >> + > >> trips { > >> cpu5_alert0: trip-point0 { > >> temperature = <90000>; > >> @@ -2523,6 +2570,24 @@ cpu6-thermal { > >> polling-delay = <0>; > >> thermal-sensors = <&tsens0 8>; > >> > >> + cooling-maps { > >> + map0 { > >> + trip = <&cpu6_alert0>; > >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > >> + }; > >> + > >> + map1 { > >> + trip = <&cpu6_alert1>; > >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > >> + }; > >> + }; > >> + > >> trips { > >> cpu6_alert0: trip-point0 { > >> temperature = <90000>; > >> @@ -2549,6 +2614,24 @@ cpu7-thermal { > >> polling-delay = <0>; > >> thermal-sensors = <&tsens0 9>; > >> > >> + cooling-maps { > >> + map0 { > >> + trip = <&cpu7_alert0>; > >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > >> + }; > >> + > >> + map1 { > >> + trip = <&cpu7_alert1>; > >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > >> + }; > >> + }; > >> + > >> trips { > >> cpu7_alert0: trip-point0 { > >> temperature = <90000>; > >> @@ -2575,6 +2658,24 @@ cpu45-thermal { > >> polling-delay = <0>; > >> thermal-sensors = <&tsens0 10>; > >> > >> + cooling-maps { > >> + map0 { > >> + trip = <&cpu45_alert0>; > >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > >> + }; > >> + > >> + map1 { > >> + trip = <&cpu45_alert1>; > >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > >> + }; > >> + }; > >> + > >> trips { > >> cpu45_alert0: trip-point0 { > >> temperature = <90000>; > >> @@ -2601,6 +2702,24 @@ cpu67-thermal { > >> polling-delay = <0>; > >> thermal-sensors = <&tsens0 11>; > >> > >> + cooling-maps { > >> + map0 { > >> + trip = <&cpu67_alert0>; > >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > >> + }; > >> + > >> + map1 { > >> + trip = <&cpu67_alert1>; > >> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > >> + }; > >> + }; > >> + > >> trips { > >> cpu67_alert0: trip-point0 { > >> temperature = <90000>; > >> @@ -2627,6 +2746,24 @@ cpu0123-thermal { > >> polling-delay = <0>; > >> thermal-sensors = <&tsens0 12>; > >> > >> + cooling-maps { > >> + map0 { > >> + trip = <&cpu0123_alert0>; > >> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > >> + }; > >> + > >> + map1 { > >> + trip = <&cpu0123_alert1>; > >> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > >> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > >> + }; > >> + }; > >> + > >> trips { > >> cpu0123_alert0: trip-point0 { > >> temperature = <90000>; > >> > >> --- > >> base-commit: 4aa1da8d99724f6c0b762b58a71cee7c5e2e109b > >> change-id: 20230418-topic-cool_bengal-2f5f3f47269c > >> > >> Best regards, > >> -- > >> Konrad Dybcio <konrad.dybcio@linaro.org> > >> ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: dts: qcom: sm6115: Set up CPU cooling maps 2023-04-18 15:51 ` Bjorn Andersson @ 2023-05-31 14:55 ` Konrad Dybcio 2023-06-20 13:19 ` Konrad Dybcio 0 siblings, 1 reply; 6+ messages in thread From: Konrad Dybcio @ 2023-05-31 14:55 UTC (permalink / raw) To: Bjorn Andersson Cc: Andy Gross, Rob Herring, Krzysztof Kozlowski, Marijn Suijten, linux-arm-msm, devicetree, linux-kernel On 18.04.2023 17:51, Bjorn Andersson wrote: > On Tue, Apr 18, 2023 at 03:01:47PM +0200, Konrad Dybcio wrote: >> >> >> On 18.04.2023 15:02, Bjorn Andersson wrote: >>> On Tue, Apr 18, 2023 at 01:56:56PM +0200, Konrad Dybcio wrote: >>>> Set up CPU cooling maps to ensure the thermal framework is aware of >>>> the connection between the CPUs and the TSENS sensors. >>>> >>>> All of the maps refer to all 4 CPUs within a given cluster at a time, >>>> as that's what can be considered the smallest DVFS target unit - they >>>> all share the same voltage line and clock source. >>>> >>> >>> Generally software based CPU cooling is considered too slow to cope with >>> CPU core temperature changes, and the limits hardware working together >>> with OSM/EPSS will do a better job maintaining appropriate core >>> temperature levels. >>> >>> Is there a reason why this can't be used/relied upon on this platform? >> I haven't set up LMH yet and the default limits, at least with my dubious >> meta build, seem to let the board go to 75degC with just 4 cores working.. >> >> Not sure if there's a voltage droop when I let it go full throttle or >> something, but pushing it to the limit definitely causes the board to be >> (even) less stable.. >> >>> >>> >>> PS. Amending this mechanism with software based cooling to keep the >>> system at a reasonable/lower temperature is a good idea. >> We don't like burned chips around here! >> > > Limits hardware will help you with that, software based cooling will > help avoid burning the user. So, are there any reasons not to take this patch? Konrad > > Regards, > Bjorn > >> Konrad >>> >>> Regards, >>> Bjorn >>> >>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> >>>> --- >>>> arch/arm64/boot/dts/qcom/sm6115.dtsi | 137 +++++++++++++++++++++++++++++++++++ >>>> 1 file changed, 137 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi >>>> index 631ca327e064..36ff913c1a60 100644 >>>> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi >>>> @@ -12,6 +12,7 @@ >>>> #include <dt-bindings/gpio/gpio.h> >>>> #include <dt-bindings/interrupt-controller/arm-gic.h> >>>> #include <dt-bindings/power/qcom-rpmpd.h> >>>> +#include <dt-bindings/thermal/thermal.h> >>>> >>>> / { >>>> interrupt-parent = <&intc>; >>>> @@ -47,6 +48,8 @@ CPU0: cpu@0 { >>>> enable-method = "psci"; >>>> next-level-cache = <&L2_0>; >>>> qcom,freq-domain = <&cpufreq_hw 0>; >>>> + #cooling-cells = <2>; >>>> + >>>> L2_0: l2-cache { >>>> compatible = "cache"; >>>> cache-level = <2>; >>>> @@ -63,6 +66,7 @@ CPU1: cpu@1 { >>>> enable-method = "psci"; >>>> next-level-cache = <&L2_0>; >>>> qcom,freq-domain = <&cpufreq_hw 0>; >>>> + #cooling-cells = <2>; >>>> }; >>>> >>>> CPU2: cpu@2 { >>>> @@ -75,6 +79,7 @@ CPU2: cpu@2 { >>>> enable-method = "psci"; >>>> next-level-cache = <&L2_0>; >>>> qcom,freq-domain = <&cpufreq_hw 0>; >>>> + #cooling-cells = <2>; >>>> }; >>>> >>>> CPU3: cpu@3 { >>>> @@ -87,6 +92,7 @@ CPU3: cpu@3 { >>>> enable-method = "psci"; >>>> next-level-cache = <&L2_0>; >>>> qcom,freq-domain = <&cpufreq_hw 0>; >>>> + #cooling-cells = <2>; >>>> }; >>>> >>>> CPU4: cpu@100 { >>>> @@ -99,6 +105,8 @@ CPU4: cpu@100 { >>>> dynamic-power-coefficient = <282>; >>>> next-level-cache = <&L2_1>; >>>> qcom,freq-domain = <&cpufreq_hw 1>; >>>> + #cooling-cells = <2>; >>>> + >>>> L2_1: l2-cache { >>>> compatible = "cache"; >>>> cache-level = <2>; >>>> @@ -115,6 +123,7 @@ CPU5: cpu@101 { >>>> enable-method = "psci"; >>>> next-level-cache = <&L2_1>; >>>> qcom,freq-domain = <&cpufreq_hw 1>; >>>> + #cooling-cells = <2>; >>>> }; >>>> >>>> CPU6: cpu@102 { >>>> @@ -127,6 +136,7 @@ CPU6: cpu@102 { >>>> enable-method = "psci"; >>>> next-level-cache = <&L2_1>; >>>> qcom,freq-domain = <&cpufreq_hw 1>; >>>> + #cooling-cells = <2>; >>>> }; >>>> >>>> CPU7: cpu@103 { >>>> @@ -139,6 +149,7 @@ CPU7: cpu@103 { >>>> enable-method = "psci"; >>>> next-level-cache = <&L2_1>; >>>> qcom,freq-domain = <&cpufreq_hw 1>; >>>> + #cooling-cells = <2>; >>>> }; >>>> >>>> cpu-map { >>>> @@ -2471,6 +2482,24 @@ cpu4-thermal { >>>> polling-delay = <0>; >>>> thermal-sensors = <&tsens0 6>; >>>> >>>> + cooling-maps { >>>> + map0 { >>>> + trip = <&cpu4_alert0>; >>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>> + }; >>>> + >>>> + map1 { >>>> + trip = <&cpu4_alert1>; >>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>> + }; >>>> + }; >>>> + >>>> trips { >>>> cpu4_alert0: trip-point0 { >>>> temperature = <90000>; >>>> @@ -2497,6 +2526,24 @@ cpu5-thermal { >>>> polling-delay = <0>; >>>> thermal-sensors = <&tsens0 7>; >>>> >>>> + cooling-maps { >>>> + map0 { >>>> + trip = <&cpu5_alert0>; >>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>> + }; >>>> + >>>> + map1 { >>>> + trip = <&cpu5_alert1>; >>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>> + }; >>>> + }; >>>> + >>>> trips { >>>> cpu5_alert0: trip-point0 { >>>> temperature = <90000>; >>>> @@ -2523,6 +2570,24 @@ cpu6-thermal { >>>> polling-delay = <0>; >>>> thermal-sensors = <&tsens0 8>; >>>> >>>> + cooling-maps { >>>> + map0 { >>>> + trip = <&cpu6_alert0>; >>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>> + }; >>>> + >>>> + map1 { >>>> + trip = <&cpu6_alert1>; >>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>> + }; >>>> + }; >>>> + >>>> trips { >>>> cpu6_alert0: trip-point0 { >>>> temperature = <90000>; >>>> @@ -2549,6 +2614,24 @@ cpu7-thermal { >>>> polling-delay = <0>; >>>> thermal-sensors = <&tsens0 9>; >>>> >>>> + cooling-maps { >>>> + map0 { >>>> + trip = <&cpu7_alert0>; >>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>> + }; >>>> + >>>> + map1 { >>>> + trip = <&cpu7_alert1>; >>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>> + }; >>>> + }; >>>> + >>>> trips { >>>> cpu7_alert0: trip-point0 { >>>> temperature = <90000>; >>>> @@ -2575,6 +2658,24 @@ cpu45-thermal { >>>> polling-delay = <0>; >>>> thermal-sensors = <&tsens0 10>; >>>> >>>> + cooling-maps { >>>> + map0 { >>>> + trip = <&cpu45_alert0>; >>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>> + }; >>>> + >>>> + map1 { >>>> + trip = <&cpu45_alert1>; >>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>> + }; >>>> + }; >>>> + >>>> trips { >>>> cpu45_alert0: trip-point0 { >>>> temperature = <90000>; >>>> @@ -2601,6 +2702,24 @@ cpu67-thermal { >>>> polling-delay = <0>; >>>> thermal-sensors = <&tsens0 11>; >>>> >>>> + cooling-maps { >>>> + map0 { >>>> + trip = <&cpu67_alert0>; >>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>> + }; >>>> + >>>> + map1 { >>>> + trip = <&cpu67_alert1>; >>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>> + }; >>>> + }; >>>> + >>>> trips { >>>> cpu67_alert0: trip-point0 { >>>> temperature = <90000>; >>>> @@ -2627,6 +2746,24 @@ cpu0123-thermal { >>>> polling-delay = <0>; >>>> thermal-sensors = <&tsens0 12>; >>>> >>>> + cooling-maps { >>>> + map0 { >>>> + trip = <&cpu0123_alert0>; >>>> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>> + }; >>>> + >>>> + map1 { >>>> + trip = <&cpu0123_alert1>; >>>> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>> + }; >>>> + }; >>>> + >>>> trips { >>>> cpu0123_alert0: trip-point0 { >>>> temperature = <90000>; >>>> >>>> --- >>>> base-commit: 4aa1da8d99724f6c0b762b58a71cee7c5e2e109b >>>> change-id: 20230418-topic-cool_bengal-2f5f3f47269c >>>> >>>> Best regards, >>>> -- >>>> Konrad Dybcio <konrad.dybcio@linaro.org> >>>> ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: dts: qcom: sm6115: Set up CPU cooling maps 2023-05-31 14:55 ` Konrad Dybcio @ 2023-06-20 13:19 ` Konrad Dybcio 0 siblings, 0 replies; 6+ messages in thread From: Konrad Dybcio @ 2023-06-20 13:19 UTC (permalink / raw) To: Bjorn Andersson Cc: Andy Gross, Rob Herring, Krzysztof Kozlowski, Marijn Suijten, linux-arm-msm, devicetree, linux-kernel On 31.05.2023 16:55, Konrad Dybcio wrote: > > > On 18.04.2023 17:51, Bjorn Andersson wrote: >> On Tue, Apr 18, 2023 at 03:01:47PM +0200, Konrad Dybcio wrote: >>> >>> >>> On 18.04.2023 15:02, Bjorn Andersson wrote: >>>> On Tue, Apr 18, 2023 at 01:56:56PM +0200, Konrad Dybcio wrote: >>>>> Set up CPU cooling maps to ensure the thermal framework is aware of >>>>> the connection between the CPUs and the TSENS sensors. >>>>> >>>>> All of the maps refer to all 4 CPUs within a given cluster at a time, >>>>> as that's what can be considered the smallest DVFS target unit - they >>>>> all share the same voltage line and clock source. >>>>> >>>> >>>> Generally software based CPU cooling is considered too slow to cope with >>>> CPU core temperature changes, and the limits hardware working together >>>> with OSM/EPSS will do a better job maintaining appropriate core >>>> temperature levels. >>>> >>>> Is there a reason why this can't be used/relied upon on this platform? >>> I haven't set up LMH yet and the default limits, at least with my dubious >>> meta build, seem to let the board go to 75degC with just 4 cores working.. >>> >>> Not sure if there's a voltage droop when I let it go full throttle or >>> something, but pushing it to the limit definitely causes the board to be >>> (even) less stable.. >>> >>>> >>>> >>>> PS. Amending this mechanism with software based cooling to keep the >>>> system at a reasonable/lower temperature is a good idea. >>> We don't like burned chips around here! >>> >> >> Limits hardware will help you with that, software based cooling will >> help avoid burning the user. > So, are there any reasons not to take this patch? Bump Konrad > > Konrad >> >> Regards, >> Bjorn >> >>> Konrad >>>> >>>> Regards, >>>> Bjorn >>>> >>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> >>>>> --- >>>>> arch/arm64/boot/dts/qcom/sm6115.dtsi | 137 +++++++++++++++++++++++++++++++++++ >>>>> 1 file changed, 137 insertions(+) >>>>> >>>>> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi >>>>> index 631ca327e064..36ff913c1a60 100644 >>>>> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi >>>>> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi >>>>> @@ -12,6 +12,7 @@ >>>>> #include <dt-bindings/gpio/gpio.h> >>>>> #include <dt-bindings/interrupt-controller/arm-gic.h> >>>>> #include <dt-bindings/power/qcom-rpmpd.h> >>>>> +#include <dt-bindings/thermal/thermal.h> >>>>> >>>>> / { >>>>> interrupt-parent = <&intc>; >>>>> @@ -47,6 +48,8 @@ CPU0: cpu@0 { >>>>> enable-method = "psci"; >>>>> next-level-cache = <&L2_0>; >>>>> qcom,freq-domain = <&cpufreq_hw 0>; >>>>> + #cooling-cells = <2>; >>>>> + >>>>> L2_0: l2-cache { >>>>> compatible = "cache"; >>>>> cache-level = <2>; >>>>> @@ -63,6 +66,7 @@ CPU1: cpu@1 { >>>>> enable-method = "psci"; >>>>> next-level-cache = <&L2_0>; >>>>> qcom,freq-domain = <&cpufreq_hw 0>; >>>>> + #cooling-cells = <2>; >>>>> }; >>>>> >>>>> CPU2: cpu@2 { >>>>> @@ -75,6 +79,7 @@ CPU2: cpu@2 { >>>>> enable-method = "psci"; >>>>> next-level-cache = <&L2_0>; >>>>> qcom,freq-domain = <&cpufreq_hw 0>; >>>>> + #cooling-cells = <2>; >>>>> }; >>>>> >>>>> CPU3: cpu@3 { >>>>> @@ -87,6 +92,7 @@ CPU3: cpu@3 { >>>>> enable-method = "psci"; >>>>> next-level-cache = <&L2_0>; >>>>> qcom,freq-domain = <&cpufreq_hw 0>; >>>>> + #cooling-cells = <2>; >>>>> }; >>>>> >>>>> CPU4: cpu@100 { >>>>> @@ -99,6 +105,8 @@ CPU4: cpu@100 { >>>>> dynamic-power-coefficient = <282>; >>>>> next-level-cache = <&L2_1>; >>>>> qcom,freq-domain = <&cpufreq_hw 1>; >>>>> + #cooling-cells = <2>; >>>>> + >>>>> L2_1: l2-cache { >>>>> compatible = "cache"; >>>>> cache-level = <2>; >>>>> @@ -115,6 +123,7 @@ CPU5: cpu@101 { >>>>> enable-method = "psci"; >>>>> next-level-cache = <&L2_1>; >>>>> qcom,freq-domain = <&cpufreq_hw 1>; >>>>> + #cooling-cells = <2>; >>>>> }; >>>>> >>>>> CPU6: cpu@102 { >>>>> @@ -127,6 +136,7 @@ CPU6: cpu@102 { >>>>> enable-method = "psci"; >>>>> next-level-cache = <&L2_1>; >>>>> qcom,freq-domain = <&cpufreq_hw 1>; >>>>> + #cooling-cells = <2>; >>>>> }; >>>>> >>>>> CPU7: cpu@103 { >>>>> @@ -139,6 +149,7 @@ CPU7: cpu@103 { >>>>> enable-method = "psci"; >>>>> next-level-cache = <&L2_1>; >>>>> qcom,freq-domain = <&cpufreq_hw 1>; >>>>> + #cooling-cells = <2>; >>>>> }; >>>>> >>>>> cpu-map { >>>>> @@ -2471,6 +2482,24 @@ cpu4-thermal { >>>>> polling-delay = <0>; >>>>> thermal-sensors = <&tsens0 6>; >>>>> >>>>> + cooling-maps { >>>>> + map0 { >>>>> + trip = <&cpu4_alert0>; >>>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>>> + }; >>>>> + >>>>> + map1 { >>>>> + trip = <&cpu4_alert1>; >>>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>>> + }; >>>>> + }; >>>>> + >>>>> trips { >>>>> cpu4_alert0: trip-point0 { >>>>> temperature = <90000>; >>>>> @@ -2497,6 +2526,24 @@ cpu5-thermal { >>>>> polling-delay = <0>; >>>>> thermal-sensors = <&tsens0 7>; >>>>> >>>>> + cooling-maps { >>>>> + map0 { >>>>> + trip = <&cpu5_alert0>; >>>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>>> + }; >>>>> + >>>>> + map1 { >>>>> + trip = <&cpu5_alert1>; >>>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>>> + }; >>>>> + }; >>>>> + >>>>> trips { >>>>> cpu5_alert0: trip-point0 { >>>>> temperature = <90000>; >>>>> @@ -2523,6 +2570,24 @@ cpu6-thermal { >>>>> polling-delay = <0>; >>>>> thermal-sensors = <&tsens0 8>; >>>>> >>>>> + cooling-maps { >>>>> + map0 { >>>>> + trip = <&cpu6_alert0>; >>>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>>> + }; >>>>> + >>>>> + map1 { >>>>> + trip = <&cpu6_alert1>; >>>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>>> + }; >>>>> + }; >>>>> + >>>>> trips { >>>>> cpu6_alert0: trip-point0 { >>>>> temperature = <90000>; >>>>> @@ -2549,6 +2614,24 @@ cpu7-thermal { >>>>> polling-delay = <0>; >>>>> thermal-sensors = <&tsens0 9>; >>>>> >>>>> + cooling-maps { >>>>> + map0 { >>>>> + trip = <&cpu7_alert0>; >>>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>>> + }; >>>>> + >>>>> + map1 { >>>>> + trip = <&cpu7_alert1>; >>>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>>> + }; >>>>> + }; >>>>> + >>>>> trips { >>>>> cpu7_alert0: trip-point0 { >>>>> temperature = <90000>; >>>>> @@ -2575,6 +2658,24 @@ cpu45-thermal { >>>>> polling-delay = <0>; >>>>> thermal-sensors = <&tsens0 10>; >>>>> >>>>> + cooling-maps { >>>>> + map0 { >>>>> + trip = <&cpu45_alert0>; >>>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>>> + }; >>>>> + >>>>> + map1 { >>>>> + trip = <&cpu45_alert1>; >>>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>>> + }; >>>>> + }; >>>>> + >>>>> trips { >>>>> cpu45_alert0: trip-point0 { >>>>> temperature = <90000>; >>>>> @@ -2601,6 +2702,24 @@ cpu67-thermal { >>>>> polling-delay = <0>; >>>>> thermal-sensors = <&tsens0 11>; >>>>> >>>>> + cooling-maps { >>>>> + map0 { >>>>> + trip = <&cpu67_alert0>; >>>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>>> + }; >>>>> + >>>>> + map1 { >>>>> + trip = <&cpu67_alert1>; >>>>> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>>> + }; >>>>> + }; >>>>> + >>>>> trips { >>>>> cpu67_alert0: trip-point0 { >>>>> temperature = <90000>; >>>>> @@ -2627,6 +2746,24 @@ cpu0123-thermal { >>>>> polling-delay = <0>; >>>>> thermal-sensors = <&tsens0 12>; >>>>> >>>>> + cooling-maps { >>>>> + map0 { >>>>> + trip = <&cpu0123_alert0>; >>>>> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>>> + }; >>>>> + >>>>> + map1 { >>>>> + trip = <&cpu0123_alert1>; >>>>> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, >>>>> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; >>>>> + }; >>>>> + }; >>>>> + >>>>> trips { >>>>> cpu0123_alert0: trip-point0 { >>>>> temperature = <90000>; >>>>> >>>>> --- >>>>> base-commit: 4aa1da8d99724f6c0b762b58a71cee7c5e2e109b >>>>> change-id: 20230418-topic-cool_bengal-2f5f3f47269c >>>>> >>>>> Best regards, >>>>> -- >>>>> Konrad Dybcio <konrad.dybcio@linaro.org> >>>>> ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-06-20 13:21 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-04-18 11:56 [PATCH] arm64: dts: qcom: sm6115: Set up CPU cooling maps Konrad Dybcio 2023-04-18 13:02 ` Bjorn Andersson 2023-04-18 13:01 ` Konrad Dybcio 2023-04-18 15:51 ` Bjorn Andersson 2023-05-31 14:55 ` Konrad Dybcio 2023-06-20 13:19 ` Konrad Dybcio
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).