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Tue, 23 Sep 2025 14:51:37 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: A0nVfrWCY5as Date: Tue, 23 Sep 2025 20:51:15 +0200 From: "Arnd Bergmann" To: "Manikanta Guntupalli" , git@amd.com, "Michal Simek" , "Alexandre Belloni" , "Frank Li" , "Rob Herring" , krzk+dt@kernel.org, "Conor Dooley" , =?UTF-8?Q?Przemys=C5=82aw_Gaj?= , "Wolfram Sang" , tommaso.merciai.xr@bp.renesas.com, quic_msavaliy@quicinc.com, Shyam-sundar.S-k@amd.com, "Sakari Ailus" , "'billy_tsai@aspeedtech.com'" , "Kees Cook" , "Gustavo A. R. Silva" , "Jarkko Nikula" , "Jorge Marques" , "linux-i3c@lists.infradead.org" , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Linux-Arch , linux-hardening@vger.kernel.org Cc: radhey.shyam.pandey@amd.com, srinivas.goud@amd.com, shubhrajyoti.datta@amd.com, manion05gk@gmail.com Message-Id: <13bbd85e-48d2-4163-b9f1-2a2a870d4322@app.fastmail.com> In-Reply-To: <20250923154551.2112388-4-manikanta.guntupalli@amd.com> References: <20250923154551.2112388-1-manikanta.guntupalli@amd.com> <20250923154551.2112388-4-manikanta.guntupalli@amd.com> Subject: Re: [PATCH V7 3/4] i3c: master: Add endianness support for i3c_readl_fifo() and i3c_writel_fifo() Content-Type: text/plain Content-Transfer-Encoding: 7bit On Tue, Sep 23, 2025, at 17:45, Manikanta Guntupalli wrote: > /** > * i3c_writel_fifo - Write data buffer to 32bit FIFO > * @addr: FIFO Address to write to > * @buf: Pointer to the data bytes to write > * @nbytes: Number of bytes to write > + * @endian: Endianness of FIFO write > */ > static inline void i3c_writel_fifo(void __iomem *addr, const void *buf, > - int nbytes) > + int nbytes, enum i3c_fifo_endian endian) > { > - writesl(addr, buf, nbytes / 4); > + if (endian) > + writesl_be(addr, buf, nbytes / 4); > + else > + writesl(addr, buf, nbytes / 4); > + This seems counter-intuitive: a FIFO doesn't really have an endianness, it is instead used to transfer a stream of bytes, so if the device has a fixed endianess, the FIFO still needs to be read using a plain writesl(). I see that your writesl_be() has an incorrect definition, which would lead to the i3c_writel_fifo() function accidentally still working if both the device and CPU use big-endian registers: static inline void writesl_be(volatile void __iomem *addr, const void *buffer, unsigned int count) { if (count) { const u32 *buf = buffer; do { __raw_writel((u32 __force)__cpu_to_be32(*buf), addr); buf++; } while (--count); } } The __cpu_to_be32() call that you add here means that the FIFO data is swapped on little-endian CPUs but not swapped on big-endian ones. Compare this to the normal writesl() function that never swaps because it writes a byte stream. > if (nbytes & 3) { > u32 tmp = 0; > > memcpy(&tmp, buf + (nbytes & ~3), nbytes & 3); > - writel(tmp, addr); > + > + if (endian) > + writel_be(tmp, addr); > + else > + writel(tmp, addr); This bit however seems to fix a bug, but does so in a confusing way. The way the FIFO registers usually deal with excess bytes is to put them into the first bytes of the FIFO register, so this should just be a writesl(addr, &tmp, 1); to write one set of four bytes into the FIFO without endian-swapping. Could it be that you are just trying to use a normal i3c adapter with little-endian registers on a normal big-endian machine but ran into this bug? Arnd