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Wed, 12 Nov 2025 13:34:50 -0800 (PST) X-Google-Smtp-Source: AGHT+IGex9yMVhli943u5iSx/utgvoPxPJzj5p0bexquPM0bky2PiZDhb0Iyz19ikO+MPy/f/zNHCw== X-Received: by 2002:a05:6a20:7f8a:b0:340:db9b:cff7 with SMTP id adf61e73a8af0-359090967d7mr5549466637.5.1762983289783; Wed, 12 Nov 2025 13:34:49 -0800 (PST) Received: from [192.168.1.5] ([106.222.234.47]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-bc37818885fsm46671a12.38.2025.11.12.13.34.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Nov 2025 13:34:49 -0800 (PST) Message-ID: <13c39ab6-f054-4552-a033-819906af29d5@oss.qualcomm.com> Date: Thu, 13 Nov 2025 03:04:40 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 16/21] drm/msm/adreno: Do CX GBIF config before GMU start To: Konrad Dybcio , Rob Clark , Bjorn Andersson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek , Jordan Crouse , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Connor Abbott Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org References: <20251110-kaana-gpu-support-v2-0-bef18acd5e94@oss.qualcomm.com> <20251110-kaana-gpu-support-v2-16-bef18acd5e94@oss.qualcomm.com> Content-Language: en-US From: Akhil P Oommen In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: oylyVnTllja9Q5BOs20rW8G7Veq4g0Nz X-Authority-Analysis: v=2.4 cv=E/fAZKdl c=1 sm=1 tr=0 ts=6914fd7b cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=2IP1oaZ8+KUWsYovLW0HHw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=9a4g6yj39E2whjoMmyEA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-ORIG-GUID: oylyVnTllja9Q5BOs20rW8G7Veq4g0Nz X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEyMDE3MyBTYWx0ZWRfX/U5WQx1ltsWP QoomUS5a00ksMOXjU/qgJP67TDVc/xheJnAg/SkdWv6N4i7tgGkStltNr36J16q5ArX+0AGaiOc DIJ7uYKKjcBalD7VJfxHcCUI2eB71Wrdf9g60oQTR6t5M1d5YlzZf3LQO3rrwrTBWZ+QzYhSV7H LpgdAad2KQRo0iR0X2uoKPx8vB7lLPSdRWi8hpWuBk+IzoE0LUyuZwEr+Qo/uqiXUpKJ5l5F/9i xPeQuMIEXxlgQXJ7bRyl/wm1VRa45p7XyaF/caTTmNlh3QzcwXV4EC7ao8wJ76ovm70Na7VBERY 3PGctFMjV//S4q7wP5alCIby6gKAM2L5fX+MMi5zuGDxxX1/IDhAY1jVHo7kW3BO5P71J7r9Hcc YPpj8ScD9R3nOX6fwzNsYybD1lbvzw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-12_06,2025-11-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 spamscore=0 phishscore=0 suspectscore=0 bulkscore=0 impostorscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511120173 On 11/12/2025 4:07 PM, Konrad Dybcio wrote: > On 11/10/25 5:37 PM, Akhil P Oommen wrote: >> GMU lies on the CX domain and accesses CX GBIF. So do CX GBIF >> configurations before GMU wakes up. This was not a problem so far, but >> A840 GPU is very sensitive to this requirement. Also, move these >> registers to the catalog. >> >> Signed-off-by: Akhil P Oommen >> --- > > [...] > >> + /* For A7x and newer, do the CX GBIF configurations before GMU wake up */ >> + for (int i = 0; (gbif_cx && gbif_cx[i].offset); i++) >> + gpu_write(gpu, gbif_cx[i].offset, gbif_cx[i].value); > > We haven't been doing this a lot in the GPU driver, but adding a > .num_entries-like field is both more memory efficient and less error-prone Gbif config array is reused a lot. So this is more memory efficient in this particular case. But generally I agree, we should stick to one scheme. We can revisit this later. > >> + >> + /* For A7x and newer, do the CX GBIF configurations before GMU wake up */ > > duplicate comment > >> + if (adreno_is_a8xx(adreno_gpu)) { >> + gpu_write(gpu, REG_A8XX_GBIF_CX_CONFIG, 0x20023000); >> + gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33); > > Either set this prio value here, or in a8xx_gpu.c We should remove the other one. > >> + } >> + >> /* Set up the lowest idle level on the GMU */ >> a6xx_gmu_power_config(gmu); >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> index 029f7bd25baf..66771958edb2 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> @@ -1265,17 +1265,20 @@ static int hw_init(struct msm_gpu *gpu) >> /* enable hardware clockgating */ >> a6xx_set_hwcg(gpu, true); >> >> - /* VBIF/GBIF start*/ >> - if (adreno_is_a610_family(adreno_gpu) || >> - adreno_is_a640_family(adreno_gpu) || >> - adreno_is_a650_family(adreno_gpu) || >> - adreno_is_a7xx(adreno_gpu)) { >> + /* For gmuwrapper implementations, do the VBIF/GBIF CX configuration here */ >> + if (adreno_is_a610_family(adreno_gpu)) { >> gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); > > a640/650 family GPUs didn't receive a .gbif_cx addition in the catalog to match> Oops, I missed that. Will fix this. Thanks. >> gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); >> gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); >> gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); >> - gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, >> - adreno_is_a7xx(adreno_gpu) ? 0x2120212 : 0x3); >> + } >> + >> + if (adreno_is_a610_family(adreno_gpu) || >> + adreno_is_a640_family(adreno_gpu) || >> + adreno_is_a650_family(adreno_gpu)) { >> + gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3); >> + } else if (adreno_is_a7xx(adreno_gpu)) { >> + gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x2120212); >> } else { >> gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); > > Downstream seems to set QOS_CNTL at the same time as QSB_SIDEn for > these targets This register is under GX power domain, so we can't configure this early. This should be okay. > > >> } >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h >> index 031ca0e4b689..cf700f7de09b 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h >> @@ -46,6 +46,7 @@ struct a6xx_info { >> const struct adreno_protect *protect; >> const struct adreno_reglist_list *pwrup_reglist; >> const struct adreno_reglist_list *ifpc_reglist; >> + const struct adreno_reglist *gbif_cx; >> const struct adreno_reglist_pipe *nonctxt_reglist; >> u32 gmu_chipid; >> u32 gmu_cgc_mode; >> diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c >> index 2ef69161f1d0..ad140b0d641d 100644 >> --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c >> @@ -500,6 +500,9 @@ static int hw_init(struct msm_gpu *gpu) >> >> gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); >> >> + /* Increase priority of GMU traffic over GPU traffic */ >> + gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33); > > Kgsl (later) added this for A740 too - would it be beneficial to enable > unconditionally on gen7+? These are actually recommendations coming from HW designers for each chipset. So we should just stick to that. I will check separately about a740. -Akhil. > > Konrad