* (unknown),
@ 2014-05-24 1:21 Loc Ho
[not found] ` <1400894467-1585-1-git-send-email-lho-qTEPVZfXA3Y@public.gmane.org>
0 siblings, 1 reply; 58+ messages in thread
From: Loc Ho @ 2014-05-24 1:21 UTC (permalink / raw)
To: dougthompson-aS9lmoZGLiVWk0Htik3J/w, bp-Gina5bIWoIWzQB+pC5nmwQ,
m.chehab-Sze3O3UU22JBDgjK7y7TUQ
Cc: linux-edac-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
jcm-H+wXaHxf7aLQT0dZR+AlfA, patches-qTEPVZfXA3Y, Loc Ho
This patch adds support for the APM X-Gene SoC EDAC driver.
v2:
* Add EDAC entry in MAINTAINERS for APM EDAC driver
* Remove the MC scrub patch
* Remove the word 'Caches' from Kconfig
* Change all MASK defines to use BIT(x)
* Update comment or remove them
* Wrap error injection code around CONFIG_EDAC_DEBUG
* Change function name xgene_edac_mc_hw_init to xgene_edac_mc_irq_ctl
* Change all function XXX_hw_init to XXX_hw_ctl
* Fix typo 'activie'
* Move calling function edac_mc_alloc after resource retrieval
* Check for NULL on platform_get_resource return if reference directly
* Add documentation for struct xgene_edac_pmd_ctx
* Move L1 and L2 check out of function xgene_edac_pmd_check to its own
functions
* Use for loop for configure each CPU of an PMD
* Replace /2 by >> 1
* Remove unnecessary comment on edac_device_add_device failure
* Make mem_err_ip static const
* Unwind EDAC register correctly if failed
---
Loc Ho (4):
MAINTAINERS: Add entry for APM X-Gene SoC EDAC driver
Documentation: Add documentation for the APM X-Gene SoC EDAC DTS
binding
edac: Add APM X-Gene SoC EDAC driver
arm64: Add APM X-Gene SoC EDAC DTS entries
.../devicetree/bindings/edac/apm-xgene-edac.txt | 70 +
MAINTAINERS | 8 +
arch/arm64/boot/dts/apm-storm.dtsi | 89 +
drivers/edac/Kconfig | 9 +-
drivers/edac/Makefile | 3 +
drivers/edac/xgene_edac.c | 1993 ++++++++++++++++++++
6 files changed, 2171 insertions(+), 1 deletions(-)
create mode 100644 Documentation/devicetree/bindings/edac/apm-xgene-edac.txt
create mode 100644 drivers/edac/xgene_edac.c
--
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^ permalink raw reply [flat|nested] 58+ messages in thread[parent not found: <1400894467-1585-1-git-send-email-lho-qTEPVZfXA3Y@public.gmane.org>]
* [PATCH v2 1/4] MAINTAINERS: Add entry for APM X-Gene SoC EDAC driver [not found] ` <1400894467-1585-1-git-send-email-lho-qTEPVZfXA3Y@public.gmane.org> @ 2014-05-24 1:21 ` Loc Ho [not found] ` <1400894467-1585-2-git-send-email-lho-qTEPVZfXA3Y@public.gmane.org> 0 siblings, 1 reply; 58+ messages in thread From: Loc Ho @ 2014-05-24 1:21 UTC (permalink / raw) To: dougthompson-aS9lmoZGLiVWk0Htik3J/w, bp-Gina5bIWoIWzQB+pC5nmwQ, m.chehab-Sze3O3UU22JBDgjK7y7TUQ Cc: linux-edac-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, jcm-H+wXaHxf7aLQT0dZR+AlfA, patches-qTEPVZfXA3Y, Loc Ho This patch adds a MAINTAINERS entry for APM X-Gene SoC EDAC driver. Signed-off-by: Loc Ho <lho-qTEPVZfXA3Y@public.gmane.org> --- MAINTAINERS | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index e67ea24..ecef44c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3321,6 +3321,14 @@ W: bluesmoke.sourceforge.net S: Maintained F: drivers/edac/sb_edac.c +EDAC-XGENE +APPLIED MICRO (APM) X-GENE SOC EDAC +M: Loc Ho <lho-qTEPVZfXA3Y@public.gmane.org> +M: Feng Kan <fkan-qTEPVZfXA3Y@public.gmane.org> +S: Supported +F: drivers/edac/xgene_edac.c +F: Documentation/devicetree/bindings/edac/apm-xgene-edac.txt + EDIROL UA-101/UA-1000 DRIVER M: Clemens Ladisch <clemens-P6GI/4k7KOmELgA04lAiVw@public.gmane.org> L: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org (moderated for non-subscribers) -- 1.5.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 58+ messages in thread
[parent not found: <1400894467-1585-2-git-send-email-lho-qTEPVZfXA3Y@public.gmane.org>]
* [PATCH v2 2/4] Documentation: Add documentation for the APM X-Gene SoC EDAC DTS binding [not found] ` <1400894467-1585-2-git-send-email-lho-qTEPVZfXA3Y@public.gmane.org> @ 2014-05-24 1:21 ` Loc Ho [not found] ` <1400894467-1585-3-git-send-email-lho-qTEPVZfXA3Y@public.gmane.org> 0 siblings, 1 reply; 58+ messages in thread From: Loc Ho @ 2014-05-24 1:21 UTC (permalink / raw) To: dougthompson-aS9lmoZGLiVWk0Htik3J/w, bp-Gina5bIWoIWzQB+pC5nmwQ, m.chehab-Sze3O3UU22JBDgjK7y7TUQ Cc: linux-edac-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, jcm-H+wXaHxf7aLQT0dZR+AlfA, patches-qTEPVZfXA3Y, Loc Ho, Feng Kan This patch adds documentation for the APM X-Gene SoC EDAC DTS binding. Signed-off-by: Feng Kan <fkan-qTEPVZfXA3Y@public.gmane.org> Signed-off-by: Loc Ho <lho-qTEPVZfXA3Y@public.gmane.org> --- .../devicetree/bindings/edac/apm-xgene-edac.txt | 70 ++++++++++++++++++++ 1 files changed, 70 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/edac/apm-xgene-edac.txt diff --git a/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt b/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt new file mode 100644 index 0000000..c4ccc98 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt @@ -0,0 +1,70 @@ +* APM X-Gene EDAC nodes + +EDAC nodes are defined to describe on-chip error detection and correction. +There are four types of EDAC: + + memory controller - Memory controller + PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache + L3 - CPU L3 cache + SoC - SoC IP such as SATA, Ethernet. and etc + +The following section describes the memory controller DT node binding. + +Required properties: +- compatible : Shall be "apm,xgene-edac-mc". +- reg : First resource shall be the PCP resource. + Second resource shall be the CSW resource. + Third resource shall be the MCB-A resource. + Fourth resource shall be the MCB-B resource. + Fifth resource shall be the MCU resource. +- interrupts : Interrupt-specifier for MCU error IRQ. + +The following section describes the L1/L2 DT node binding. + +- compatible : Shall be "apm,xgene-edac-pmd". +- reg : First resource shall be the PCP resource. + Second resource shall be the PMD resource. +- interrupts : Interrupt-specifier for PMD error IRQ. + +The following section describes the L3 DT node binding. + +- compatible : Shall be "apm,xgene-edac-l3". +- reg : First resource shall be the PCP resource. + Second resource shall be the L3 resource. +- interrupts : Interrupt-specifier for L3 error IRQ. + +Example: + edacmc0: edacmc0@7e800000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x78800000 0x0 0x1000>, + <0x0 0x7e200000 0x0 0x1000>, + <0x0 0x7e700000 0x0 0x1000>, + <0x0 0x7e720000 0x0 0x1000>, + <0x0 0x7e800000 0x0 0x1000>; + interrupts = <0x0 0x20 0x4>; + }; + + edacl3: edacl3@7e600000 { + compatible = "apm,xgene-edac-l3"; + reg = <0x0 0x78800000 0x0 0x1000>, + <0x0 0x7e600000 0x0 0x1000>; + interrupts = <0x0 0x20 0x4>, + <0x0 0x21 0x4>; + }; + + edacpmd0: edacpmd0@7c000000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x78800000 0x0 0x1000>, + <0x0 0x7c000000 0x0 0x200000>; + interrupts = <0x0 0x20 0x4>, + <0x0 0x21 0x4>; + }; + + edacsoc: edacsoc@7e930000 { + compatible = "apm,xgene-edac-soc"; + reg = <0x0 0x78800000 0x0 0x1000>, + <0x0 0x7e930000 0x0 0x1000>; + interrupts = <0x0 0x20 0x4>, + <0x0 0x21 0x4>, + <0x0 0x27 0x4>; + }; -- 1.5.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 58+ messages in thread
[parent not found: <1400894467-1585-3-git-send-email-lho-qTEPVZfXA3Y@public.gmane.org>]
* [PATCH v2 3/4] edac: Add APM X-Gene SoC EDAC driver [not found] ` <1400894467-1585-3-git-send-email-lho-qTEPVZfXA3Y@public.gmane.org> @ 2014-05-24 1:21 ` Loc Ho [not found] ` <1400894467-1585-4-git-send-email-lho-qTEPVZfXA3Y@public.gmane.org> 0 siblings, 1 reply; 58+ messages in thread From: Loc Ho @ 2014-05-24 1:21 UTC (permalink / raw) To: dougthompson-aS9lmoZGLiVWk0Htik3J/w, bp-Gina5bIWoIWzQB+pC5nmwQ, m.chehab-Sze3O3UU22JBDgjK7y7TUQ Cc: linux-edac-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, jcm-H+wXaHxf7aLQT0dZR+AlfA, patches-qTEPVZfXA3Y, Loc Ho, Feng Kan This patch adds support for the APM X-Gene SoC EDAC driver and requires ARM64 EDAC support patch [1] to compile. [1] http://www.spinics.net/lists/arm-kernel/msg324093.html Signed-off-by: Feng Kan <fkan-qTEPVZfXA3Y@public.gmane.org> Signed-off-by: Loc Ho <lho-qTEPVZfXA3Y@public.gmane.org> --- drivers/edac/Kconfig | 9 +- drivers/edac/Makefile | 3 + drivers/edac/xgene_edac.c | 1993 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 2004 insertions(+), 1 deletions(-) create mode 100644 drivers/edac/xgene_edac.c diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 878f090..43e8281 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -10,7 +10,7 @@ config EDAC_SUPPORT menuconfig EDAC bool "EDAC (Error Detection And Correction) reporting" depends on HAS_IOMEM - depends on X86 || PPC || TILE || ARM || EDAC_SUPPORT + depends on X86 || PPC || TILE || ARM || ARM64 || EDAC_SUPPORT help EDAC is designed to report errors in the core system. These are low-level errors that are reported in the CPU or @@ -368,4 +368,11 @@ config EDAC_OCTEON_PCI Support for error detection and correction on the Cavium Octeon family of SOCs. +config EDAC_XGENE + tristate "APM X-Gene SoC" + depends on EDAC_MM_EDAC && ARM64 + help + Support for error detection and correction on the + APM X-Gene family of SOCs. + endif # EDAC diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 4154ed6..f408be4 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -64,3 +64,6 @@ obj-$(CONFIG_EDAC_OCTEON_PC) += octeon_edac-pc.o obj-$(CONFIG_EDAC_OCTEON_L2C) += octeon_edac-l2c.o obj-$(CONFIG_EDAC_OCTEON_LMC) += octeon_edac-lmc.o obj-$(CONFIG_EDAC_OCTEON_PCI) += octeon_edac-pci.o + +obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o + diff --git a/drivers/edac/xgene_edac.c b/drivers/edac/xgene_edac.c new file mode 100644 index 0000000..23bd2ea --- /dev/null +++ b/drivers/edac/xgene_edac.c @@ -0,0 +1,1993 @@ +/* + * APM X-Gene SoC EDAC (error detection and correction) Module + * + * Copyright (c) 2014, Applied Micro Circuits Corporation + * Author: Feng Kan <fkan-qTEPVZfXA3Y@public.gmane.org> + * Loc Ho <lho-qTEPVZfXA3Y@public.gmane.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/ctype.h> +#include <linux/edac.h> +#include <linux/of.h> +#include "edac_core.h" + +#define EDAC_MOD_STR "xgene_edac" + +static int edac_mc_idx; +static DEFINE_MUTEX(xgene_edac_lock); + +/* Global error configuration status registers (CSR) */ +#define PCPHPERRINTSTS 0x0000 +#define PCPHPERRINTMSK 0x0004 +#define MCU_CTL_ERR_MASK BIT(12) +#define IOB_PA_ERR_MASK BIT(11) +#define IOB_BA_ERR_MASK BIT(10) +#define IOB_XGIC_ERR_MASK BIT(9) +#define IOB_RB_ERR_MASK BIT(8) +#define L3C_UNCORR_ERR_MASK BIT(5) +#define MCU_UNCORR_ERR_MASK BIT(4) +#define PMD3_MERR_MASK BIT(3) +#define PMD2_MERR_MASK BIT(2) +#define PMD1_MERR_MASK BIT(1) +#define PMD0_MERR_MASK BIT(0) +#define PCPLPERRINTSTS 0x0008 +#define PCPLPERRINTMSK 0x000C +#define CSW_SWITCH_TRACE_ERR_MASK BIT(2) +#define L3C_CORR_ERR_MASK BIT(1) +#define MCU_CORR_ERR_MASK BIT(0) +#define MEMERRINTSTS 0x0010 +#define MEMERRINTMSK 0x0014 + +/* Memory controller error CSR */ +#define MCU_MAX_RANK 8 +#define MCU_RANK_STRIDE 0x40 + +#define MCUGESR 0x0114 +#define MCU_GESR_ADDRNOMATCH_ERR_MASK BIT(7) +#define MCU_GESR_ADDRMULTIMATCH_ERR_MASK BIT(6) +#define MCU_GESR_PHYP_ERR_MASK BIT(3) +#define MCUESRR0 0x0314 +#define MCU_ESRR_MULTUCERR_MASK BIT(3) +#define MCU_ESRR_BACKUCERR_MASK BIT(2) +#define MCU_ESRR_DEMANDUCERR_MASK BIT(1) +#define MCU_ESRR_CERR_MASK BIT(0) +#define MCUESRRA0 0x0318 +#define MCUEBLRR0 0x031c +#define MCU_EBLRR_ERRBANK_RD(src) (((src) & 0x00000007) >> 0) +#define MCUERCRR0 0x0320 +#define MCU_ERCRR_ERRROW_RD(src) (((src) & 0xFFFF0000) >> 16) +#define MCU_ERCRR_ERRCOL_RD(src) ((src) & 0x00000FFF) +#define MCUSBECNT0 0x0324 +#define MCU_SBECNT_COUNT(src) ((src) & 0xFFFF) + +#define CSW_CSWCR 0x0000 +#define CSW_CSWCR_DUALMCB_MASK BIT(0) + +#define MCBADDRMR 0x0000 +#define MCBADDRMR_MCU_INTLV_MODE_MASK BIT(3) +#define MCBADDRMR_DUALMCU_MODE_MASK BIT(2) +#define MCBADDRMR_MCB_INTLV_MODE_MASK BIT(1) +#define MCBADDRMR_ADDRESS_MODE_MASK BIT(0) + +struct xgene_edac_mc_ctx { + char *name; + void __iomem *pcp_csr; + void __iomem *csw_csr; + void __iomem *mcba_csr; + void __iomem *mcbb_csr; + void __iomem *mcu_csr; +}; + +#define to_mci(k) container_of(k, struct mem_ctl_info, dev) + +static ssize_t xgene_edac_mc_inject_ctrl_show(struct device *dev, + struct device_attribute *mattr, + char *data) +{ + struct mem_ctl_info *mci = to_mci(dev); + struct xgene_edac_mc_ctx *ctx = mci->pvt_info; + int i; + ssize_t ret_size = 0; + + for (i = 0; i < MCU_MAX_RANK; i++) { + ret_size += sprintf(data, "0x%08X", + readl(ctx->mcu_csr + MCUESRRA0 + + i * MCU_RANK_STRIDE)); + data += 10; + if (i != (MCU_MAX_RANK - 1)) { + ret_size += sprintf(data, " "); + data++; + } + } + return ret_size; +} + +static ssize_t xgene_edac_mc_inject_ctrl_store(struct device *dev, + struct device_attribute *mattr, + const char *data, size_t count) +{ + struct mem_ctl_info *mci = to_mci(dev); + struct xgene_edac_mc_ctx *ctx = mci->pvt_info; + u32 val; + int i; + + if (isdigit(*data)) { + if (kstrtou32(data, 0, &val)) + return 0; + for (i = 0; i < MCU_MAX_RANK; i++) { + writel(val, + ctx->mcu_csr + MCUESRRA0 + i * MCU_RANK_STRIDE); + } + return count; + } + return 0; +} + +DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR, + xgene_edac_mc_inject_ctrl_show, xgene_edac_mc_inject_ctrl_store); + +static int xgene_edac_mc_create_sysfs_attributes(struct mem_ctl_info *mci) +{ +#if defined(CONFIG_EDAC_DEBUG) + return device_create_file(&mci->dev, &dev_attr_inject_ctrl); +#else + return 0; +#endif +} + +static void xgene_edac_mc_remove_sysfs_attributes(struct mem_ctl_info *mci) +{ +#if defined(CONFIG_EDAC_DEBUG) + device_remove_file(&mci->dev, &dev_attr_inject_ctrl); +#endif +} + +static void xgene_edac_mc_check(struct mem_ctl_info *mci) +{ + struct xgene_edac_mc_ctx *ctx = mci->pvt_info; + u32 pcp_hp_stat; + u32 pcp_lp_stat; + u32 reg; + u32 rank; + u32 bank; + u32 count; + u32 col_row; + + pcp_hp_stat = readl(ctx->pcp_csr + PCPHPERRINTSTS); + pcp_lp_stat = readl(ctx->pcp_csr + PCPLPERRINTSTS); + if (!((MCU_UNCORR_ERR_MASK & pcp_hp_stat) || + (MCU_CTL_ERR_MASK & pcp_hp_stat) || + (MCU_CORR_ERR_MASK & pcp_lp_stat))) + return; + + for (rank = 0; rank < MCU_MAX_RANK; rank++) { + reg = readl(ctx->mcu_csr + MCUESRR0 + rank * MCU_RANK_STRIDE); + + /* Detect uncorrectable memory error */ + if (reg & (MCU_ESRR_DEMANDUCERR_MASK | + MCU_ESRR_BACKUCERR_MASK)) { + /* Detected uncorrectable memory error */ + edac_mc_chipset_printk(mci, KERN_ERR, "X-Gene", + "MCU uncorrectable error at rank %d\n", rank); + + edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, + 1, 0, 0, 0, 0, 0, -1, mci->ctl_name, ""); + } + + /* Detect correctable memory error */ + if (reg & MCU_ESRR_CERR_MASK) { + bank = readl(ctx->mcu_csr + MCUEBLRR0 + + rank * MCU_RANK_STRIDE); + col_row = readl(ctx->mcu_csr + MCUERCRR0 + + rank * MCU_RANK_STRIDE); + count = readl(ctx->mcu_csr + MCUSBECNT0 + + rank * MCU_RANK_STRIDE); + edac_mc_chipset_printk(mci, KERN_WARNING, "X-Gene", + "MCU correctable error at rank %d bank %d column %d row %d count %d\n", + rank, MCU_EBLRR_ERRBANK_RD(bank), + MCU_ERCRR_ERRCOL_RD(col_row), + MCU_ERCRR_ERRROW_RD(col_row), + MCU_SBECNT_COUNT(count)); + + edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, + 1, 0, 0, 0, 0, 0, -1, mci->ctl_name, ""); + } + + /* Clear all error registers */ + writel(0x0, ctx->mcu_csr + MCUEBLRR0 + rank * MCU_RANK_STRIDE); + writel(0x0, ctx->mcu_csr + MCUERCRR0 + rank * MCU_RANK_STRIDE); + writel(0x0, ctx->mcu_csr + MCUSBECNT0 + + rank * MCU_RANK_STRIDE); + writel(reg, ctx->mcu_csr + MCUESRR0 + rank * MCU_RANK_STRIDE); + } + + /* Detect memory controller error */ + reg = readl(ctx->mcu_csr + MCUGESR); + if (reg) { + if (reg & MCU_GESR_ADDRNOMATCH_ERR_MASK) + edac_mc_chipset_printk(mci, KERN_WARNING, "X-Gene", + "MCU address miss-match error\n"); + if (reg & MCU_GESR_ADDRMULTIMATCH_ERR_MASK) + edac_mc_chipset_printk(mci, KERN_WARNING, "X-Gene", + "MCU address multi-match error\n"); + + writel(reg, ctx->mcu_csr + MCUGESR); + } +} + +static irqreturn_t xgene_edac_mc_isr(int irq, void *dev_id) +{ + struct mem_ctl_info *mci = dev_id; + struct xgene_edac_mc_ctx *ctx = mci->pvt_info; + u32 pcp_hp_stat; + u32 pcp_lp_stat; + + pcp_hp_stat = readl(ctx->pcp_csr + PCPHPERRINTSTS); + pcp_lp_stat = readl(ctx->pcp_csr + PCPLPERRINTSTS); + if (!((MCU_UNCORR_ERR_MASK & pcp_hp_stat) || + (MCU_CTL_ERR_MASK & pcp_hp_stat) || + (MCU_CORR_ERR_MASK & pcp_lp_stat))) + return IRQ_NONE; + + xgene_edac_mc_check(mci); + + return IRQ_HANDLED; +} + +static void xgene_edac_mc_irq_ctl(struct mem_ctl_info *mci, bool enable) +{ + struct xgene_edac_mc_ctx *ctx = mci->pvt_info; + u32 val; + + if (edac_op_state != EDAC_OPSTATE_INT) + return; + + mutex_lock(&xgene_edac_lock); + + if (enable) { + /* Enable memory controller top level interrupt */ + val = readl(ctx->pcp_csr + PCPHPERRINTMSK); + val &= ~(MCU_UNCORR_ERR_MASK | MCU_CTL_ERR_MASK); + writel(val, ctx->pcp_csr + PCPHPERRINTMSK); + } else { + /* Disable memory controller top level interrupt */ + val = readl(ctx->pcp_csr + PCPHPERRINTMSK); + val |= MCU_UNCORR_ERR_MASK | MCU_CTL_ERR_MASK; + writel(val, ctx->pcp_csr + PCPHPERRINTMSK); + } + + mutex_unlock(&xgene_edac_lock); +} + +static int xgene_edac_mc_is_active(struct xgene_edac_mc_ctx *ctx, int mc_idx) +{ + u32 reg; + u32 mcu_mask; + + reg = readl(ctx->csw_csr + CSW_CSWCR); + if (reg & CSW_CSWCR_DUALMCB_MASK) { + /* + * Dual MCB active - Determine if all 4 active or just MCU0 + * and MCU2 active + */ + reg = readl(ctx->mcbb_csr + MCBADDRMR); + mcu_mask = (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5; + } else { + /* + * Single MCB active - Determine if MCU0/MCU1 or just MCU0 + * active + */ + reg = readl(ctx->mcba_csr + MCBADDRMR); + mcu_mask = (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1; + } + + return (mcu_mask & (1 << mc_idx)) ? 1 : 0; +} + +static int xgene_edac_mc_probe(struct platform_device *pdev) +{ + struct mem_ctl_info *mci; + struct edac_mc_layer layers[2]; + struct xgene_edac_mc_ctx tmp_ctx; + struct xgene_edac_mc_ctx *ctx; + struct resource *res; + int rc = 0; + + if (!devres_open_group(&pdev->dev, xgene_edac_mc_probe, GFP_KERNEL)) + return -ENOMEM; + + /* Retrieve resources */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "no PCP resource address\n"); + rc = -EINVAL; + goto err_group; + } + tmp_ctx.pcp_csr = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (IS_ERR(tmp_ctx.pcp_csr)) { + dev_err(&pdev->dev, "no PCP resource address\n"); + rc = PTR_ERR(tmp_ctx.pcp_csr); + goto err_group; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) { + dev_err(&pdev->dev, "no CSW resource address\n"); + rc = -EINVAL; + goto err_group; + } + tmp_ctx.csw_csr = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (IS_ERR(tmp_ctx.csw_csr)) { + dev_err(&pdev->dev, "no CSW resource address\n"); + rc = PTR_ERR(tmp_ctx.csw_csr); + goto err_group; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (!res) { + dev_err(&pdev->dev, "no MCBA resource address\n"); + rc = -EINVAL; + goto err_group; + } + tmp_ctx.mcba_csr = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (IS_ERR(tmp_ctx.mcba_csr)) { + dev_err(&pdev->dev, "no MCBA resource address\n"); + rc = PTR_ERR(tmp_ctx.mcba_csr); + goto err_group; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 3); + if (!res) { + dev_err(&pdev->dev, "no MCBB resource address\n"); + rc = -EINVAL; + goto err_group; + } + tmp_ctx.mcbb_csr = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (IS_ERR(tmp_ctx.mcbb_csr)) { + dev_err(&pdev->dev, "no MCBB resource address\n"); + rc = PTR_ERR(tmp_ctx.mcbb_csr); + goto err_group; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 4); + tmp_ctx.mcu_csr = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(tmp_ctx.mcu_csr)) { + dev_err(&pdev->dev, "no MCU resource address\n"); + rc = PTR_ERR(tmp_ctx.mcu_csr); + goto err_group; + } + /* Ignore non-active MCU */ + if (!xgene_edac_mc_is_active(&tmp_ctx, + ((res->start >> 16) & 0xF) / 4)) { + rc = -ENODEV; + goto err_group; + } + + layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; + layers[0].size = 4; + layers[0].is_virt_csrow = true; + layers[1].type = EDAC_MC_LAYER_CHANNEL; + layers[1].size = 2; + layers[1].is_virt_csrow = false; + mci = edac_mc_alloc(edac_mc_idx++, ARRAY_SIZE(layers), layers, + sizeof(*ctx)); + if (!mci) { + rc = -ENOMEM; + goto err_group; + } + + ctx = mci->pvt_info; + *ctx = tmp_ctx; /* Copy over resource value */ + ctx->name = "xgene_edac_mc_err"; + mci->pdev = &pdev->dev; + dev_set_drvdata(mci->pdev, mci); + mci->ctl_name = ctx->name; + mci->dev_name = ctx->name; + + mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 | MEM_FLAG_RDDR3 | + MEM_FLAG_DDR | MEM_FLAG_DDR2 | MEM_FLAG_DDR3; + mci->edac_ctl_cap = EDAC_FLAG_SECDED; + mci->edac_cap = EDAC_FLAG_SECDED; + mci->mod_name = EDAC_MOD_STR; + mci->mod_ver = "0.1"; + mci->ctl_page_to_phys = NULL; + mci->scrub_cap = SCRUB_FLAG_HW_SRC; + mci->scrub_mode = SCRUB_HW_SRC; + + if (edac_op_state == EDAC_OPSTATE_POLL) + mci->edac_check = xgene_edac_mc_check; + + if (edac_mc_add_mc(mci)) { + dev_err(&pdev->dev, "failed add edac mc\n"); + rc = -EINVAL; + goto err_free; + } + + if (xgene_edac_mc_create_sysfs_attributes(mci)) { + dev_err(&pdev->dev, "failed create edac sysfs\n"); + goto err_del; + } + + if (edac_op_state == EDAC_OPSTATE_INT) { + int irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "No IRQ resource\n"); + rc = -EINVAL; + goto err_sysfs; + } + rc = devm_request_irq(&pdev->dev, irq, + xgene_edac_mc_isr, IRQF_SHARED, + dev_name(&pdev->dev), mci); + if (rc) { + dev_err(&pdev->dev, "Could not request IRQ\n"); + goto err_sysfs; + } + } + + xgene_edac_mc_irq_ctl(mci, 1); + + devres_remove_group(&pdev->dev, xgene_edac_mc_probe); + + dev_info(&pdev->dev, "X-Gene EDAC MC registered\n"); + return 0; + +err_sysfs: + xgene_edac_mc_remove_sysfs_attributes(mci); +err_del: + edac_mc_del_mc(&pdev->dev); +err_free: + edac_mc_free(mci); +err_group: + devres_release_group(&pdev->dev, xgene_edac_mc_probe); + return rc; +} + +static int xgene_edac_mc_remove(struct platform_device *pdev) +{ + struct mem_ctl_info *mci = dev_get_drvdata(&pdev->dev); + + xgene_edac_mc_irq_ctl(mci, 0); + xgene_edac_mc_remove_sysfs_attributes(mci); + edac_mc_del_mc(&pdev->dev); + edac_mc_free(mci); + return 0; +} + +#ifdef CONFIG_OF +static struct of_device_id xgene_edac_mc_of_match[] = { + { .compatible = "apm,xgene-edac-mc" }, + {}, +}; +MODULE_DEVICE_TABLE(of, xgene_edac_of_match); +#endif + +static struct platform_driver xgene_edac_mc_driver = { + .probe = xgene_edac_mc_probe, + .remove = xgene_edac_mc_remove, + .driver = { + .name = "xgene-edac-mc", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(xgene_edac_mc_of_match), + }, +}; + +/* CPU L1/L2 error device */ +#define MAX_CPU_PER_PMD 2 +#define CPU_CSR_STRIDE 0x00100000 +#define CPU_L2C_PAGE 0x000D0000 +#define CPU_MEMERR_L2C_PAGE 0x000E0000 +#define CPU_MEMERR_CPU_PAGE 0x000F0000 + +#define MEMERR_CPU_ICFECR_PAGE_OFFSET 0x0000 +#define MEMERR_CPU_ICFESR_PAGE_OFFSET 0x0004 +#define MEMERR_CPU_ICFESR_ERRWAY_RD(src) (((src) & 0xFF000000) >> 24) +#define MEMERR_CPU_ICFESR_ERRINDEX_RD(src) (((src) & 0x003F0000) >> 16) +#define MEMERR_CPU_ICFESR_ERRINFO_RD(src) (((src) & 0x0000FF00) >> 8) +#define MEMERR_CPU_ICFESR_ERRTYPE_RD(src) (((src) & 0x00000070) >> 4) +#define MEMERR_CPU_ICFESR_MULTCERR_MASK BIT(2) +#define MEMERR_CPU_ICFESR_CERR_MASK BIT(0) +#define MEMERR_CPU_LSUESR_PAGE_OFFSET 0x000c +#define MEMERR_CPU_LSUESR_ERRWAY_RD(src) (((src) & 0xFF000000) >> 24) +#define MEMERR_CPU_LSUESR_ERRINDEX_RD(src) (((src) & 0x003F0000) >> 16) +#define MEMERR_CPU_LSUESR_ERRINFO_RD(src) (((src) & 0x0000FF00) >> 8) +#define MEMERR_CPU_LSUESR_ERRTYPE_RD(src) (((src) & 0x00000070) >> 4) +#define MEMERR_CPU_LSUESR_MULTCERR_MASK BIT(2) +#define MEMERR_CPU_LSUESR_CERR_MASK BIT(0) +#define MEMERR_CPU_LSUECR_PAGE_OFFSET 0x0008 +#define MEMERR_CPU_MMUECR_PAGE_OFFSET 0x0010 +#define MEMERR_CPU_MMUESR_PAGE_OFFSET 0x0014 +#define MEMERR_CPU_ICFESRA_PAGE_OFFSET 0x0804 +#define MEMERR_CPU_LSUESRA_PAGE_OFFSET 0x080c +#define MEMERR_CPU_MMUESRA_PAGE_OFFSET 0x0814 + +#define MEMERR_L2C_L2ECR_PAGE_OFFSET 0x0000 +#define MEMERR_L2C_L2ESR_PAGE_OFFSET 0x0004 +#define MEMERR_L2C_L2ESR_ERRSYN_RD(src) (((src) & 0xFF000000) >> 24) +#define MEMERR_L2C_L2ESR_ERRWAY_RD(src) (((src) & 0x00FC0000) >> 18) +#define MEMERR_L2C_L2ESR_ERRCPU_RD(src) (((src) & 0x00020000) >> 17) +#define MEMERR_L2C_L2ESR_ERRGROUP_RD(src) (((src) & 0x0000E000) >> 13) +#define MEMERR_L2C_L2ESR_ERRACTION_RD(src) (((src) & 0x00001C00) >> 10) +#define MEMERR_L2C_L2ESR_ERRTYPE_RD(src) (((src) & 0x00000300) >> 8) +#define MEMERR_L2C_L2ESR_MULTUCERR_MASK BIT(3) +#define MEMERR_L2C_L2ESR_MULTICERR_MASK BIT(2) +#define MEMERR_L2C_L2ESR_UCERR_MASK BIT(1) +#define MEMERR_L2C_L2ESR_ERR_MASK BIT(0) +#define MEMERR_L2C_L2EALR_PAGE_OFFSET 0x0008 +#define CPUX_L2C_L2RTOCR_PAGE_OFFSET 0x0010 +#define MEMERR_L2C_L2EAHR_PAGE_OFFSET 0x000c +#define CPUX_L2C_L2RTOSR_PAGE_OFFSET 0x0014 +#define CPUX_L2C_L2RTOALR_PAGE_OFFSET 0x0018 +#define CPUX_L2C_L2RTOAHR_PAGE_OFFSET 0x001c +#define MEMERR_L2C_L2ESRA_PAGE_OFFSET 0x0804 + +/* + * Processor Module Domain (PMD) context - Context for an pair of processsors. + * Each PMD consists of 2 CPU's and an shared L2 cache. Each CPU consists of + * its own L1 cache. + */ +struct xgene_edac_pmd_ctx { + struct device *dev; + char *name; + void __iomem *pcp_csr; /* PCP CSR for reading error interrupt reg */ + void __iomem *pmd_csr; /* PMD CSR for reading L1/L2 error reg */ + int pmd; /* Identify the register in pcp_csr */ +}; + +static void xgene_edac_pmd_l1_check(struct edac_device_ctl_info *edac_dev, + int cpu_idx) +{ + struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; + u32 __iomem *pg_f; + u32 val; + + pg_f = ctx->pmd_csr + cpu_idx * CPU_CSR_STRIDE + CPU_MEMERR_CPU_PAGE; + + val = readl(pg_f + MEMERR_CPU_ICFESR_PAGE_OFFSET); + if (val) { + dev_err(edac_dev->dev, + "CPU%d L1 memory error ICF 0x%08X Way 0x%02X Index 0x%02X Info 0x%02X\n", + ctx->pmd * MAX_CPU_PER_PMD + cpu_idx, val, + MEMERR_CPU_ICFESR_ERRWAY_RD(val), + MEMERR_CPU_ICFESR_ERRINDEX_RD(val), + MEMERR_CPU_ICFESR_ERRINFO_RD(val)); + if (val & MEMERR_CPU_ICFESR_CERR_MASK) + dev_err(edac_dev->dev, + "One or more correctable error\n"); + if (val & MEMERR_CPU_ICFESR_MULTCERR_MASK) + dev_err(edac_dev->dev, "Multiple correctable error\n"); + switch (MEMERR_CPU_ICFESR_ERRTYPE_RD(val)) { + case 1: + dev_err(edac_dev->dev, "L1 TLB multiple hit\n"); + break; + case 2: + dev_err(edac_dev->dev, "Way select multiple hit\n"); + break; + case 3: + dev_err(edac_dev->dev, "Physical tag parity error\n"); + break; + case 4: + case 5: + dev_err(edac_dev->dev, "L1 data parity error\n"); + break; + case 6: + dev_err(edac_dev->dev, "L1 pre-decode parity error\n"); + break; + } + writel(val, pg_f + MEMERR_CPU_ICFESRA_PAGE_OFFSET); + if (val & (MEMERR_CPU_ICFESR_CERR_MASK | + MEMERR_CPU_ICFESR_MULTCERR_MASK)) + edac_device_handle_ce(edac_dev, 0, 0, + edac_dev->ctl_name); + } + + val = readl(pg_f + MEMERR_CPU_LSUESR_PAGE_OFFSET); + if (val) { + dev_err(edac_dev->dev, + "CPU%d memory error LSU 0x%08X Way 0x%02X Index 0x%02X Info 0x%02X\n", + ctx->pmd * MAX_CPU_PER_PMD + cpu_idx, val, + MEMERR_CPU_LSUESR_ERRWAY_RD(val), + MEMERR_CPU_LSUESR_ERRINDEX_RD(val), + MEMERR_CPU_LSUESR_ERRINFO_RD(val)); + if (val & MEMERR_CPU_LSUESR_CERR_MASK) + dev_err(edac_dev->dev, + "One or more correctable error\n"); + if (val & MEMERR_CPU_LSUESR_MULTCERR_MASK) + dev_err(edac_dev->dev, "Multiple correctable error\n"); + switch (MEMERR_CPU_LSUESR_ERRTYPE_RD(val)) { + case 0: + dev_err(edac_dev->dev, "Load tag error\n"); + break; + case 1: + dev_err(edac_dev->dev, "Load data error\n"); + break; + case 2: + dev_err(edac_dev->dev, "WSL multihit error\n"); + break; + case 3: + dev_err(edac_dev->dev, "Store tag error\n"); + break; + case 4: + dev_err(edac_dev->dev, + "DTB multihit from load pipeline error\n"); + break; + case 5: + dev_err(edac_dev->dev, + "DTB multihit from store pipeline error\n"); + break; + } + writel(val, pg_f + MEMERR_CPU_LSUESRA_PAGE_OFFSET); + if (val & (MEMERR_CPU_LSUESR_CERR_MASK | + MEMERR_CPU_LSUESR_MULTCERR_MASK)) + edac_device_handle_ce(edac_dev, 0, 0, + edac_dev->ctl_name); + else + edac_device_handle_ue(edac_dev, 0, 0, + edac_dev->ctl_name); + } + + val = readl(pg_f + MEMERR_CPU_MMUESR_PAGE_OFFSET); + if (val) { + dev_err(edac_dev->dev, "CPU%d memory error MMU 0x%08X\n", + ctx->pmd * MAX_CPU_PER_PMD + cpu_idx, val); + writel(val, pg_f + MEMERR_CPU_MMUESRA_PAGE_OFFSET); + edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); + } +} + +static void xgene_edac_pmd_l2_check(struct edac_device_ctl_info *edac_dev) +{ + struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; + u32 __iomem *pg_d; + u32 __iomem *pg_e; + u32 val_hi; + u32 val_lo; + u32 val; + + /* Check L2 */ + pg_e = ctx->pmd_csr + CPU_MEMERR_L2C_PAGE; + val = readl(pg_e + MEMERR_L2C_L2ESR_PAGE_OFFSET); + if (val) { + val_lo = readl(pg_e + MEMERR_L2C_L2EALR_PAGE_OFFSET); + val_hi = readl(pg_e + MEMERR_L2C_L2EAHR_PAGE_OFFSET); + dev_err(edac_dev->dev, + "PMD%d memory error L2C L2ESR 0x%08X @ 0x%08X.%08X\n", + ctx->pmd, val, val_hi, val_lo); + dev_err(edac_dev->dev, + "ErrSyndrome 0x%02X ErrWay 0x%02X ErrCpu %d ErrGroup 0x%02X ErrAction 0x%02X\n", + MEMERR_L2C_L2ESR_ERRSYN_RD(val), + MEMERR_L2C_L2ESR_ERRWAY_RD(val), + MEMERR_L2C_L2ESR_ERRCPU_RD(val), + MEMERR_L2C_L2ESR_ERRGROUP_RD(val), + MEMERR_L2C_L2ESR_ERRACTION_RD(val)); + + if (val & MEMERR_L2C_L2ESR_ERR_MASK) + dev_err(edac_dev->dev, + "One or more correctable error\n"); + if (val & MEMERR_L2C_L2ESR_MULTICERR_MASK) + dev_err(edac_dev->dev, "Multiple correctable error\n"); + if (val & MEMERR_L2C_L2ESR_UCERR_MASK) + dev_err(edac_dev->dev, + "One or more uncorrectable error\n"); + if (val & MEMERR_L2C_L2ESR_MULTUCERR_MASK) + dev_err(edac_dev->dev, + "Multiple uncorrectable error\n"); + + switch (MEMERR_L2C_L2ESR_ERRTYPE_RD(val)) { + case 0: + dev_err(edac_dev->dev, "Outbound SDB parity error\n"); + break; + case 1: + dev_err(edac_dev->dev, "Inbound SDB parity error\n"); + break; + case 2: + dev_err(edac_dev->dev, "Tag ECC error\n"); + break; + case 3: + dev_err(edac_dev->dev, "Data ECC error\n"); + break; + } + + writel(0x0, pg_e + MEMERR_L2C_L2EALR_PAGE_OFFSET); + writel(0x0, pg_e + MEMERR_L2C_L2EAHR_PAGE_OFFSET); + writel(val, pg_e + MEMERR_L2C_L2ESRA_PAGE_OFFSET); + + if (val & (MEMERR_L2C_L2ESR_ERR_MASK | + MEMERR_L2C_L2ESR_MULTICERR_MASK)) + edac_device_handle_ce(edac_dev, 0, 0, + edac_dev->ctl_name); + if (val & (MEMERR_L2C_L2ESR_UCERR_MASK | + MEMERR_L2C_L2ESR_MULTUCERR_MASK)) + edac_device_handle_ue(edac_dev, 0, 0, + edac_dev->ctl_name); + } + + /* Check if any memory request timed out on L2 cache */ + pg_d = ctx->pmd_csr + CPU_L2C_PAGE; + val = readl(pg_d + CPUX_L2C_L2RTOSR_PAGE_OFFSET); + if (val) { + val_lo = readl(pg_d + CPUX_L2C_L2RTOALR_PAGE_OFFSET); + val_hi = readl(pg_d + CPUX_L2C_L2RTOAHR_PAGE_OFFSET); + dev_err(edac_dev->dev, + "PMD%d L2C error L2C RTOSR 0x%08X @ 0x%08X.%08X\n", + ctx->pmd, val, val_hi, val_lo); + writel(0x0, pg_d + CPUX_L2C_L2RTOALR_PAGE_OFFSET); + writel(0x0, pg_d + CPUX_L2C_L2RTOAHR_PAGE_OFFSET); + writel(0x0, pg_d + CPUX_L2C_L2RTOSR_PAGE_OFFSET); + } +} + +static void xgene_edac_pmd_check(struct edac_device_ctl_info *edac_dev) +{ + struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; + u32 pcp_hp_stat; + int i; + + pcp_hp_stat = readl(ctx->pcp_csr + PCPHPERRINTSTS); + if (!((PMD0_MERR_MASK << ctx->pmd) & pcp_hp_stat)) + return; + + /* Check CPU L1 error */ + for (i = 0; i < MAX_CPU_PER_PMD; i++) + xgene_edac_pmd_l1_check(edac_dev, i); + + /* Check CPU L2 error */ + xgene_edac_pmd_l2_check(edac_dev); +} + +static irqreturn_t xgene_edac_pmd_isr(int irq, void *dev_id) +{ + struct edac_device_ctl_info *edac_dev = dev_id; + struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; + u32 pcp_hp_stat; + + pcp_hp_stat = readl(ctx->pcp_csr + PCPHPERRINTSTS); + if (!(pcp_hp_stat & (PMD0_MERR_MASK << ctx->pmd))) + return IRQ_NONE; + + xgene_edac_pmd_check(edac_dev); + + return IRQ_HANDLED; +} + +static void xgene_edac_pmd_cpu_hw_cfg(struct edac_device_ctl_info *edac_dev, + int cpu) +{ + struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; + void __iomem *pg_f = ctx->pmd_csr + cpu * CPU_CSR_STRIDE + + CPU_MEMERR_CPU_PAGE; + + /* + * Clear CPU memory error: + * MEMERR_CPU_ICFESRA, MEMERR_CPU_LSUESRA, and MEMERR_CPU_MMUESRA + */ + writel(0x00000000, pg_f + MEMERR_CPU_ICFESRA_PAGE_OFFSET); + writel(0x00000000, pg_f + MEMERR_CPU_LSUESRA_PAGE_OFFSET); + writel(0x00000000, pg_f + MEMERR_CPU_MMUESRA_PAGE_OFFSET); + + /* + * Enable CPU memory error: + * MEMERR_CPU_ICFESRA, MEMERR_CPU_LSUESRA, and MEMERR_CPU_MMUESRA + */ + writel(0x00000301, pg_f + MEMERR_CPU_ICFECR_PAGE_OFFSET); + writel(0x00000301, pg_f + MEMERR_CPU_LSUECR_PAGE_OFFSET); + writel(0x00000101, pg_f + MEMERR_CPU_MMUECR_PAGE_OFFSET); +} + +static void xgene_edac_pmd_hw_cfg(struct edac_device_ctl_info *edac_dev) +{ + struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; + void __iomem *pg_d = ctx->pmd_csr + CPU_L2C_PAGE; + void __iomem *pg_e = ctx->pmd_csr + CPU_MEMERR_L2C_PAGE; + + /* + * Clear PMD memory error: + * MEMERR_L2C_L2ESRA, MEMERR_L2C_L2EALR, and MEMERR_L2C_L2EAHR + */ + writel(0x00000000, pg_e + MEMERR_L2C_L2ESRA_PAGE_OFFSET); + writel(0x00000000, pg_e + MEMERR_L2C_L2EALR_PAGE_OFFSET); + writel(0x00000000, pg_e + MEMERR_L2C_L2EAHR_PAGE_OFFSET); + + /* + * Clear L2 error: + * L2C_L2RTOSR, L2C_L2RTOALR, L2C_L2RTOAHR + */ + writel(0x00000000, pg_d + CPUX_L2C_L2RTOSR_PAGE_OFFSET); + writel(0x00000000, pg_d + CPUX_L2C_L2RTOALR_PAGE_OFFSET); + writel(0x00000000, pg_d + CPUX_L2C_L2RTOAHR_PAGE_OFFSET); + + /* Enable PMD memory error - MEMERR_L2C_L2ECR and L2C_L2RTOCR */ + writel(0x00000703, pg_e + MEMERR_L2C_L2ECR_PAGE_OFFSET); + writel(0x00000119, pg_d + CPUX_L2C_L2RTOCR_PAGE_OFFSET); +} + +static void xgene_edac_pmd_hw_ctl(struct edac_device_ctl_info *edac_dev, + bool enable) +{ + struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; + u32 val; + int i; + + /* Enable PMD error interrupt */ + if (edac_dev->op_state == OP_RUNNING_INTERRUPT) { + mutex_lock(&xgene_edac_lock); + + val = readl(ctx->pcp_csr + PCPHPERRINTMSK); + if (enable) + val &= ~(PMD0_MERR_MASK << ctx->pmd); + else + val |= PMD0_MERR_MASK << ctx->pmd; + writel(val, ctx->pcp_csr + PCPHPERRINTMSK); + + mutex_unlock(&xgene_edac_lock); + } + + if (enable) { + xgene_edac_pmd_hw_cfg(edac_dev); + + /* Two CPU's per an PMD */ + for (i = 0; i < MAX_CPU_PER_PMD; i++) + xgene_edac_pmd_cpu_hw_cfg(edac_dev, i); + } +} + +#if defined(CONFIG_EDAC_DEBUG) +static ssize_t xgene_edac_pmd_l1_inject_ctrl_show( + struct edac_device_ctl_info *edac_dev, char *data) +{ + struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; + void __iomem *cpu0_pg_f = ctx->pmd_csr + CPU_MEMERR_CPU_PAGE; + void __iomem *cpu1_pg_f = ctx->pmd_csr + CPU_CSR_STRIDE + + CPU_MEMERR_CPU_PAGE; + + return sprintf(data, "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X", + readl(cpu0_pg_f + MEMERR_CPU_ICFESRA_PAGE_OFFSET), + readl(cpu0_pg_f + MEMERR_CPU_LSUESRA_PAGE_OFFSET), + readl(cpu0_pg_f + MEMERR_CPU_MMUESRA_PAGE_OFFSET), + readl(cpu1_pg_f + MEMERR_CPU_ICFESRA_PAGE_OFFSET), + readl(cpu1_pg_f + MEMERR_CPU_LSUESRA_PAGE_OFFSET), + readl(cpu1_pg_f + MEMERR_CPU_MMUESRA_PAGE_OFFSET)); +} + +static ssize_t xgene_edac_pmd_l1_inject_ctrl_store( + struct edac_device_ctl_info *edac_dev, const char *data, size_t count) +{ + struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; + void __iomem *cpu0_pg_f = ctx->pmd_csr + CPU_MEMERR_CPU_PAGE; + void __iomem *cpu1_pg_f = ctx->pmd_csr + CPU_CSR_STRIDE + + CPU_MEMERR_CPU_PAGE; + u32 val; + + if (isdigit(*data)) { + if (kstrtou32(data, 0, &val)) + return 0; + writel(val, cpu0_pg_f + MEMERR_CPU_ICFESRA_PAGE_OFFSET); + writel(val, cpu0_pg_f + MEMERR_CPU_LSUESRA_PAGE_OFFSET); + writel(val, cpu0_pg_f + MEMERR_CPU_MMUESRA_PAGE_OFFSET); + writel(val, cpu1_pg_f + MEMERR_CPU_ICFESRA_PAGE_OFFSET); + writel(val, cpu1_pg_f + MEMERR_CPU_LSUESRA_PAGE_OFFSET); + writel(val, cpu1_pg_f + MEMERR_CPU_MMUESRA_PAGE_OFFSET); + return count; + } + return 0; +} + +static ssize_t xgene_edac_pmd_l2_inject_ctrl_show( + struct edac_device_ctl_info *edac_dev, char *data) +{ + struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; + void __iomem *pg_e = ctx->pmd_csr + CPU_MEMERR_L2C_PAGE; + + return sprintf(data, "0x%08X", + readl(pg_e + MEMERR_L2C_L2ESRA_PAGE_OFFSET)); +} + +static ssize_t xgene_edac_pmd_l2_inject_ctrl_store( + struct edac_device_ctl_info *edac_dev, const char *data, size_t count) +{ + struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; + void __iomem *pg_e = ctx->pmd_csr + CPU_MEMERR_L2C_PAGE; + u32 val; + + if (isdigit(*data)) { + if (kstrtou32(data, 0, &val)) + return 0; + writel(val, + pg_e + MEMERR_L2C_L2ESRA_PAGE_OFFSET); + return count; + } + return 0; +} + +static struct edac_dev_sysfs_attribute xgene_edac_pmd_sysfs_attributes[] = { + { .attr = { + .name = "l1_inject_ctrl", + .mode = (S_IRUGO | S_IWUSR) + }, + .show = xgene_edac_pmd_l1_inject_ctrl_show, + .store = xgene_edac_pmd_l1_inject_ctrl_store }, + { .attr = { + .name = "l2_inject_ctrl", + .mode = (S_IRUGO | S_IWUSR) + }, + .show = xgene_edac_pmd_l2_inject_ctrl_show, + .store = xgene_edac_pmd_l2_inject_ctrl_store }, + + /* End of list */ + { .attr = {.name = NULL } } +}; +#endif + +static int xgene_edac_pmd_probe(struct platform_device *pdev) +{ + struct edac_device_ctl_info *edac_dev; + struct xgene_edac_pmd_ctx *ctx; + char edac_name[10]; + struct resource *res; + int pmd; + int rc = 0; + + if (!devres_open_group(&pdev->dev, xgene_edac_pmd_probe, GFP_KERNEL)) + return -ENOMEM; + + /* Find the PMD number from its address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res || resource_size(res) <= 0) { + rc = -ENODEV; + goto err_group; + } + pmd = ((res->start >> 20) & 0x1E) >> 1; + + sprintf(edac_name, "l2c%d", pmd); + edac_dev = edac_device_alloc_ctl_info(sizeof(*ctx), + edac_name, 1, "l2c", 1, 2, NULL, + 0, edac_device_alloc_index()); + if (!edac_dev) { + rc = -ENOMEM; + goto err_group; + } + + ctx = edac_dev->pvt_info; + ctx->name = "xgene_pmd_err"; + ctx->pmd = pmd; + edac_dev->dev = &pdev->dev; + dev_set_drvdata(edac_dev->dev, edac_dev); + edac_dev->ctl_name = ctx->name; + edac_dev->dev_name = ctx->name; + edac_dev->mod_name = EDAC_MOD_STR; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "no PCP resource address\n"); + rc = -EINVAL; + goto err_free; + } + ctx->pcp_csr = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (IS_ERR(ctx->pcp_csr)) { + dev_err(&pdev->dev, "no PCP resource address\n"); + rc = PTR_ERR(ctx->pcp_csr); + goto err_free; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) { + dev_err(&pdev->dev, "no PMD resource address\n"); + rc = -EINVAL; + goto err_free; + } + ctx->pmd_csr = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (IS_ERR(ctx->pmd_csr)) { + dev_err(&pdev->dev, "no PMD resource address\n"); + rc = PTR_ERR(ctx->pmd_csr); + goto err_free; + } + + if (edac_op_state == EDAC_OPSTATE_POLL) + edac_dev->edac_check = xgene_edac_pmd_check; + +#if defined(CONFIG_EDAC_DEBUG) + edac_dev->sysfs_attributes = xgene_edac_pmd_sysfs_attributes; +#endif + + rc = edac_device_add_device(edac_dev); + if (rc > 0) { + dev_err(&pdev->dev, "failed edac_device_add_device()\n"); + rc = -ENOMEM; + goto err_free; + } + + if (edac_op_state == EDAC_OPSTATE_INT) { + int irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "No IRQ resource\n"); + rc = -EINVAL; + goto err_del; + } + rc = devm_request_irq(&pdev->dev, irq, + xgene_edac_pmd_isr, IRQF_SHARED, + dev_name(&pdev->dev), edac_dev); + if (rc) { + dev_err(&pdev->dev, "Could not request IRQ %d\n", irq); + goto err_del; + } + edac_dev->op_state = OP_RUNNING_INTERRUPT; + } + + xgene_edac_pmd_hw_ctl(edac_dev, 1); + + devres_remove_group(&pdev->dev, xgene_edac_pmd_probe); + + dev_info(&pdev->dev, "X-Gene EDAC PMD registered\n"); + return 0; + +err_del: + edac_device_del_device(&pdev->dev); +err_free: + edac_device_free_ctl_info(edac_dev); +err_group: + devres_release_group(&pdev->dev, xgene_edac_pmd_probe); + return rc; +} + +static int xgene_edac_pmd_remove(struct platform_device *pdev) +{ + struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&pdev->dev); + + xgene_edac_pmd_hw_ctl(edac_dev, 0); + edac_device_del_device(&pdev->dev); + edac_device_free_ctl_info(edac_dev); + return 0; +} + +#ifdef CONFIG_OF +static struct of_device_id xgene_edac_pmd_of_match[] = { + { .compatible = "apm,xgene-edac-pmd" }, + {}, +}; +MODULE_DEVICE_TABLE(of, xgene_edac_pmd_of_match); +#endif + +static struct platform_driver xgene_edac_pmd_driver = { + .probe = xgene_edac_pmd_probe, + .remove = xgene_edac_pmd_remove, + .driver = { + .name = "xgene-edac-pmd", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(xgene_edac_pmd_of_match), + }, +}; + +/* L3 Error device */ +#define L3C_ESR (0x0A * 4) +#define L3C_ESR_DATATAG_MASK BIT(9) +#define L3C_ESR_MULTIHIT_MASK BIT(8) +#define L3C_ESR_UCEVICT_MASK BIT(6) +#define L3C_ESR_MULTIUCERR_MASK BIT(5) +#define L3C_ESR_MULTICERR_MASK BIT(4) +#define L3C_ESR_UCERR_MASK BIT(3) +#define L3C_ESR_CERR_MASK BIT(2) +#define L3C_ESR_UCERRINTR_MASK BIT(1) +#define L3C_ESR_CERRINTR_MASK BIT(0) +#define L3C_ECR (0x0B * 4) +#define L3C_ECR_UCINTREN BIT(3) +#define L3C_ECR_CINTREN BIT(2) +#define L3C_UCERREN BIT(1) +#define L3C_CERREN BIT(0) +#define L3C_ELR (0x0C * 4) +#define L3C_ELR_ERRSYN(src) ((src & 0xFF800000) >> 23) +#define L3C_ELR_ERRWAY(src) ((src & 0x007E0000) >> 17) +#define L3C_ELR_AGENTID(src) ((src & 0x0001E000) >> 13) +#define L3C_ELR_ERRGRP(src) ((src & 0x00000F00) >> 8) +#define L3C_ELR_OPTYPE(src) ((src & 0x000000F0) >> 4) +#define L3C_ELR_PADDRHIGH(src) (src & 0x0000000F) +#define L3C_AELR (0x0D * 4) +#define L3C_BELR (0x0E * 4) +#define L3C_BELR_BANK(src) (src & 0x0000000F) + +struct xgene_edac_dev_ctx { + char *name; + int edac_idx; + void __iomem *pcp_csr; + void __iomem *dev_csr; +}; + +static void xgene_edac_l3_check(struct edac_device_ctl_info *edac_dev) +{ + struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; + u32 l3cesr; + u32 l3celr; + u32 l3caelr; + u32 l3cbelr; + + l3cesr = readl(ctx->dev_csr + L3C_ESR); + if (!(l3cesr & (L3C_ESR_UCERR_MASK | L3C_ESR_CERR_MASK))) + return; + + if (l3cesr & L3C_ESR_UCERR_MASK) + dev_err(edac_dev->dev, "L3C uncorrectable error\n"); + if (l3cesr & L3C_ESR_CERR_MASK) + dev_warn(edac_dev->dev, "L3C correctable error\n"); + + l3celr = readl(ctx->dev_csr + L3C_ELR); + l3caelr = readl(ctx->dev_csr + L3C_AELR); + l3cbelr = readl(ctx->dev_csr + L3C_BELR); + if (l3cesr & L3C_ESR_MULTIHIT_MASK) + dev_err(edac_dev->dev, "L3C multiple hit error\n"); + if (l3cesr & L3C_ESR_UCEVICT_MASK) + dev_err(edac_dev->dev, + "L3C dropped eviction of line with error\n"); + if (l3cesr & L3C_ESR_MULTIUCERR_MASK) + dev_err(edac_dev->dev, "L3C multiple uncorrectable error\n"); + if (l3cesr & L3C_ESR_DATATAG_MASK) + dev_err(edac_dev->dev, + "L3C data error syndrome 0x%X group 0x%X\n", + L3C_ELR_ERRSYN(l3celr), L3C_ELR_ERRGRP(l3celr)); + else + dev_err(edac_dev->dev, + "L3C tag error syndrome 0x%X Way of Tag 0x%X Agent ID 0x%X Operation type 0x%X\n", + L3C_ELR_ERRSYN(l3celr), L3C_ELR_ERRWAY(l3celr), + L3C_ELR_AGENTID(l3celr), L3C_ELR_OPTYPE(l3celr)); + /* + * NOTE: Address [41:38] in L3C_ELR_PADDRHIGH(l3celr). + * Address [37:6] in l3caelr. Lower 6 bits are zero. + */ + dev_err(edac_dev->dev, "L3C error address 0x%08X.%08X bank %d\n", + L3C_ELR_PADDRHIGH(l3celr) << 6 | (l3caelr >> 26), + (l3caelr & 0x3FFFFFFF) << 6, L3C_BELR_BANK(l3cbelr)); + dev_err(edac_dev->dev, + "L3C error status register value 0x%X\n", l3cesr); + + /* Clear L3C error interrupt */ + writel(0, ctx->dev_csr + L3C_ESR); + + if (l3cesr & L3C_ESR_CERR_MASK) + edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); + if (l3cesr & L3C_ESR_UCERR_MASK) + edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); +} + +static irqreturn_t xgene_edac_l3_isr(int irq, void *dev_id) +{ + struct edac_device_ctl_info *edac_dev = dev_id; + struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; + u32 l3cesr; + + l3cesr = readl(ctx->dev_csr + L3C_ESR); + if (!(l3cesr & (L3C_ESR_UCERRINTR_MASK | L3C_ESR_CERRINTR_MASK))) + return IRQ_NONE; + + xgene_edac_l3_check(edac_dev); + + return IRQ_HANDLED; +} + +static void xgene_edac_l3_hw_ctl(struct edac_device_ctl_info *edac_dev, + bool enable) +{ + struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; + u32 val; + + val = readl(ctx->dev_csr + L3C_ECR); + val |= L3C_UCERREN | L3C_CERREN; + /* On disable, we just disable interrupt but keep error enabled */ + if (edac_dev->op_state == OP_RUNNING_INTERRUPT) { + if (enable) + val |= L3C_ECR_UCINTREN | L3C_ECR_CINTREN; + else + val &= ~(L3C_ECR_UCINTREN | L3C_ECR_CINTREN); + } + writel(val, ctx->dev_csr + L3C_ECR); + + mutex_lock(&xgene_edac_lock); + + if (edac_dev->op_state == OP_RUNNING_INTERRUPT) { + /* Enable L3C error top level interrupt */ + val = readl(ctx->pcp_csr + PCPHPERRINTMSK); + if (enable) + val &= ~L3C_UNCORR_ERR_MASK; + else + val |= L3C_UNCORR_ERR_MASK; + writel(val, ctx->pcp_csr + PCPHPERRINTMSK); + val = readl(ctx->pcp_csr + PCPLPERRINTMSK); + if (enable) + val &= ~L3C_CORR_ERR_MASK; + else + val |= L3C_CORR_ERR_MASK; + writel(val, ctx->pcp_csr + PCPLPERRINTMSK); + } + + mutex_unlock(&xgene_edac_lock); +} + +#if defined(CONFIG_EDAC_DEBUG) +static ssize_t xgene_edac_l3_inject_ctrl_show( + struct edac_device_ctl_info *edac_dev, char *data) +{ + struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; + + return sprintf(data, "0x%08X", readl(ctx->dev_csr + L3C_ESR)); +} + +static ssize_t xgene_edac_l3_inject_ctrl_store( + struct edac_device_ctl_info *edac_dev, const char *data, size_t count) +{ + struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; + u32 val; + + if (isdigit(*data)) { + if (kstrtou32(data, 0, &val)) + return 0; + writel(val, ctx->dev_csr + L3C_ESR); + return count; + } + return 0; +} + +static struct edac_dev_sysfs_attribute xgene_edac_l3_sysfs_attributes[] = { + { .attr = { + .name = "inject_ctrl", + .mode = (S_IRUGO | S_IWUSR) + }, + .show = xgene_edac_l3_inject_ctrl_show, + .store = xgene_edac_l3_inject_ctrl_store }, + + /* End of list */ + { .attr = {.name = NULL } } +}; +#endif + +static int xgene_edac_l3_probe(struct platform_device *pdev) +{ + struct edac_device_ctl_info *edac_dev; + struct xgene_edac_dev_ctx *ctx; + struct resource *res; + int rc = 0; + + if (!devres_open_group(&pdev->dev, xgene_edac_l3_probe, GFP_KERNEL)) + return -ENOMEM; + + edac_dev = edac_device_alloc_ctl_info(sizeof(*ctx), + "l3c", 1, "l3c", 1, 0, NULL, 0, + edac_device_alloc_index()); + if (!edac_dev) { + rc = -ENOMEM; + goto err; + } + + ctx = edac_dev->pvt_info; + ctx->name = "xgene_l3_err"; + edac_dev->dev = &pdev->dev; + dev_set_drvdata(edac_dev->dev, edac_dev); + edac_dev->ctl_name = ctx->name; + edac_dev->dev_name = ctx->name; + edac_dev->mod_name = EDAC_MOD_STR; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "no PCP resource address\n"); + rc = -EINVAL; + goto err1; + } + ctx->pcp_csr = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (IS_ERR(ctx->pcp_csr)) { + dev_err(&pdev->dev, "no PCP resource address\n"); + rc = PTR_ERR(ctx->pcp_csr); + goto err1; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + ctx->dev_csr = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(ctx->dev_csr)) { + dev_err(&pdev->dev, "no L3 resource address\n"); + rc = PTR_ERR(ctx->dev_csr); + goto err1; + } + + if (edac_op_state == EDAC_OPSTATE_POLL) + edac_dev->edac_check = xgene_edac_l3_check; + +#if defined(CONFIG_EDAC_DEBUG) + edac_dev->sysfs_attributes = xgene_edac_l3_sysfs_attributes; +#endif + + rc = edac_device_add_device(edac_dev); + if (rc > 0) { + dev_err(&pdev->dev, "failed edac_device_add_device()\n"); + rc = -ENOMEM; + goto err1; + } + + if (edac_op_state == EDAC_OPSTATE_INT) { + int irq; + int i; + + for (i = 0; i < 2; i++) { + irq = platform_get_irq(pdev, i); + if (irq < 0) { + dev_err(&pdev->dev, "No IRQ resource\n"); + rc = -EINVAL; + goto err2; + } + rc = devm_request_irq(&pdev->dev, irq, + xgene_edac_l3_isr, IRQF_SHARED, + dev_name(&pdev->dev), edac_dev); + if (rc) { + dev_err(&pdev->dev, + "Could not request IRQ %d\n", irq); + goto err2; + } + } + edac_dev->op_state = OP_RUNNING_INTERRUPT; + } + + xgene_edac_l3_hw_ctl(edac_dev, 1); + + devres_remove_group(&pdev->dev, xgene_edac_l3_probe); + + dev_info(&pdev->dev, "X-Gene EDAC L3 registered\n"); + return 0; + +err2: + edac_device_del_device(&pdev->dev); +err1: + edac_device_free_ctl_info(edac_dev); +err: + devres_release_group(&pdev->dev, xgene_edac_l3_probe); + return rc; +} + +static int xgene_edac_l3_remove(struct platform_device *pdev) +{ + struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&pdev->dev); + + xgene_edac_l3_hw_ctl(edac_dev, 0); + edac_device_del_device(&pdev->dev); + edac_device_free_ctl_info(edac_dev); + return 0; +} + +#ifdef CONFIG_OF +static struct of_device_id xgene_edac_l3_of_match[] = { + { .compatible = "apm,xgene-edac-l3" }, + {}, +}; +MODULE_DEVICE_TABLE(of, xgene_edac_l3_of_match); +#endif + +static struct platform_driver xgene_edac_l3_driver = { + .probe = xgene_edac_l3_probe, + .remove = xgene_edac_l3_remove, + .driver = { + .name = "xgene-edac-l3", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(xgene_edac_l3_of_match), + }, +}; + +/* SoC Error device */ +#define IOBAXIS0TRANSERRINTSTS 0x0000 +#define IOBAXIS0_M_ILLEGAL_ACCESS_MASK BIT(1) +#define IOBAXIS0_ILLEGAL_ACCESS_MASK BIT(0) +#define IOBAXIS0TRANSERRINTMSK 0x0004 +#define IOBAXIS0TRANSERRREQINFOL 0x0008 +#define IOBAXIS0TRANSERRREQINFOH 0x000c +#define REQTYPE_RD(src) (((src) & BIT(0))) +#define ERRADDRH_RD(src) (((src) & 0xffc00000) >> 22) +#define IOBAXIS1TRANSERRINTSTS 0x0010 +#define IOBAXIS1TRANSERRINTMSK 0x0014 +#define IOBAXIS1TRANSERRREQINFOL 0x0018 +#define IOBAXIS1TRANSERRREQINFOH 0x001c +#define IOBPATRANSERRINTSTS 0x0020 +#define IOBPA_M_REQIDRAM_CORRUPT_MASK BIT(7) +#define IOBPA_REQIDRAM_CORRUPT_MASK BIT(6) +#define IOBPA_M_TRANS_CORRUPT_MASK BIT(5) +#define IOBPA_TRANS_CORRUPT_MASK BIT(4) +#define IOBPA_M_WDATA_CORRUPT_MASK BIT(3) +#define IOBPA_WDATA_CORRUPT_MASK BIT(2) +#define IOBPA_M_RDATA_CORRUPT_MASK BIT(1) +#define IOBPA_RDATA_CORRUPT_MASK BIT(0) +#define IOBBATRANSERRINTSTS 0x0030 +#define M_ILLEGAL_ACCESS_MASK 0x00008000 +#define ILLEGAL_ACCESS_MASK 0x00004000 +#define M_WIDRAM_CORRUPT_MASK 0x00002000 +#define WIDRAM_CORRUPT_MASK BIT(12) +#define M_RIDRAM_CORRUPT_MASK BIT(11) +#define RIDRAM_CORRUPT_MASK BIT(10) +#define M_TRANS_CORRUPT_MASK BIT(9) +#define TRANS_CORRUPT_MASK BIT(8) +#define M_WDATA_CORRUPT_MASK BIT(7) +#define WDATA_CORRUPT_MASK BIT(6) +#define M_RBM_POISONED_REQ_MASK BIT(5) +#define RBM_POISONED_REQ_MASK BIT(4) +#define M_XGIC_POISONED_REQ_MASK BIT(3) +#define XGIC_POISONED_REQ_MASK BIT(2) +#define M_WRERR_RESP_MASK BIT(1) +#define WRERR_RESP_MASK BIT(0) +#define IOBBATRANSERRREQINFOL 0x0038 +#define IOBBATRANSERRREQINFOH 0x003c +#define REQTYPE_F2_RD(src) (((src) & BIT(0))) +#define ERRADDRH_F2_RD(src) (((src) & 0xffc00000) >> 22) +#define IOBBATRANSERRCSWREQID 0x0040 +#define XGICTRANSERRINTSTS 0x0050 +#define M_WR_ACCESS_ERR_MASK BIT(3) +#define WR_ACCESS_ERR_MASK BIT(2) +#define M_RD_ACCESS_ERR_MASK BIT(1) +#define RD_ACCESS_ERR_MASK BIT(0) +#define XGICTRANSERRINTMSK 0x0054 +#define XGICTRANSERRREQINFO 0x0058 +#define REQTYPE_MASK 0x04000000 +#define ERRADDR_RD(src) ((src) & 0x03ffffff) +#define GLBL_ERR_STS 0x0800 +#define MDED_ERR_MASK BIT(3) +#define DED_ERR_MASK BIT(2) +#define MSEC_ERR_MASK BIT(1) +#define SEC_ERR_MASK BIT(0) +#define GLBL_SEC_ERRL 0x0810 +#define GLBL_SEC_ERRH 0x0818 +#define GLBL_MSEC_ERRL 0x0820 +#define GLBL_MSEC_ERRH 0x0828 +#define GLBL_DED_ERRL 0x0830 +#define GLBL_DED_ERRLMASK 0x0834 +#define GLBL_DED_ERRH 0x0838 +#define GLBL_DED_ERRHMASK 0x083c +#define GLBL_MDED_ERRL 0x0840 +#define GLBL_MDED_ERRLMASK 0x0844 +#define GLBL_MDED_ERRH 0x0848 +#define GLBL_MDED_ERRHMASK 0x084c + +static void xgene_edac_iob_gic_report(struct edac_device_ctl_info *edac_dev) +{ + struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; + u32 err_addr_lo; + u32 err_addr_hi; + u32 reg; + u32 info; + + /* GIC transaction error interrupt */ + reg = readl(ctx->dev_csr + XGICTRANSERRINTSTS); + if (reg) { + dev_err(edac_dev->dev, "XGIC transaction error\n"); + if (reg & RD_ACCESS_ERR_MASK) + dev_err(edac_dev->dev, "XGIC read size error\n"); + if (reg & M_RD_ACCESS_ERR_MASK) + dev_err(edac_dev->dev, + "Multiple XGIC read size error\n"); + if (reg & WR_ACCESS_ERR_MASK) + dev_err(edac_dev->dev, "XGIC write size error\n"); + if (reg & M_WR_ACCESS_ERR_MASK) + dev_err(edac_dev->dev, + "Multiple XGIC write size error\n"); + info = readl(ctx->dev_csr + XGICTRANSERRREQINFO); + dev_err(edac_dev->dev, "XGIC %s access @ 0x%08X (0x%08X)\n", + info & REQTYPE_MASK ? "read" : "write", + ERRADDR_RD(info), info); + writel(reg, ctx->dev_csr + XGICTRANSERRINTSTS); + } + + /* IOB memory error */ + reg = readl(ctx->dev_csr + GLBL_ERR_STS); + if (reg) { + if (reg & SEC_ERR_MASK) { + err_addr_lo = readl(ctx->dev_csr + GLBL_SEC_ERRL); + err_addr_hi = readl(ctx->dev_csr + GLBL_SEC_ERRH); + dev_err(edac_dev->dev, + "IOB single-bit correctable memory at 0x%08X.%08X error\n", + err_addr_lo, err_addr_hi); + writel(err_addr_lo, ctx->dev_csr + GLBL_SEC_ERRL); + writel(err_addr_hi, ctx->dev_csr + GLBL_SEC_ERRH); + } + if (reg & MSEC_ERR_MASK) { + err_addr_lo = readl(ctx->dev_csr + GLBL_MSEC_ERRL); + err_addr_hi = readl(ctx->dev_csr + GLBL_MSEC_ERRH); + dev_err(edac_dev->dev, + "IOB multiple single-bit correctable memory at 0x%08X.%08X error\n", + err_addr_lo, err_addr_hi); + writel(err_addr_lo, ctx->dev_csr + GLBL_MSEC_ERRL); + writel(err_addr_hi, ctx->dev_csr + GLBL_MSEC_ERRH); + } + if (reg & (SEC_ERR_MASK | MSEC_ERR_MASK)) + edac_device_handle_ce(edac_dev, 0, 0, + edac_dev->ctl_name); + + if (reg & DED_ERR_MASK) { + err_addr_lo = readl(ctx->dev_csr + GLBL_DED_ERRL); + err_addr_hi = readl(ctx->dev_csr + GLBL_DED_ERRH); + dev_err(edac_dev->dev, + "IOB double-bit uncorrectable memory at 0x%08X.%08X error\n", + err_addr_lo, err_addr_hi); + writel(err_addr_lo, ctx->dev_csr + GLBL_DED_ERRL); + writel(err_addr_hi, ctx->dev_csr + GLBL_DED_ERRH); + } + if (reg & MDED_ERR_MASK) { + err_addr_lo = readl(ctx->dev_csr + GLBL_MDED_ERRL); + err_addr_hi = readl(ctx->dev_csr + GLBL_MDED_ERRH); + dev_err(edac_dev->dev, + "Multiple IOB double-bit uncorrectable memory at 0x%08X.%08X error\n", + err_addr_lo, err_addr_hi); + writel(err_addr_lo, ctx->dev_csr + GLBL_MDED_ERRL); + writel(err_addr_hi, ctx->dev_csr + GLBL_MDED_ERRH); + } + if (reg & (DED_ERR_MASK | MDED_ERR_MASK)) + edac_device_handle_ue(edac_dev, 0, 0, + edac_dev->ctl_name); + } +} + +static void xgene_edac_rb_report(struct edac_device_ctl_info *edac_dev) +{ + struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; + u32 err_addr_lo; + u32 err_addr_hi; + u32 reg; + + /* IOB Bridge agent transaction error interrupt */ + reg = readl(ctx->dev_csr + IOBBATRANSERRINTSTS); + if (!reg) + return; + + dev_err(edac_dev->dev, "IOB bridge agent (BA) transaction error\n"); + if (reg & WRERR_RESP_MASK) + dev_err(edac_dev->dev, "IOB BA write response error\n"); + if (reg & M_WRERR_RESP_MASK) + dev_err(edac_dev->dev, + "Multiple IOB BA write response error\n"); + if (reg & XGIC_POISONED_REQ_MASK) + dev_err(edac_dev->dev, "IOB BA XGIC poisoned write error\n"); + if (reg & M_XGIC_POISONED_REQ_MASK) + dev_err(edac_dev->dev, + "Multiple IOB BA XGIC poisoned write error\n"); + if (reg & RBM_POISONED_REQ_MASK) + dev_err(edac_dev->dev, "IOB BA RBM poisoned write error\n"); + if (reg & M_RBM_POISONED_REQ_MASK) + dev_err(edac_dev->dev, + "Multiple IOB BA RBM poisoned write error\n"); + if (reg & WDATA_CORRUPT_MASK) + dev_err(edac_dev->dev, "IOB BA write error\n"); + if (reg & M_WDATA_CORRUPT_MASK) + dev_err(edac_dev->dev, "Multiple IOB BA write error\n"); + if (reg & TRANS_CORRUPT_MASK) + dev_err(edac_dev->dev, "IOB BA transaction error\n"); + if (reg & M_TRANS_CORRUPT_MASK) + dev_err(edac_dev->dev, "Multiple IOB BA transaction error\n"); + if (reg & RIDRAM_CORRUPT_MASK) + dev_err(edac_dev->dev, + "IOB BA RDIDRAM read transaction ID error\n"); + if (reg & M_RIDRAM_CORRUPT_MASK) + dev_err(edac_dev->dev, + "Multiple IOB BA RDIDRAM read transaction ID error\n"); + if (reg & WIDRAM_CORRUPT_MASK) + dev_err(edac_dev->dev, + "IOB BA RDIDRAM write transaction ID error\n"); + if (reg & M_WIDRAM_CORRUPT_MASK) + dev_err(edac_dev->dev, + "Multiple IOB BA RDIDRAM write transaction ID error\n"); + if (reg & ILLEGAL_ACCESS_MASK) + dev_err(edac_dev->dev, + "IOB BA XGIC/RB illegal access error\n"); + if (reg & M_ILLEGAL_ACCESS_MASK) + dev_err(edac_dev->dev, + "Multiple IOB BA XGIC/RB illegal access error\n"); + + err_addr_lo = readl(ctx->dev_csr + IOBBATRANSERRREQINFOL); + err_addr_hi = readl(ctx->dev_csr + IOBBATRANSERRREQINFOH); + dev_err(edac_dev->dev, "IOB BA %s access at 0x%02X.%08X (0x%08X)\n", + REQTYPE_F2_RD(err_addr_hi) ? "read" : "write", + ERRADDRH_F2_RD(err_addr_hi), err_addr_lo, err_addr_hi); + if (reg & WRERR_RESP_MASK) + dev_err(edac_dev->dev, "IOB BA requestor ID 0x%08X\n", + readl(ctx->dev_csr + IOBBATRANSERRCSWREQID)); + writel(reg, ctx->dev_csr + IOBBATRANSERRINTSTS); +} + +static void xgene_edac_pa_report(struct edac_device_ctl_info *edac_dev) +{ + struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; + u32 err_addr_lo; + u32 err_addr_hi; + u32 reg; + + /* IOB Processing agent transaction error interrupt */ + reg = readl(ctx->dev_csr + IOBPATRANSERRINTSTS); + if (reg) { + dev_err(edac_dev->dev, + "IOB procesing agent (PA) transaction error\n"); + if (reg & IOBPA_RDATA_CORRUPT_MASK) + dev_err(edac_dev->dev, "IOB PA read data RAM error\n"); + if (reg & IOBPA_M_RDATA_CORRUPT_MASK) + dev_err(edac_dev->dev, + "Mutilple IOB PA read data RAM error\n"); + if (reg & IOBPA_WDATA_CORRUPT_MASK) + dev_err(edac_dev->dev, + "IOB PA write data RAM error\n"); + if (reg & IOBPA_M_WDATA_CORRUPT_MASK) + dev_err(edac_dev->dev, + "Mutilple IOB PA write data RAM error\n"); + if (reg & IOBPA_TRANS_CORRUPT_MASK) + dev_err(edac_dev->dev, "IOB PA transaction error\n"); + if (reg & IOBPA_M_TRANS_CORRUPT_MASK) + dev_err(edac_dev->dev, + "Mutilple IOB PA transaction error\n"); + if (reg & IOBPA_REQIDRAM_CORRUPT_MASK) + dev_err(edac_dev->dev, + "IOB PA transaction ID RAM error\n"); + if (reg & IOBPA_M_REQIDRAM_CORRUPT_MASK) + dev_err(edac_dev->dev, + "Multiple IOB PA transaction ID RAM error\n"); + writel(reg, ctx->dev_csr + IOBPATRANSERRINTSTS); + } + + /* IOB AXI0 Error */ + reg = readl(ctx->dev_csr + IOBAXIS0TRANSERRINTSTS); + if (reg) { + err_addr_lo = readl(ctx->dev_csr + IOBAXIS0TRANSERRREQINFOL); + err_addr_hi = readl(ctx->dev_csr + IOBAXIS0TRANSERRREQINFOH); + dev_err(edac_dev->dev, + "%sAXI slave 0 illegal %s access @ 0x%02X.%08X (0x%08X)\n", + reg & IOBAXIS0_M_ILLEGAL_ACCESS_MASK ? "Multiple " : "", + REQTYPE_RD(err_addr_hi) ? "read" : "write", + ERRADDRH_RD(err_addr_hi), err_addr_lo, err_addr_hi); + writel(reg, ctx->dev_csr + IOBAXIS0TRANSERRINTSTS); + } + + /* IOB AXI1 Error */ + reg = readl(ctx->dev_csr + IOBAXIS1TRANSERRINTSTS); + if (reg) { + err_addr_lo = readl(ctx->dev_csr + IOBAXIS1TRANSERRREQINFOL); + err_addr_hi = readl(ctx->dev_csr + IOBAXIS1TRANSERRREQINFOH); + dev_err(edac_dev->dev, + "%sAXI slave 1 illegal %s access @ 0x%02X.%08X (0x%08X)\n", + reg & IOBAXIS0_M_ILLEGAL_ACCESS_MASK ? "Multiple " : "", + REQTYPE_RD(err_addr_hi) ? "read" : "write", + ERRADDRH_RD(err_addr_hi), err_addr_lo, err_addr_hi); + writel(reg, ctx->dev_csr + IOBAXIS1TRANSERRINTSTS); + } +} + +static void xgene_edac_soc_check(struct edac_device_ctl_info *edac_dev) +{ + struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; + static const char * const mem_err_ip[] = { + "10GbE0", + "10GbE1", + "Security", + "SATA45", + "SATA23/ETH23", + "SATA01/ETH01", + "USB1", + "USB0", + "QML", + "QM0", + "QM1 (XGbE01)", + "PCIE4", + "PCIE3", + "PCIE2", + "PCIE1", + "PCIE0", + "CTX Manager", + "OCM", + "1GbE", + "CLE", + "AHBC", + "PktDMA", + "GFC", + "MSLIM", + "10GbE2", + "10GbE3", + "QM2 (XGbE23)", + "IOB", + "unknown", + "unknown", + "unknown", + "unknown", + }; + u32 pcp_hp_stat; + u32 pcp_lp_stat; + u32 reg; + int i; + + pcp_hp_stat = readl(ctx->pcp_csr + PCPHPERRINTSTS); + pcp_lp_stat = readl(ctx->pcp_csr + PCPLPERRINTSTS); + reg = readl(ctx->pcp_csr + MEMERRINTSTS); + if (!((pcp_hp_stat & (IOB_PA_ERR_MASK | IOB_BA_ERR_MASK | + IOB_XGIC_ERR_MASK | IOB_RB_ERR_MASK)) || + (pcp_lp_stat & CSW_SWITCH_TRACE_ERR_MASK) || reg)) + return; + + if (pcp_hp_stat & IOB_XGIC_ERR_MASK) + xgene_edac_iob_gic_report(edac_dev); + + if (pcp_hp_stat & (IOB_RB_ERR_MASK | IOB_BA_ERR_MASK)) + xgene_edac_rb_report(edac_dev); + + if (pcp_hp_stat & IOB_PA_ERR_MASK) + xgene_edac_pa_report(edac_dev); + + if (pcp_lp_stat & CSW_SWITCH_TRACE_ERR_MASK) { + dev_info(edac_dev->dev, + "CSW switch trace correctable memory parity error\n"); + edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); + } + + for (i = 0; i < 31; i++) { + if (reg & (1 << i)) { + dev_err(edac_dev->dev, "%s memory parity error\n", + mem_err_ip[i]); + edac_device_handle_ue(edac_dev, 0, 0, + edac_dev->ctl_name); + } + } +} + +static irqreturn_t xgene_edac_soc_isr(int irq, void *dev_id) +{ + struct edac_device_ctl_info *edac_dev = dev_id; + struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; + u32 pcp_hp_stat; + u32 pcp_lp_stat; + u32 reg; + + pcp_hp_stat = readl(ctx->pcp_csr + PCPHPERRINTSTS); + pcp_lp_stat = readl(ctx->pcp_csr + PCPLPERRINTSTS); + reg = readl(ctx->pcp_csr + MEMERRINTSTS); + if (!((pcp_hp_stat & (IOB_PA_ERR_MASK | IOB_BA_ERR_MASK | + IOB_XGIC_ERR_MASK | IOB_RB_ERR_MASK)) || + (pcp_lp_stat & CSW_SWITCH_TRACE_ERR_MASK) || reg)) + return IRQ_NONE; + + xgene_edac_soc_check(edac_dev); + + return IRQ_HANDLED; +} + +static void xgene_edac_soc_hw_ctl(struct edac_device_ctl_info *edac_dev, + bool enable) +{ + struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; + u32 val; + + /* Enable SoC IP error interrupt */ + if (edac_dev->op_state == OP_RUNNING_INTERRUPT) { + mutex_lock(&xgene_edac_lock); + + val = readl(ctx->pcp_csr + PCPHPERRINTMSK); + if (enable) + val &= ~(IOB_PA_ERR_MASK | IOB_BA_ERR_MASK | + IOB_XGIC_ERR_MASK | IOB_RB_ERR_MASK); + else + val |= IOB_PA_ERR_MASK | IOB_BA_ERR_MASK | + IOB_XGIC_ERR_MASK | IOB_RB_ERR_MASK; + writel(val, ctx->pcp_csr + PCPHPERRINTMSK); + val = readl(ctx->pcp_csr + PCPLPERRINTMSK); + if (enable) + val &= ~CSW_SWITCH_TRACE_ERR_MASK; + else + val |= CSW_SWITCH_TRACE_ERR_MASK; + writel(val, ctx->pcp_csr + PCPLPERRINTMSK); + + mutex_unlock(&xgene_edac_lock); + + writel(enable ? 0x0 : 0xFFFFFFFF, + ctx->dev_csr + IOBAXIS0TRANSERRINTMSK); + writel(enable ? 0x0 : 0xFFFFFFFF, + ctx->dev_csr + IOBAXIS1TRANSERRINTMSK); + writel(enable ? 0x0 : 0xFFFFFFFF, + ctx->dev_csr + XGICTRANSERRINTMSK); + + writel(enable ? 0x0 : 0xFFFFFFFF, ctx->pcp_csr + MEMERRINTMSK); + } +} + +static int xgene_edac_soc_probe(struct platform_device *pdev) +{ + struct edac_device_ctl_info *edac_dev; + struct xgene_edac_dev_ctx *ctx; + struct resource *res; + int rc = 0; + + if (!devres_open_group(&pdev->dev, xgene_edac_soc_probe, GFP_KERNEL)) + return -ENOMEM; + + edac_dev = edac_device_alloc_ctl_info(sizeof(*ctx), + "SOC", 1, "SOC", 1, 2, NULL, 0, + edac_device_alloc_index()); + if (!edac_dev) { + rc = -ENOMEM; + goto err; + } + + ctx = edac_dev->pvt_info; + ctx->name = "xgene_soc_err"; + edac_dev->dev = &pdev->dev; + dev_set_drvdata(edac_dev->dev, edac_dev); + edac_dev->ctl_name = ctx->name; + edac_dev->dev_name = ctx->name; + edac_dev->mod_name = EDAC_MOD_STR; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "no PCP resource address\n"); + rc = -EINVAL; + goto err1; + } + ctx->pcp_csr = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (IS_ERR(ctx->pcp_csr)) { + dev_err(&pdev->dev, "no PCP resource address\n"); + rc = PTR_ERR(ctx->pcp_csr); + goto err1; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + ctx->dev_csr = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(ctx->dev_csr)) { + dev_err(&pdev->dev, "no SoC resource address\n"); + rc = PTR_ERR(ctx->dev_csr); + goto err1; + } + + if (edac_op_state == EDAC_OPSTATE_POLL) + edac_dev->edac_check = xgene_edac_soc_check; + + rc = edac_device_add_device(edac_dev); + if (rc > 0) { + dev_err(&pdev->dev, "failed edac_device_add_device()\n"); + rc = -ENOMEM; + goto err1; + } + + if (edac_op_state == EDAC_OPSTATE_INT) { + int irq; + int i; + + /* + * Register for SoC un-correctable and correctable errors + */ + for (i = 0; i < 3; i++) { + irq = platform_get_irq(pdev, i); + if (irq < 0) { + dev_err(&pdev->dev, "No IRQ resource\n"); + rc = -EINVAL; + goto err2; + } + rc = devm_request_irq(&pdev->dev, irq, + xgene_edac_soc_isr, IRQF_SHARED, + dev_name(&pdev->dev), edac_dev); + if (rc) { + dev_err(&pdev->dev, + "Could not request IRQ %d\n", + irq); + goto err2; + } + } + + edac_dev->op_state = OP_RUNNING_INTERRUPT; + } + + xgene_edac_soc_hw_ctl(edac_dev, 1); + + devres_remove_group(&pdev->dev, xgene_edac_soc_probe); + + dev_info(&pdev->dev, "X-Gene EDAC SoC registered\n"); + return 0; + +err2: + edac_device_del_device(&pdev->dev); +err1: + edac_device_free_ctl_info(edac_dev); +err: + devres_release_group(&pdev->dev, xgene_edac_soc_probe); + return rc; +} + +static int xgene_edac_soc_remove(struct platform_device *pdev) +{ + struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&pdev->dev); + + xgene_edac_soc_hw_ctl(edac_dev, 0); + edac_device_del_device(&pdev->dev); + edac_device_free_ctl_info(edac_dev); + return 0; +} + +#ifdef CONFIG_OF +static struct of_device_id xgene_edac_soc_of_match[] = { + { .compatible = "apm,xgene-edac-soc" }, + {}, +}; +MODULE_DEVICE_TABLE(of, xgene_edac_soc_of_match); +#endif + +static struct platform_driver xgene_edac_soc_driver = { + .probe = xgene_edac_soc_probe, + .remove = xgene_edac_soc_remove, + .driver = { + .name = "xgene-edac-soc", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(xgene_edac_soc_of_match), + }, +}; + +static int __init xgene_edac_init(void) +{ + int rc; + + /* make sure error reporting method is sane */ + switch (edac_op_state) { + case EDAC_OPSTATE_POLL: + case EDAC_OPSTATE_INT: + break; + default: + edac_op_state = EDAC_OPSTATE_INT; + break; + } + + rc = platform_driver_register(&xgene_edac_mc_driver); + if (rc) { + pr_err(EDAC_MOD_STR "MCU fails to register\n"); + goto reg_mc_failed; + } + rc = platform_driver_register(&xgene_edac_pmd_driver); + if (rc) { + pr_err(EDAC_MOD_STR "PMD fails to register\n"); + goto reg_pmd_failed; + } + rc = platform_driver_register(&xgene_edac_l3_driver); + if (rc) { + pr_warn(EDAC_MOD_STR "L3 fails to register\n"); + goto reg_l3_failed; + } + rc = platform_driver_register(&xgene_edac_soc_driver); + if (rc) { + pr_warn(EDAC_MOD_STR "SoC fails to register\n"); + goto reg_soc_failed; + } + + return 0; + +reg_soc_failed: + platform_driver_unregister(&xgene_edac_l3_driver); + +reg_l3_failed: + platform_driver_unregister(&xgene_edac_pmd_driver); + +reg_pmd_failed: + platform_driver_unregister(&xgene_edac_mc_driver); + +reg_mc_failed: + return rc; +} +module_init(xgene_edac_init); + +static void __exit xgene_edac_exit(void) +{ + platform_driver_unregister(&xgene_edac_soc_driver); + platform_driver_unregister(&xgene_edac_l3_driver); + platform_driver_unregister(&xgene_edac_pmd_driver); + platform_driver_unregister(&xgene_edac_mc_driver); +} +module_exit(xgene_edac_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Feng Kan <fkan-qTEPVZfXA3Y@public.gmane.org>"); +MODULE_DESCRIPTION("APM X-Gene EDAC driver"); +module_param(edac_op_state, int, 0444); +MODULE_PARM_DESC(edac_op_state, + "EDAC Error Reporting state: 0=Poll, 2=Interrupt"); -- 1.5.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 58+ messages in thread
[parent not found: <1400894467-1585-4-git-send-email-lho-qTEPVZfXA3Y@public.gmane.org>]
* [PATCH v2 4/4] arm64: Add APM X-Gene SoC EDAC DTS entries [not found] ` <1400894467-1585-4-git-send-email-lho-qTEPVZfXA3Y@public.gmane.org> @ 2014-05-24 1:21 ` Loc Ho 2014-05-30 10:29 ` [PATCH v2 3/4] edac: Add APM X-Gene SoC EDAC driver Borislav Petkov 1 sibling, 0 replies; 58+ messages in thread From: Loc Ho @ 2014-05-24 1:21 UTC (permalink / raw) To: dougthompson-aS9lmoZGLiVWk0Htik3J/w, bp-Gina5bIWoIWzQB+pC5nmwQ, m.chehab-Sze3O3UU22JBDgjK7y7TUQ Cc: linux-edac-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, jcm-H+wXaHxf7aLQT0dZR+AlfA, patches-qTEPVZfXA3Y, Loc Ho, Feng Kan This patch adds APM X-Gene SoC EDAC DTS entries. Signed-off-by: Feng Kan <fkan-qTEPVZfXA3Y@public.gmane.org> Signed-off-by: Loc Ho <lho-qTEPVZfXA3Y@public.gmane.org> --- arch/arm64/boot/dts/apm-storm.dtsi | 89 ++++++++++++++++++++++++++++++++++++ 1 files changed, 89 insertions(+), 0 deletions(-) diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi index 93f4b2d..aff6821 100644 --- a/arch/arm64/boot/dts/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm-storm.dtsi @@ -269,6 +269,95 @@ interrupts = <0x0 0x4c 0x4>; }; + edacmc0: edacmc0@7e800000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x78800000 0x0 0x1000>, + <0x0 0x7e200000 0x0 0x1000>, + <0x0 0x7e700000 0x0 0x1000>, + <0x0 0x7e720000 0x0 0x1000>, + <0x0 0x7e800000 0x0 0x1000>; + interrupts = <0x0 0x20 0x4>; + }; + + edacmc1: edacmc1@7e840000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x78800000 0x0 0x1000>, + <0x0 0x7e200000 0x0 0x1000>, + <0x0 0x7e700000 0x0 0x1000>, + <0x0 0x7e720000 0x0 0x1000>, + <0x0 0x7e840000 0x0 0x1000>; + interrupts = <0x0 0x20 0x4>; + }; + + edacmc2: edacmc2@7e880000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x78800000 0x0 0x1000>, + <0x0 0x7e200000 0x0 0x1000>, + <0x0 0x7e700000 0x0 0x1000>, + <0x0 0x7e720000 0x0 0x1000>, + <0x0 0x7e880000 0x0 0x1000>; + interrupts = <0x0 0x20 0x4>; + }; + + edacmc3: edacmc3@7e8c0000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x78800000 0x0 0x1000>, + <0x0 0x7e200000 0x0 0x1000>, + <0x0 0x7e700000 0x0 0x1000>, + <0x0 0x7e720000 0x0 0x1000>, + <0x0 0x7e8c0000 0x0 0x1000>; + interrupts = <0x0 0x20 0x4>; + }; + + edacpmd0: edacpmd0@7c000000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x78800000 0x0 0x1000>, + <0x0 0x7c000000 0x0 0x200000>; + interrupts = <0x0 0x20 0x4>, + <0x0 0x21 0x4>; + }; + + edacpmd1: edacpmd1@7c200000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x78800000 0x0 0x1000>, + <0x0 0x7c200000 0x0 0x200000>; + interrupts = <0x0 0x20 0x4>, + <0x0 0x21 0x4>; + }; + + edacpmd2: edacpmd2@7c400000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x78800000 0x0 0x1000>, + <0x0 0x7c400000 0x0 0x200000>; + interrupts = <0x0 0x20 0x4>, + <0x0 0x21 0x4>; + }; + + edacpmd3: edacpmd3@7c600000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x78800000 0x0 0x1000>, + <0x0 0x7c600000 0x0 0x200000>; + interrupts = <0x0 0x20 0x4>, + <0x0 0x21 0x4>; + }; + + edacl3: edacl3@7e600000 { + compatible = "apm,xgene-edac-l3"; + reg = <0x0 0x78800000 0x0 0x1000>, + <0x0 0x7e600000 0x0 0x1000>; + interrupts = <0x0 0x20 0x4>, + <0x0 0x21 0x4>; + }; + + edacsoc: edacsoc@7e930000 { + compatible = "apm,xgene-edac-soc"; + reg = <0x0 0x78800000 0x0 0x1000>, + <0x0 0x7e930000 0x0 0x1000>; + interrupts = <0x0 0x20 0x4>, + <0x0 0x21 0x4>, + <0x0 0x27 0x4>; + }; + phy1: phy@1f21a000 { compatible = "apm,xgene-phy"; reg = <0x0 0x1f21a000 0x0 0x100>; -- 1.5.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 58+ messages in thread
* Re: [PATCH v2 3/4] edac: Add APM X-Gene SoC EDAC driver [not found] ` <1400894467-1585-4-git-send-email-lho-qTEPVZfXA3Y@public.gmane.org> 2014-05-24 1:21 ` [PATCH v2 4/4] arm64: Add APM X-Gene SoC EDAC DTS entries Loc Ho @ 2014-05-30 10:29 ` Borislav Petkov 1 sibling, 0 replies; 58+ messages in thread From: Borislav Petkov @ 2014-05-30 10:29 UTC (permalink / raw) To: Loc Ho Cc: dougthompson-aS9lmoZGLiVWk0Htik3J/w, m.chehab-Sze3O3UU22JBDgjK7y7TUQ, linux-edac-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, jcm-H+wXaHxf7aLQT0dZR+AlfA, patches-qTEPVZfXA3Y, Feng Kan On Fri, May 23, 2014 at 07:21:06PM -0600, Loc Ho wrote: > +static ssize_t xgene_edac_mc_inject_ctrl_store(struct device *dev, > + struct device_attribute *mattr, > + const char *data, size_t count) > +{ > + struct mem_ctl_info *mci = to_mci(dev); > + struct xgene_edac_mc_ctx *ctx = mci->pvt_info; > + u32 val; > + int i; > + > + if (isdigit(*data)) { > + if (kstrtou32(data, 0, &val)) > + return 0; > + for (i = 0; i < MCU_MAX_RANK; i++) { > + writel(val, > + ctx->mcu_csr + MCUESRRA0 + i * MCU_RANK_STRIDE); > + } > + return count; > + } > + return 0; > +} > + > +DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR, > + xgene_edac_mc_inject_ctrl_show, xgene_edac_mc_inject_ctrl_store); > + > +static int xgene_edac_mc_create_sysfs_attributes(struct mem_ctl_info *mci) > +{ > +#if defined(CONFIG_EDAC_DEBUG) Why #if defined()? #ifdef CONFIG_EDAC_DEBUG is normally enough. But more importantly, why not wrap around the whole injection code with #ifdef CONFIG_EDAC_DEBUG instead of only the parts that create the sysfs nodes? Also, this is for debugging only so it shouldn't be in sysfs but debugfs. And yes, there are other edac drivers which use sysfs for injection but this should be fixed too and I'll be looking into that too soon. IOW, here's a good example how it should be done: http://lkml.kernel.org/r/1399330337-16748-4-git-send-email-tthayer-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org ... > +static int xgene_edac_mc_probe(struct platform_device *pdev) > +{ > + struct mem_ctl_info *mci; > + struct edac_mc_layer layers[2]; > + struct xgene_edac_mc_ctx tmp_ctx; > + struct xgene_edac_mc_ctx *ctx; > + struct resource *res; > + int rc = 0; ... > + ctx = mci->pvt_info; > + *ctx = tmp_ctx; /* Copy over resource value */ > + ctx->name = "xgene_edac_mc_err"; > + mci->pdev = &pdev->dev; > + dev_set_drvdata(mci->pdev, mci); > + mci->ctl_name = ctx->name; > + mci->dev_name = ctx->name; > + > + mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 | MEM_FLAG_RDDR3 | > + MEM_FLAG_DDR | MEM_FLAG_DDR2 | MEM_FLAG_DDR3; > + mci->edac_ctl_cap = EDAC_FLAG_SECDED; > + mci->edac_cap = EDAC_FLAG_SECDED; > + mci->mod_name = EDAC_MOD_STR; > + mci->mod_ver = "0.1"; > + mci->ctl_page_to_phys = NULL; > + mci->scrub_cap = SCRUB_FLAG_HW_SRC; > + mci->scrub_mode = SCRUB_HW_SRC; > + > + if (edac_op_state == EDAC_OPSTATE_POLL) > + mci->edac_check = xgene_edac_mc_check; > + > + if (edac_mc_add_mc(mci)) { > + dev_err(&pdev->dev, "failed add edac mc\n"); You forgot to fix those: "failed add edac mc\n" --> "edac_mc_add_mc failed\n" > + rc = -EINVAL; > + goto err_free; > + } > + > + if (xgene_edac_mc_create_sysfs_attributes(mci)) { > + dev_err(&pdev->dev, "failed create edac sysfs\n"); "failed create edac sysfs\n" --> "Failure creating sysfs injection node\n" Also, please go over the rest of the driver and correct similar error messages into proper English. > + goto err_del; > + } > + > + if (edac_op_state == EDAC_OPSTATE_INT) { > + int irq = platform_get_irq(pdev, 0); > + if (irq < 0) { > + dev_err(&pdev->dev, "No IRQ resource\n"); > + rc = -EINVAL; > + goto err_sysfs; > + } > + rc = devm_request_irq(&pdev->dev, irq, > + xgene_edac_mc_isr, IRQF_SHARED, > + dev_name(&pdev->dev), mci); > + if (rc) { > + dev_err(&pdev->dev, "Could not request IRQ\n"); > + goto err_sysfs; > + } > + } > + > + xgene_edac_mc_irq_ctl(mci, 1); Forgot this one too: xgene_edac_mc_irq_ctl(mci, 1); --> xgene_edac_mc_irq_ctl(mci, true); > + > + devres_remove_group(&pdev->dev, xgene_edac_mc_probe); > + > + dev_info(&pdev->dev, "X-Gene EDAC MC registered\n"); > + return 0; > + > +err_sysfs: > + xgene_edac_mc_remove_sysfs_attributes(mci); > +err_del: > + edac_mc_del_mc(&pdev->dev); > +err_free: > + edac_mc_free(mci); > +err_group: > + devres_release_group(&pdev->dev, xgene_edac_mc_probe); > + return rc; > +} > + > +static int xgene_edac_mc_remove(struct platform_device *pdev) > +{ > + struct mem_ctl_info *mci = dev_get_drvdata(&pdev->dev); > + > + xgene_edac_mc_irq_ctl(mci, 0); xgene_edac_mc_irq_ctl(mci, 0); --> xgene_edac_mc_irq_ctl(mci, false); > + xgene_edac_mc_remove_sysfs_attributes(mci); > + edac_mc_del_mc(&pdev->dev); > + edac_mc_free(mci); > + return 0; > +} > + > +#ifdef CONFIG_OF > +static struct of_device_id xgene_edac_mc_of_match[] = { > + { .compatible = "apm,xgene-edac-mc" }, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, xgene_edac_of_match); > +#endif > + > +static struct platform_driver xgene_edac_mc_driver = { > + .probe = xgene_edac_mc_probe, > + .remove = xgene_edac_mc_remove, > + .driver = { > + .name = "xgene-edac-mc", > + .owner = THIS_MODULE, > + .of_match_table = of_match_ptr(xgene_edac_mc_of_match), > + }, > +}; > + > +/* CPU L1/L2 error device */ > +#define MAX_CPU_PER_PMD 2 > +#define CPU_CSR_STRIDE 0x00100000 > +#define CPU_L2C_PAGE 0x000D0000 > +#define CPU_MEMERR_L2C_PAGE 0x000E0000 > +#define CPU_MEMERR_CPU_PAGE 0x000F0000 > + > +#define MEMERR_CPU_ICFECR_PAGE_OFFSET 0x0000 > +#define MEMERR_CPU_ICFESR_PAGE_OFFSET 0x0004 > +#define MEMERR_CPU_ICFESR_ERRWAY_RD(src) (((src) & 0xFF000000) >> 24) > +#define MEMERR_CPU_ICFESR_ERRINDEX_RD(src) (((src) & 0x003F0000) >> 16) > +#define MEMERR_CPU_ICFESR_ERRINFO_RD(src) (((src) & 0x0000FF00) >> 8) > +#define MEMERR_CPU_ICFESR_ERRTYPE_RD(src) (((src) & 0x00000070) >> 4) > +#define MEMERR_CPU_ICFESR_MULTCERR_MASK BIT(2) > +#define MEMERR_CPU_ICFESR_CERR_MASK BIT(0) > +#define MEMERR_CPU_LSUESR_PAGE_OFFSET 0x000c > +#define MEMERR_CPU_LSUESR_ERRWAY_RD(src) (((src) & 0xFF000000) >> 24) > +#define MEMERR_CPU_LSUESR_ERRINDEX_RD(src) (((src) & 0x003F0000) >> 16) > +#define MEMERR_CPU_LSUESR_ERRINFO_RD(src) (((src) & 0x0000FF00) >> 8) > +#define MEMERR_CPU_LSUESR_ERRTYPE_RD(src) (((src) & 0x00000070) >> 4) > +#define MEMERR_CPU_LSUESR_MULTCERR_MASK BIT(2) > +#define MEMERR_CPU_LSUESR_CERR_MASK BIT(0) > +#define MEMERR_CPU_LSUECR_PAGE_OFFSET 0x0008 > +#define MEMERR_CPU_MMUECR_PAGE_OFFSET 0x0010 > +#define MEMERR_CPU_MMUESR_PAGE_OFFSET 0x0014 > +#define MEMERR_CPU_ICFESRA_PAGE_OFFSET 0x0804 > +#define MEMERR_CPU_LSUESRA_PAGE_OFFSET 0x080c > +#define MEMERR_CPU_MMUESRA_PAGE_OFFSET 0x0814 > + > +#define MEMERR_L2C_L2ECR_PAGE_OFFSET 0x0000 > +#define MEMERR_L2C_L2ESR_PAGE_OFFSET 0x0004 > +#define MEMERR_L2C_L2ESR_ERRSYN_RD(src) (((src) & 0xFF000000) >> 24) > +#define MEMERR_L2C_L2ESR_ERRWAY_RD(src) (((src) & 0x00FC0000) >> 18) > +#define MEMERR_L2C_L2ESR_ERRCPU_RD(src) (((src) & 0x00020000) >> 17) > +#define MEMERR_L2C_L2ESR_ERRGROUP_RD(src) (((src) & 0x0000E000) >> 13) > +#define MEMERR_L2C_L2ESR_ERRACTION_RD(src) (((src) & 0x00001C00) >> 10) > +#define MEMERR_L2C_L2ESR_ERRTYPE_RD(src) (((src) & 0x00000300) >> 8) > +#define MEMERR_L2C_L2ESR_MULTUCERR_MASK BIT(3) > +#define MEMERR_L2C_L2ESR_MULTICERR_MASK BIT(2) > +#define MEMERR_L2C_L2ESR_UCERR_MASK BIT(1) > +#define MEMERR_L2C_L2ESR_ERR_MASK BIT(0) > +#define MEMERR_L2C_L2EALR_PAGE_OFFSET 0x0008 > +#define CPUX_L2C_L2RTOCR_PAGE_OFFSET 0x0010 > +#define MEMERR_L2C_L2EAHR_PAGE_OFFSET 0x000c > +#define CPUX_L2C_L2RTOSR_PAGE_OFFSET 0x0014 > +#define CPUX_L2C_L2RTOALR_PAGE_OFFSET 0x0018 > +#define CPUX_L2C_L2RTOAHR_PAGE_OFFSET 0x001c > +#define MEMERR_L2C_L2ESRA_PAGE_OFFSET 0x0804 > + > +/* > + * Processor Module Domain (PMD) context - Context for an pair of processsors. s/ an / a / > + * Each PMD consists of 2 CPU's and an shared L2 cache. Each CPU consists of s/CPU's/CPUs/; s/ an / a / > + * its own L1 cache. > + */ > +struct xgene_edac_pmd_ctx { > + struct device *dev; > + char *name; > + void __iomem *pcp_csr; /* PCP CSR for reading error interrupt reg */ > + void __iomem *pmd_csr; /* PMD CSR for reading L1/L2 error reg */ > + int pmd; /* Identify the register in pcp_csr */ > +}; ... > +static struct edac_dev_sysfs_attribute xgene_edac_pmd_sysfs_attributes[] = { > + { .attr = { > + .name = "l1_inject_ctrl", > + .mode = (S_IRUGO | S_IWUSR) > + }, > + .show = xgene_edac_pmd_l1_inject_ctrl_show, > + .store = xgene_edac_pmd_l1_inject_ctrl_store }, > + { .attr = { > + .name = "l2_inject_ctrl", > + .mode = (S_IRUGO | S_IWUSR) > + }, > + .show = xgene_edac_pmd_l2_inject_ctrl_show, > + .store = xgene_edac_pmd_l2_inject_ctrl_store }, > + > + /* End of list */ > + { .attr = {.name = NULL } } > +}; > +#endif Yep, this is exactly what I meant with CONFIG_EDAC_DEBUG. This looks good except it should be in debugfs and not sysfs. > + > +static int xgene_edac_pmd_probe(struct platform_device *pdev) > +{ > + struct edac_device_ctl_info *edac_dev; > + struct xgene_edac_pmd_ctx *ctx; > + char edac_name[10]; > + struct resource *res; > + int pmd; > + int rc = 0; > + > + if (!devres_open_group(&pdev->dev, xgene_edac_pmd_probe, GFP_KERNEL)) > + return -ENOMEM; > + > + /* Find the PMD number from its address */ > + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); > + if (!res || resource_size(res) <= 0) { > + rc = -ENODEV; > + goto err_group; > + } > + pmd = ((res->start >> 20) & 0x1E) >> 1; > + > + sprintf(edac_name, "l2c%d", pmd); > + edac_dev = edac_device_alloc_ctl_info(sizeof(*ctx), > + edac_name, 1, "l2c", 1, 2, NULL, > + 0, edac_device_alloc_index()); > + if (!edac_dev) { > + rc = -ENOMEM; > + goto err_group; > + } > + > + ctx = edac_dev->pvt_info; > + ctx->name = "xgene_pmd_err"; > + ctx->pmd = pmd; > + edac_dev->dev = &pdev->dev; > + dev_set_drvdata(edac_dev->dev, edac_dev); > + edac_dev->ctl_name = ctx->name; > + edac_dev->dev_name = ctx->name; > + edac_dev->mod_name = EDAC_MOD_STR; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!res) { > + dev_err(&pdev->dev, "no PCP resource address\n"); > + rc = -EINVAL; > + goto err_free; > + } > + ctx->pcp_csr = devm_ioremap(&pdev->dev, res->start, resource_size(res)); > + if (IS_ERR(ctx->pcp_csr)) { > + dev_err(&pdev->dev, "no PCP resource address\n"); > + rc = PTR_ERR(ctx->pcp_csr); > + goto err_free; > + } > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); > + if (!res) { > + dev_err(&pdev->dev, "no PMD resource address\n"); > + rc = -EINVAL; > + goto err_free; > + } > + ctx->pmd_csr = devm_ioremap(&pdev->dev, res->start, resource_size(res)); > + if (IS_ERR(ctx->pmd_csr)) { > + dev_err(&pdev->dev, "no PMD resource address\n"); > + rc = PTR_ERR(ctx->pmd_csr); > + goto err_free; > + } > + > + if (edac_op_state == EDAC_OPSTATE_POLL) > + edac_dev->edac_check = xgene_edac_pmd_check; > + ... > +static int __init xgene_edac_init(void) > +{ > + int rc; > + > + /* make sure error reporting method is sane */ > + switch (edac_op_state) { > + case EDAC_OPSTATE_POLL: > + case EDAC_OPSTATE_INT: > + break; > + default: > + edac_op_state = EDAC_OPSTATE_INT; > + break; > + } > + > + rc = platform_driver_register(&xgene_edac_mc_driver); > + if (rc) { > + pr_err(EDAC_MOD_STR "MCU fails to register\n"); > + goto reg_mc_failed; > + } > + rc = platform_driver_register(&xgene_edac_pmd_driver); > + if (rc) { > + pr_err(EDAC_MOD_STR "PMD fails to register\n"); > + goto reg_pmd_failed; > + } > + rc = platform_driver_register(&xgene_edac_l3_driver); > + if (rc) { > + pr_warn(EDAC_MOD_STR "L3 fails to register\n"); > + goto reg_l3_failed; > + } > + rc = platform_driver_register(&xgene_edac_soc_driver); > + if (rc) { > + pr_warn(EDAC_MOD_STR "SoC fails to register\n"); Those pr_warn can all be edac_printk. Ok, overall it is getting better, just needs a bit more work. Also, the devicetree stuff would need an ack before it goes through the edac tree. Thanks. -- Regards/Gruss, Boris. Sent from a fat crate under my desk. Formatting is fine. -- -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown),
@ 2018-06-23 21:08 David Lechner
0 siblings, 0 replies; 58+ messages in thread
From: David Lechner @ 2018-06-23 21:08 UTC (permalink / raw)
To: linux-remoteproc, devicetree, linux-omap, linux-arm-kernel
Cc: David Lechner, Ohad Ben-Cohen, Bjorn Andersson, Rob Herring,
Mark Rutland, Benoît Cousson, Tony Lindgren, Sekhar Nori,
Kevin Hilman, linux-kernel
Date: Sat, 23 Jun 2018 15:43:59 -0500
Subject: [PATCH 0/8] New remoteproc driver for TI PRU
This series adds a new remoteproc driver for the TI Programmable Runtime Unit
(PRU) that is present in some TI Sitara processors. This code has been tested
working on AM1808 (LEGO MINDSTORMS EV3) and AM3358 (BeagleBone Green).
There are a couple of quirks that had to be worked around in order to get this
working. The PRU units have multiple memory maps. Notably, both the instruction
RAM and data RAM are at address 0x0. This caused the da_to_va callback to not
work because the same address could refer to two different locations. To work
around this, the first two patches add a "map" parameter to the da_to_va
callbacks so that we have an extra bit of information to make this distinction.
Also, on AM38xx we have to use pdata for accessing a reset since there is not
a reset controller. There are several other devices doing this, so the seems
the best way for now.
For anyone else who would like to test, I used the rpmsg-client-sample driver.
Just enable it in your kernel config. Then grab the appropriate firmware[1]
and put in in /lib/firmware/. Use sysfs to start and stop the PRU:
echo start > /sys/class/remoteproc<n>/state
echo stop > /sys/class/remoteproc<n>/state
[1]: firmware downloads:
AM18XX: https://github.com/ev3dev/ev3dev-pru-firmware/releases/download/mainline-kernel-testing/AM18xx-PRU-rpmsg-client-sample.zip
AM335X: https://github.com/ev3dev/ev3dev-pru-firmware/releases/download/mainline-kernel-testing/AM335x-PRU-rpmsg-client-sample.zip
David Lechner (8):
remoteproc: add map parameter to da_to_va
remoteproc: add page lookup for TI PRU to ELF loader
ARM: OMAP2+: add pdata quirks for PRUSS reset
dt-bindings: add bindings for TI PRU as remoteproc
remoteproc: new driver for TI PRU
ARM: davinci_all_defconfig: enable PRU remoteproc module
ARM: dts: da850: add node for PRUSS
ARM: dts: am33xx: add node for PRU remoteproc
.../bindings/remoteproc/ti_pru_rproc.txt | 51 ++
MAINTAINERS | 5 +
arch/arm/boot/dts/am33xx.dtsi | 9 +
arch/arm/boot/dts/da850.dtsi | 8 +
arch/arm/configs/davinci_all_defconfig | 2 +
arch/arm/mach-omap2/pdata-quirks.c | 9 +
drivers/remoteproc/Kconfig | 7 +
drivers/remoteproc/Makefile | 1 +
drivers/remoteproc/imx_rproc.c | 2 +-
drivers/remoteproc/keystone_remoteproc.c | 3 +-
drivers/remoteproc/qcom_adsp_pil.c | 2 +-
drivers/remoteproc/qcom_q6v5_pil.c | 2 +-
drivers/remoteproc/qcom_wcnss.c | 2 +-
drivers/remoteproc/remoteproc_core.c | 10 +-
drivers/remoteproc/remoteproc_elf_loader.c | 117 +++-
drivers/remoteproc/remoteproc_internal.h | 2 +-
drivers/remoteproc/st_slim_rproc.c | 2 +-
drivers/remoteproc/ti_pru_rproc.c | 660 ++++++++++++++++++
drivers/remoteproc/wkup_m3_rproc.c | 3 +-
include/linux/platform_data/ti-pruss.h | 18 +
include/linux/remoteproc.h | 2 +-
include/uapi/linux/elf-em.h | 1 +
22 files changed, 899 insertions(+), 19 deletions(-)
create mode 100644 Documentation/devicetree/bindings/remoteproc/ti_pru_rproc.txt
create mode 100644 drivers/remoteproc/ti_pru_rproc.c
create mode 100644 include/linux/platform_data/ti-pruss.h
--
2.17.1
^ permalink raw reply [flat|nested] 58+ messages in thread* (unknown), @ 2018-02-12 1:39 Alfred Cheuk Chow 0 siblings, 0 replies; 58+ messages in thread From: Alfred Cheuk Chow @ 2018-02-12 1:39 UTC (permalink / raw) Good Day, I am Mr. Alfred Cheuk Yu Chow, the Director for Credit & Marketing Chong Hing Bank, Hong Kong, Chong Hing Bank Center, 24 Des Voeux Road Central, Hong Kong. I have a business proposal of $ 38,980,369.00. All confirmable documents to back up the claims will be made available to you prior to your acceptance and as soon as I receive your return mail. Best Regards, Alfred Chow. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH] default implementation for of_find_all_nodes(...)
@ 2017-08-30 18:32 Artur Lorincz
[not found] ` <1504117946-3958-1-git-send-email-larturus2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 58+ messages in thread
From: Artur Lorincz @ 2017-08-30 18:32 UTC (permalink / raw)
To: frowand.list; +Cc: devicetree, linux-kernel, larturus, Artur Lorincz
Added default implementation for of_find_all_nodes(). This function is
used by board.c from the board module (drivers/staging/board).
Signed-off-by: Artur Lorincz <larturus@yahoo.com>
---
include/linux/of.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/linux/of.h b/include/linux/of.h
index 4a8a709..0a9c17a 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -865,6 +865,11 @@ static inline void of_property_clear_flag(struct property *p, unsigned long flag
#define of_match_ptr(_ptr) NULL
#define of_match_node(_matches, _node) NULL
+
+static inline struct device_node *of_find_all_nodes(struct device_node *prev)
+{
+ return NULL;
+}
#endif /* CONFIG_OF */
/* Default string compare functions, Allow arch asm/prom.h to override */
--
1.9.1
^ permalink raw reply related [flat|nested] 58+ messages in thread[parent not found: <1504117946-3958-1-git-send-email-larturus2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* (unknown), [not found] ` <1504117946-3958-1-git-send-email-larturus2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2017-09-24 15:50 ` Artur Lorincz 2017-10-06 19:31 ` (unknown), Artur Lorincz 2017-10-08 16:28 ` (unknown), Artur Lorincz 2 siblings, 0 replies; 58+ messages in thread From: Artur Lorincz @ 2017-09-24 15:50 UTC (permalink / raw) To: frowand.list-Re5JQEeQqe8AvxtiuMwx3w Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, larturus-/E1597aS9LQAvxtiuMwx3w Hello, Could you please send me an update about this patch? Thanks, Artur -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), [not found] ` <1504117946-3958-1-git-send-email-larturus2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2017-09-24 15:50 ` (unknown), Artur Lorincz @ 2017-10-06 19:31 ` Artur Lorincz 2017-10-08 16:28 ` (unknown), Artur Lorincz 2 siblings, 0 replies; 58+ messages in thread From: Artur Lorincz @ 2017-10-06 19:31 UTC (permalink / raw) To: robh-DgEjT+Ai2ygdnm+yROfE0A Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, larturus-/E1597aS9LQAvxtiuMwx3w Hello, When you get to it, could you please send me an update about this patch? I believe the attached (trivial) patch should take less time to review then reading this message. Thanks, Artur -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), [not found] ` <1504117946-3958-1-git-send-email-larturus2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2017-09-24 15:50 ` (unknown), Artur Lorincz 2017-10-06 19:31 ` (unknown), Artur Lorincz @ 2017-10-08 16:28 ` Artur Lorincz 2 siblings, 0 replies; 58+ messages in thread From: Artur Lorincz @ 2017-10-08 16:28 UTC (permalink / raw) To: robh-DgEjT+Ai2ygdnm+yROfE0A Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, larturus-/E1597aS9LQAvxtiuMwx3w Hello, Thanks for checking the patch. I missed the #else part of he CONFIG_OF #ifdef previously. I made the code properly depend on CONFIG_OF now. I am not familiar with this code base. When time allows I would like to contribute by refactoring code in this area. Let me know if you have specific ideas about what should change and how the code should be refactored. Artur -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2017-06-23 4:50 nkosuta-f+iqBESB6gc 0 siblings, 0 replies; 58+ messages in thread From: nkosuta-f+iqBESB6gc @ 2017-06-23 4:50 UTC (permalink / raw) To: devicetree-u79uwXL29TY76Z2rM5mHXA [-- Attachment #1: 39579.zip --] [-- Type: application/zip, Size: 3602 bytes --] ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2017-06-10 7:07 Youichi Kanno 0 siblings, 0 replies; 58+ messages in thread From: Youichi Kanno @ 2017-06-10 7:07 UTC (permalink / raw) Sir/Madam I am sorry to encroach into your privacy in this manner, I found you listed in the Trade Center Chambers of Commerce directory here in Japan, My name is Youichi Kanno and I work in Audit & credit Supervisory role at The Norinchukin Bank, I need your assistance to process the fund claims oF $18,100,000.00 (Eighteen Million, One Hundred Thousand, USD) of a deceased client Mr. Grigor Kassan, And i need your assistance to process the fund claims, I only pray at this time that your address is still valid. I want to solicit your attention to receive this money on my behalf. The purpose of my contacting you is because my status would not permit me to do this alone. I hope to hear from you soon so we can discuss the logistic of moving the funds to a safe offshore bank. Yours sincerely, Youichi Kanno Phone Number: +81345400962 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2017-04-17 4:06 nkosuta-f+iqBESB6gc 0 siblings, 0 replies; 58+ messages in thread From: nkosuta-f+iqBESB6gc @ 2017-04-17 4:06 UTC (permalink / raw) To: devicetree [-- Attachment #1: $MONEY-52123352603-devicetree.zip --] [-- Type: application/zip, Size: 2171 bytes --] ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2017-04-03 6:14 Adrian Gillian Bayford 0 siblings, 0 replies; 58+ messages in thread From: Adrian Gillian Bayford @ 2017-04-03 6:14 UTC (permalink / raw) To: Recipients £1.5 Million Has Been Granted To You As A Donation Visit www.bbc.co.uk/news/uk-england-19254228 Sendname Address Phone for more info -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2017-03-20 19:40 janepatrick00-VmEwxm1hRrAnxqbYAscKCQ 0 siblings, 0 replies; 58+ messages in thread From: janepatrick00-VmEwxm1hRrAnxqbYAscKCQ @ 2017-03-20 19:40 UTC (permalink / raw) To: Recipients Hello, My name is Jane from UK, I came across you email address online, I will like to know more about you , I have a very important reason of contacting you which, I'll tell you in my next mail. I wait for your reply -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2017-03-14 17:14 nkosuta-f+iqBESB6gc 0 siblings, 0 replies; 58+ messages in thread From: nkosuta-f+iqBESB6gc @ 2017-03-14 17:14 UTC (permalink / raw) To: devicetree [-- Attachment #1: EMAIL_05109557_devicetree.zip --] [-- Type: application/zip, Size: 4727 bytes --] ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2017-02-16 21:01 Qin's Yanjun 0 siblings, 0 replies; 58+ messages in thread From: Qin's Yanjun @ 2017-02-16 21:01 UTC (permalink / raw) How are you today and your family? I'm Qin Yanjun, Tak-lam, SBS, JP, and Chief Executive of (HKMA). I have a concealed business suggestion for you, It require your attention and honest co-operation. Regards, Mr. Qin Yanjun ______________________________ Sky Silk, http://aknet.kz -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2016-12-14 2:45 Mr Friedrich Mayrhofer 0 siblings, 0 replies; 58+ messages in thread From: Mr Friedrich Mayrhofer @ 2016-12-14 2:45 UTC (permalink / raw) Good Day, This is the second time i am sending you this mail. I, Friedrich Mayrhofer Donate $ 1,000,000.00 to You, Email Me personally for more details. Regards. Friedrich Mayrhofer -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2016-11-28 9:58 Mr Friedrich Mayrhofer 0 siblings, 0 replies; 58+ messages in thread From: Mr Friedrich Mayrhofer @ 2016-11-28 9:58 UTC (permalink / raw) Good Day, This is the second time i am sending you this mail. I, Friedrich Mayrhofer Donate $ 1,000,000.00 to You, Email Me personally for more details. Regards. Friedrich Mayrhofer -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2016-11-20 22:16 Mr Friedrich Mayrhofer 0 siblings, 0 replies; 58+ messages in thread From: Mr Friedrich Mayrhofer @ 2016-11-20 22:16 UTC (permalink / raw) Good Day, This is the second time i am sending you this mail. I, Friedrich Mayrhofer Donate $ 1,000,000.00 to You, Email Me personally for more details. Regards. Friedrich Mayrhofer -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown),
@ 2016-09-30 14:37 Maxime Ripard
0 siblings, 0 replies; 58+ messages in thread
From: Maxime Ripard @ 2016-09-30 14:37 UTC (permalink / raw)
To: Rob Herring, Daniel Vetter, David Airlie, Archit Taneja
Cc: devicetree, dri-devel, Chen-Yu Tsai, Maxime Ripard,
linux-arm-kernel
Subject: [PATCH v5 0/5] drm: Add Support for Passive RGB to VGA bridges
Hi,
This serie is about adding support for the RGB to VGA bridge found in
the A13-Olinuxino and the CHIP VGA adapter.
Both these boards rely on an entirely passive bridge made out of
resitor ladders that do not require any initialisation. The only thing
needed is to get the timings from the screen if available (and if not,
fall back on XGA standards), set up the display pipeline to output on
the RGB bus with the proper timings, and you're done.
This serie also fixes a bunch of bugs uncovered when trying to
increase the resolution, and hence the pixel clock, of our
pipeline. It also fixes a few bugs in the DRM driver itself that went
unnoticed before.
Let me know what you think,
Maxime
Changes from v4:
- Removed unused functions
Changes from v3:
- Depends on OF in Kconfig
- Fixed typos in the driver comments
- Removed the mention of a "passive" bridge in the bindings doc
- Made the strcuture const
- Removed the nops and best_encoders implementations
- Removed the call to drm_bridge_enable in the sun4i driver
Changes from v2:
- Changed the compatible as suggested
- Rebased on top 4.8
Changes from v1:
- Switch to using a vga-connector
- Use drm_encoder bridge pointer instead of doing our own
- Report the connector status as unknown instead of connected by
default, and as connected only if we can retrieve the EDID.
- Switch to of_i2c_get_adapter by node, and put the reference when done
- Rebased on linux-next
Maxime Ripard (5):
drm/sun4i: rgb: Remove the bridge enable/disable functions
drm/bridge: Add RGB to VGA bridge support
ARM: sun5i: a13-olinuxino: Enable VGA bridge
ARM: multi_v7: enable VGA bridge
ARM: sunxi: Enable VGA bridge
.../bindings/display/bridge/rgb-to-vga-bridge.txt | 48 +++++
arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 54 +++++
arch/arm/configs/multi_v7_defconfig | 1 +
arch/arm/configs/sunxi_defconfig | 1 +
drivers/gpu/drm/bridge/Kconfig | 7 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/rgb-to-vga.c | 229 +++++++++++++++++++++
drivers/gpu/drm/sun4i/sun4i_rgb.c | 6 -
8 files changed, 341 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/bridge/rgb-to-vga-bridge.txt
create mode 100644 drivers/gpu/drm/bridge/rgb-to-vga.c
--
2.9.3
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 58+ messages in thread* (unknown), @ 2016-07-28 17:49 Ryan 0 siblings, 0 replies; 58+ messages in thread From: Ryan @ 2016-07-28 17:49 UTC (permalink / raw) To: devicetree-u79uwXL29TY76Z2rM5mHXA auth 74e10dbf subscribe devicetree ryanphilips19-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2016-05-18 16:26 Warner Losh 0 siblings, 0 replies; 58+ messages in thread From: Warner Losh @ 2016-05-18 16:26 UTC (permalink / raw) To: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Greetings, I was looking at the draft link posted here https://github.com/devicetree-org/devicetree-specification-released/blob/master/prerelease/devicetree-specification-v0.1-pre1-20160429.pdf a while ago. I hope this is the right place to ask about it. It raised a bit of a question. There's nothing in it talking about the current practice of using CPP to pre-process the .dts/.dtsi files before passing them into dtc to compile them into dtb. Normally, I see such things outside the scope of standardization. However, many of the .dts files that are in the wild today use a number of #define constants to make things more readable (having GPIO_ACTIVE_HIGH instead of '0' makes the .dts files easier to read). However, there's a small issue that I've had. The files that contain those definitions are currently in the Linux kernel and have a wide variety of licenses (including none at all). So before even getting to the notion of licenses and such (which past expereince suggests may be the worst place to start a discussion), I'm wondering where that will be defined, and if these #defines will become part of the standard for each of the bindings that are defined. I'm also wondering where the larger issue of using cpp to process the dts files will be discussed, since FreeBSD's BSDL dtc suffers interoperability due to this issue. Having the formal spec will also be helpful for its care and feeding since many fine points have had to be decided based on .dts files in the wild rather than a clear spec. Thanks again for spear-heading the effort to get a new version out now that ePAPR has fallen on hard times. Warner P.S. I'm mostly a FreeBSD guy, but just spent some time digging into this issue for another of the BSDs that's considering adopting DTS files. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown) @ 2016-01-11 6:54 wangwyy-hl91/bYNON7k1uMJSBkQmQ 0 siblings, 0 replies; 58+ messages in thread From: wangwyy-hl91/bYNON7k1uMJSBkQmQ @ 2016-01-11 6:54 UTC (permalink / raw) To: dfengsteel-Mj/0Miq2reM, dfdqyb-/E1597aS9LRv1O+Z8WTAqQ, dfdhcjs-/E1597aS9LRv1O+Z8WTAqQ, devilliang2003-/E1597aS9LRv1O+Z8WTAqQ, dfcmwhb-/E1597aS9LRv1O+Z8WTAqQ, dfcb203719-/E1597aS9LRv1O+Z8WTAqQ, dfertl-/E1597aS9LT0CCvOHzKKcA, dengjw2006-/E1597aS9LQAvxtiuMwx3w, devpandey007-/E1597aS9LQAvxtiuMwx3w, dfdpep-/E1597aS9LQAvxtiuMwx3w, dfdok-/E1597aS9LQAvxtiuMwx3w, devananthangovindasamy-/E1597aS9LQAvxtiuMwx3w, dezhimu-/E1597aS9LQAvxtiuMwx3w, dfevdong-dbdLmdGazhY, dfdichi-dbdLmdGazhY, dfd3fdf31-dbdLmdGazhY, dezheng5918-dbdLmdGazhY, deyeni-dbdLmdGazhY, devon199-icHrzHC44DVdHVCsmzoppAC/G2K4zDHf, dfdai-yKZSRQ1cFl8nDS1+zs4M5A, dfd.com.yahoomail.com.com.com.qmail-3K/ljU4b5cRWj0EZb7rXcA, dfermine-39ZsbGIQGT5GWvitb5QawA, deyuelou-uB8bxKUEBrdWk0Htik3J/w, devil2012-OlFFNeSka43QT0dZR+AlfA, dfcnyh-Q4arlSNMIUZBDgjK7y7TUQ, dfcgx-Q4arlSNMIUYnDS1+zs4M5A, den-GveOkT2v/s5BDgjK7y7TUQ, dfczyj-GveOkT2v/s5BDgjK7y7TUQ, dfcar-GveOkT2v/s5BDgjK7y7TUQ, devicetree-u79uwXL29TY76Z2rM5mHXA, devin_kao-53PKxisUrC1Wk0Htik3J/w, dfcm-N6yXg7DiKdn/Op/ZHr5HmtBPR1lH4CV8, dennisqiu-WVlzvzqoTvw, dfe2221a-WVlzvzqoTvw, devil.lucifer-WVlzvzqoTvw, dfdfd-WVlzvzqoTvw nd of smlast -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2015-09-18 14:57 Asia Heritage Foundation 0 siblings, 0 replies; 58+ messages in thread From: Asia Heritage Foundation @ 2015-09-18 14:57 UTC (permalink / raw) ATTENTION This is to inform you that you have been selected for this year fund donation please contact our online officer via email: asiaheritagefoundations-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org for more information of claims. From Mr.Rehan Omar. Secretary Asia Heritage Foundation (AHF) Italy Chapter -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2015-08-29 1:09 Zheng Group 0 siblings, 0 replies; 58+ messages in thread From: Zheng Group @ 2015-08-29 1:09 UTC (permalink / raw) Greetings, This is an official request for Professional/consultants who will stand as our regional representative to run logistics on behalf of zheng Group.We are looking for a payment collection agent in USA, Canada, Mexico and Europe. Salary is 10% of every payment you receive from our customers. Get back to us for more details if interested. contact us for more details. NOTE!!! it have no effect on your present job. Respectfully Mr Tadashi Itoh (Human Resources) zheng Group -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2015-08-04 15:37 Mark Salter 0 siblings, 0 replies; 58+ messages in thread From: Mark Salter @ 2015-08-04 15:37 UTC (permalink / raw) To: devicetree-u79uwXL29TY76Z2rM5mHXA unsubscribe devicetree -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2015-07-31 11:22 Mrs Christy Walton 0 siblings, 0 replies; 58+ messages in thread From: Mrs Christy Walton @ 2015-07-31 11:22 UTC (permalink / raw) To: peter.u2011-PkbjNfxxIARBDgjK7y7TUQ Greetings, This is an official request for Professional/consultants who will stand as our regional representative to run logistics on behalf of zheng Group.We are looking for a payment collection agent in USA, Canada, Mexico and Europe. Salary is 10% of every payment you receive from our customers. Get back to us for more details if interested. NOTE!!! it have no effect on your present job. (1)Your Full names: (2)Your Complete Address: a. City: b. State: c. Zip code: d. Country: (3)Tele/cell numbers: (4)Occupation: (5)Gender: (6)Age: (7)Email: Respectfully Mr Tadashi Itoh (Human Resources) zheng Group -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown),
@ 2015-07-22 14:05 Chunfeng Yun
0 siblings, 0 replies; 58+ messages in thread
From: Chunfeng Yun @ 2015-07-22 14:05 UTC (permalink / raw)
To: Mathias Nyman
Cc: Rob Herring, Mark Rutland, Matthias Brugger, Felipe Balbi,
Chunfeng Yun, Sascha Hauer, devicetree, linux-kernel,
linux-arm-kernel, Roger Quadros, linux-usb, linux-mediatek,
John Crispin, Daniel Kurtz
>From ac1e8724bfa47494223bad0af450c1a63cd2fe0c Mon Sep 17 00:00:00 2001
From: Chunfeng Yun <chunfeng.yun@mediatek.com>
Date: Wed, 22 Jul 2015 21:15:15 +0800
Subject: [PATCH 0/5] *** SUBJECT HERE ***
The patch supports MediaTek's xHCI controller.
There are some differences from xHCI spec:
1. The interval is specified in 250 * 8ns increments for Interrupt Moderation
Interval(IMODI) of the Interrupter Moderation(IMOD) register, it is 8 times as
much as that defined in xHCI spec.
2. For the value of TD Size in Normal TRB, MTK's xHCI controller defines a
number of packets that remain to be transferred for a TD after processing all
Max packets in all previous TRBs,that means don't include the current TRB's,
but in xHCI spec it includes the current ones.
3. To minimize the scheduling effort for synchronous endpoints in xHC, the MTK
architecture defines some extra SW scheduling parameters for HW. According to
these parameters provided by SW, the xHC can easily decide whether a
synchronous endpoint should be scheduled in a specific uFrame. The extra SW
scheduling parameters are put into reserved DWs in Slot and Endpoint Context.
And a bandwidth scheduler algorithm is added to support such feature.
A usb3.0 phy driver is also added which used by mt65xx SoCs platform, it
supports two usb2.0 ports and one usb3.0 port.
Change in v3:
1. implement generic phy
2. move opperations for IPPC and wakeup from phy driver to xHCI driver
3. seperate quirk functions into a single C file to fix up dependence issue
Chunfeng Yun (5):
dt-bindings: Add usb3.0 phy binding for MT65xx SoCs
dt-bindings: Add a binding for Mediatek xHCI host controller
usb: phy: add usb3.0 phy driver for mt65xx SoCs
xhci: mediatek: support MTK xHCI host controller
arm64: dts: mediatek: add xHCI & usb phy for mt8173
.../devicetree/bindings/phy/phy-mt65xx-u3.txt | 21 +
.../devicetree/bindings/usb/mt8173-xhci.txt | 50 ++
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 15 +
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 31 +
drivers/phy/Kconfig | 9 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-mt65xx-usb3.c | 426 +++++++++++
drivers/usb/host/Kconfig | 9 +
drivers/usb/host/Makefile | 4 +
drivers/usb/host/xhci-mtk-sch.c | 436 +++++++++++
drivers/usb/host/xhci-mtk.c | 836 +++++++++++++++++++++
drivers/usb/host/xhci-mtk.h | 135 ++++
drivers/usb/host/xhci-ring.c | 35 +-
drivers/usb/host/xhci.c | 19 +-
drivers/usb/host/xhci.h | 1 +
15 files changed, 2021 insertions(+), 7 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/phy-mt65xx-u3.txt
create mode 100644 Documentation/devicetree/bindings/usb/mt8173-xhci.txt
create mode 100644 drivers/phy/phy-mt65xx-usb3.c
create mode 100644 drivers/usb/host/xhci-mtk-sch.c
create mode 100644 drivers/usb/host/xhci-mtk.c
create mode 100644 drivers/usb/host/xhci-mtk.h
--
1.8.1.1.dirty
In-Reply-To:
^ permalink raw reply [flat|nested] 58+ messages in thread* (unknown), @ 2015-07-06 15:57 Maria McCumiskey 0 siblings, 0 replies; 58+ messages in thread From: Maria McCumiskey @ 2015-07-06 15:57 UTC (permalink / raw) I and my wife violet donated $500,000.00 USD as our personal donation to you this year 2015.Contact us: allenlarge0452-1ViLX0X+lBJBDgjK7y7TUQ@public.gmane.org -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2015-05-18 20:00 raghu MG 0 siblings, 0 replies; 58+ messages in thread From: raghu MG @ 2015-05-18 20:00 UTC (permalink / raw) To: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA Hi, This mail is regarding Linux smp boot on ARMADA-XP MV2860 . CPU-1 doesnt boot/go through the boot sequence & it fails to come online & dumps this message CPU1:failed to come online . The CPU-1 boot register is programmed with physical address of -->armada_xp_secondary_startup function & then cpu-0 deasserts the CPU-1. I am using armada-xp-gp.dts with armada-xp-mv78260.dts included in it. Any help would be appreciated. Regards -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2015-05-05 6:23 Alanoud AlFayeza 0 siblings, 0 replies; 58+ messages in thread From: Alanoud AlFayeza @ 2015-05-05 6:23 UTC (permalink / raw) I have a business proposal of a mutual benefit for you, contact for more information -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2015-03-25 20:46 Robert Smigielski 0 siblings, 0 replies; 58+ messages in thread From: Robert Smigielski @ 2015-03-25 20:46 UTC (permalink / raw) To: devicetree-u79uwXL29TY76Z2rM5mHXA subscribe -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2015-03-07 15:29 Mr John Wong 0 siblings, 0 replies; 58+ messages in thread From: Mr John Wong @ 2015-03-07 15:29 UTC (permalink / raw) To: Recipients Seeking Your Assistance In A Business Proposal get back to me if interested via email:mrjohn.wong-/E1597aS9LQAvxtiuMwx3w@public.gmane.org ------------------------ This email was scanned by BitDefender. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2015-02-18 16:14 Lee Jones 0 siblings, 0 replies; 58+ messages in thread From: Lee Jones @ 2015-02-18 16:14 UTC (permalink / raw) To: linux-arm-kernel, linux-kernel Cc: lee.jones, kernel, mturquette, sboyd, devicetree Subject: [PATCH v2 0/4] clk: st: New clock domain v1 => v2: - Turned the ST specific driver into a generic one Hardware can have a bunch of clocks which must not be turned off. If drivers a) fail to obtain a reference to any of these or b) give up a previously obtained reference during suspend, the common clk framework will attempt to turn them off and the hardware will subsequently die. The only way to recover from this failure is to restart. To avoid either of these two scenarios from catastrophically disabling the running system we have implemented a clock domain where clocks are consumed and references are taken, thus preventing them from being shut down by the framework. Lee Jones (4): ARM: sti: stih407-family: Supply defines for CLOCKGEN A0 ARM: sti: stih407-family: Provide Clock Domain information clk: Provide an always-on clock domain framework clk: dt: Introduce always-on clock domain documentation .../devicetree/bindings/clock/clk-domain.txt | 35 ++++++++++++ arch/arm/boot/dts/stih407-family.dtsi | 13 +++++ drivers/clk/Makefile | 1 + drivers/clk/clkdomain.c | 63 ++++++++++++++++++++++ include/dt-bindings/clock/stih407-clks.h | 4 ++ 5 files changed, 116 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/clk-domain.txt create mode 100644 drivers/clk/clkdomain.c -- 1.9.1 ^ permalink raw reply [flat|nested] 58+ messages in thread
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[parent not found: <1488091663.147175.1414957674639.JavaMail.yahoo-pZijWUW3o9/uQS8rMknbopOW+3bF1jUfVpNB7YpNyf8@public.gmane.org>]
* (unknown) [not found] ` <1488091663.147175.1414957674639.JavaMail.yahoo-pZijWUW3o9/uQS8rMknbopOW+3bF1jUfVpNB7YpNyf8@public.gmane.org> @ 2014-11-02 19:48 ` MRS GRACE MANDA 0 siblings, 0 replies; 58+ messages in thread From: MRS GRACE MANDA @ 2014-11-02 19:48 UTC (permalink / raw) [-- Attachment #1: Type: text/plain, Size: 140 bytes --] This is Mrs Grace Manda ( Please I need your Help is Urgent). This is Mrs Grace Manda ( Please I need your Help is Urgent). [-- Attachment #2: Mrs Grace Manda.rtf --] [-- Type: application/rtf, Size: 35796 bytes --] ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2014-10-06 19:57 Omar Hashim 0 siblings, 0 replies; 58+ messages in thread From: Omar Hashim @ 2014-10-06 19:57 UTC (permalink / raw) -- I have a lucrative business proposal of mutual interest to share with you, contact me if you are interested. -- -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown),
@ 2014-10-06 6:56 Suman Tripathi
0 siblings, 0 replies; 58+ messages in thread
From: Suman Tripathi @ 2014-10-06 6:56 UTC (permalink / raw)
To: olof, tj, arnd
Cc: linux-scsi, linux-ide, devicetree, linux-arm-kernel, ddutile, jcm,
patches, Suman Tripathi, Loc Ho, Ben Hutchings,
Greg Kroah-Hartman
commit 72f79f9e35bd3f78ee8853f2fcacaa197d23ebac upstream.
Subject: [PATCH 3.16 350/357] ahci_xgene: Removing NCQ support from the APM X-Gene SoC AHCI SATA Host Controller driver.
This patch removes the NCQ support from the APM X-Gene SoC AHCI
Host Controller driver as it doesn't support it.
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
[bwh: Backported to 3.16: host flags are passed to ahci_platform_init_host()]
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Suman Tripathi <stripathi@apm.com>
---
drivers/ata/ahci_xgene.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/drivers/ata/ahci_xgene.c
+++ b/drivers/ata/ahci_xgene.c
@@ -337,7 +337,7 @@ static struct ata_port_operations xgene_
};
static const struct ata_port_info xgene_ahci_port_info = {
- .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
+ .flags = AHCI_FLAG_COMMON,
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
.port_ops = &xgene_ahci_ops,
@@ -484,7 +484,7 @@ static int xgene_ahci_probe(struct platf
goto disable_resources;
}
- hflags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ;
+ hflags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_NCQ;
rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info,
hflags, 0, 0);
^ permalink raw reply [flat|nested] 58+ messages in thread* (unknown), @ 2014-09-29 3:16 Shengchao Guo 0 siblings, 0 replies; 58+ messages in thread From: Shengchao Guo @ 2014-09-29 3:16 UTC (permalink / raw) To: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org unsubscribe devicetree -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2014-09-22 7:45 Jingchang Lu 0 siblings, 0 replies; 58+ messages in thread From: Jingchang Lu @ 2014-09-22 7:45 UTC (permalink / raw) To: shawn.guo-KZfg59tc24xl57MIdRCFDg Cc: arnd-r2nGTMty4D4, mark.rutland-5wv7dgnIgG8, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA This series contain the support for Freescale LS1021A CPU and LS1021A-QDS and LS1021A-TWR board. The LS1021A SoC combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3W embedded communications processors and with a comprehensive enablement model focused on ease of programmability. The LS1021A SoC shares IPs with i.MX family, Vybrid family and Freescale PowerPC platform. For the detail information about LS1021A SoC, please refer to the RM doc. --- changes in v4: add "syscon" compatible to device tree scfg and dcfg node, and remove uncompleted dcsr related node. remove mxc_restart reference in DT_MACHINE_START. remove dma_zone_size defination in DT_MACHINE_START. changes in v3: rewrite scfg and dcfg binding doc description. remove sai related node leaving to the driver support. changes in v2: remove unused nodes. wakeup the secondary core by IPI call to u-boot standby procedure. add dt-bindings for LS1021A SoC and platform gerenal configuration nodes. ---------------------------------------------------------------- Jingchang Lu (6): ARM: dts: Add SoC level device tree support for LS1021A ARM: dts: Add initial LS1021A QDS board dts support ARM: dts: Add initial LS1021A TWR board dts support dt-bindings: arm: add Freescale LS1021A SoC device tree binding ARM: imx: Add initial support for Freescale LS1021A ARM: imx: Add Freescale LS1021A SMP support Documentation/devicetree/bindings/arm/fsl.txt | 38 ++++ arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/ls1021a-qds.dts | 285 ++++++++++++++++++++++++++ arch/arm/boot/dts/ls1021a-twr.dts | 117 +++++++++++ arch/arm/boot/dts/ls1021a.dtsi | 539 ++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/Kconfig | 14 ++ arch/arm/mach-imx/Makefile | 4 +- arch/arm/mach-imx/common.h | 1 + arch/arm/mach-imx/mach-ls1021a.c | 22 +++ arch/arm/mach-imx/platsmp.c | 32 +++ 10 files changed, 1053 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/ls1021a-qds.dts create mode 100755 arch/arm/boot/dts/ls1021a-twr.dts create mode 100644 arch/arm/boot/dts/ls1021a.dtsi create mode 100644 arch/arm/mach-imx/mach-ls1021a.c -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2014-09-20 23:12 M.K-YIN 0 siblings, 0 replies; 58+ messages in thread From: M.K-YIN @ 2014-09-20 23:12 UTC (permalink / raw) -- I have a portfolio project for you. Regards, M.K-YIN -- -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2014-03-11 3:29 Christian Organization 0 siblings, 0 replies; 58+ messages in thread From: Christian Organization @ 2014-03-11 3:29 UTC (permalink / raw) Good day, We are Christian organization, we give out loan to those that have given there lives to Christ, contact us via email marieloanlenders-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org Regard Mrs Marie -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown),
@ 2014-02-22 15:53 Hans de Goede
0 siblings, 0 replies; 58+ messages in thread
From: Hans de Goede @ 2014-02-22 15:53 UTC (permalink / raw)
To: Tejun Heo, Maxime Ripard
Cc: Oliver Schinagl, Richard Zhu, Roger Quadros, Lee Jones,
linux-ide-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
Hi all,
Here is v7 of my patchset for adding ahci-sunxi support. This is hopefully
the final final version of this set :)
Note I'm going on vacation for a week starting Monday, so if I'm not responding
that is why. Tejun if you feel some small cleanups are still necessary and
you don't want to wait for me to get back feel free to squash in any cleanups
you deem necessary.
This has been tested with Allwinner A10, Allwinner A20 and Freeware imx6x SoCs,
including suspend / resume. Note that the ahci_imx driver now also has imx53
sata support, it would be good if someone could test that with this series.
History:
v1, by Olliver Schinagl:
This was using the approach of having a platform device which probe method
creates a new child platform device which gets driven by ahci_platform.c,
as done by ahci_imx.c .
v2, by Hans de Goede:
Stand-alone platform driver based on Olliver's work
v3, by Hans de Goede:
patch-series, with 4 different parts
a) Make ahci_platform.c more generic, handle more then 1 clk, target pwr
regulator
b) New ahci-sunxi code only populating ahci_platform_data, passed to
ahci_platform.c to of_device_id matching.
c) Refactor ahci-imx code to work the same as the new ahci-sunxi code, this
is the reason why v3 is an RFC, I'm waiting for the wandboard I ordered to
arrive so that I can actually test this.
d) dts bindings for the sunxi ahci parts
v4, by Hans de Goede:
patch-series, with 5 different parts:
a) Make ahci_platform.c more generic, handle more then 1 clk, target pwr
regulator
b) Turn parts of ahci_platform.c into a library for use by other drivers
c) New ahci-sunxi driver using the ahci_platform.c library functionality
d) Refactor ahci-imx code to work the same as the new ahci-sunxi code
e) dts bindings for the sunxi ahci parts
v5:
v4 + the following changes:
1) fsl,imx6q driver is now tested
2) fixed suspend / resume on fsl,imx6q
3) Modifed devicetree node naming to match dt spec
4) Reworked the busy waiting code in the sunxi-phy handling as suggested by
Russell King
v6:
v5 rebased on top of 3.14-rc3 + the following changes
1) Added Roger Quadros' generic phy support series
2) Added a "ARM: sun4i: dt: Remove grouping + simple-bus for regulators" dts
patch
v7:
v6 + the following changes:
1) Addressed all Tejun's review remarks:
* Added function header comments to all exported ahci_platform functions
* Added comments in some other places
* Removed use of 2 empty lines to separate functions in some cases
* Use devres to automatically call ahci_platform_put_resources on
get_resource failure, probe failure and regular device remove
2) Dropped patches to move ahci_host_priv struct declaration to include/linux,
this was a left-over from v3 and is no longer necessary
3) Updated Roger's "ata: ahci_platform: Manage SATA PHY" patch:
* Update function header comments for the changes this makes
* Drop the Kconfig PHY requires hack, my patch for the phy-core to always be
built-in has been queued in Greg KH's tree, so this is no longer necessary.
4) Dropped Roger's "ata: ahci_platform: Add 'struct device' argument to ahci_platform_put_resources()"
patch, ahci_platform_put_resources already has a device argument as result
of it being changed into a devres release function
Tejun, can you please add patches 1-12 to your ata tree for 3.15 ?
Maxime, can you please add patch 13-15 to your dts tree for 3.15 ?
Thanks & Regards,
Hans
^ permalink raw reply [flat|nested] 58+ messages in thread* (unknown), @ 2014-02-16 11:35 Eleazar Molina Molina 0 siblings, 0 replies; 58+ messages in thread From: Eleazar Molina Molina @ 2014-02-16 11:35 UTC (permalink / raw) Good day. I am Mark Reyes Guus, I not work with Abn Amro Bank as an auditor. I have a proposition to discuss with you. Should you be interested, Please e-mail back to me. Private Email: markreyesguus@abnmrob.co.uk OR markguus.reyes01 @ yahoo.nl Yours Sincerely, Guus Mark Reyes. ________________________________ La información de este correo así como la contenida en los documentos que se adjuntan, pueden ser objeto de solicitudes de acceso a la información. Visítanos: http://www.ipn.mx ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2014-02-02 18:31 Davor Joja 0 siblings, 0 replies; 58+ messages in thread From: Davor Joja @ 2014-02-02 18:31 UTC (permalink / raw) To: mark.rutland-5wv7dgnIgG8; +Cc: devicetree-u79uwXL29TY76Z2rM5mHXA Hi, I would like to ask for comments on these patches. Their purpose is to show how I did binding for Xylon logiCVC IP core within DRM driver. First goal is to get comments on logiCVC binding so that I can use it in community approved form in DRM and FB drivers and then send drivers to review. Second goal is to get "xylon" prefix in vendor-prefixes. Thanks, Davor -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown),
@ 2014-01-16 16:11 Loc Ho
0 siblings, 0 replies; 58+ messages in thread
From: Loc Ho @ 2014-01-16 16:11 UTC (permalink / raw)
To: olof, tj, arnd
Cc: linux-scsi, linux-ide, devicetree, linux-arm-kernel, dmilburn,
jcm, patches, Loc Ho, Tuan Phan, Suman Tripathi
This patch adds support for the APM X-Gene SoC SATA host controller. In
order for the host controller to work, the corresponding PHY driver
musts also be available.
v10:
* Update binding documentation
v9:
* Remove ACPI/EFI include files
* Remove the IO flush support, interrupt routine, and DTS resources
* Remove function xgene_rd, xgene_wr, and xgene_wr_flush
* Remove PMP support (function xgene_ahci_qc_issue, xgene_ahci_qc_prep,
xgene_ahci_qc_fill_rtf, xgene_ahci_softreset, and xgene_ahci_do_softreset)
* Rename function xgene_ahci_enable_phy to xgene_ahci_force_phy_rdy
* Clean up hardreset functions
* Require v7 of the PHY driver
v8:
* Remove _ADDR from defines
* Remove define MSTAWAUX_COHERENT_BYPASS_SET and
STARAUX_COHERENT_BYPASS_SET and use direct coding
* Remove the un-necessary check for DTS boot with built in ACPI table
* Switch to use dma_set_mask_and_coherent for setting DMA mask
* Remove ACPI table matching code
* Update clock-names for sata01clk, sata23clk, and sata45clk
v7:
* Update the clock code by toggle the clock
* Update the DTS clock mask values due to the clock spilt between host and
v5 of the PHY drivers
v6:
* Update binding documentation
* Change select PHY_XGENE_SATA to PHY_XGENE
* Add ULL to constants
* Change indentation and comments
* Clean up the probe functions a bit more
* Remove xgene_ahci_remove function
* Add the flush register to DTS
* Remove the interrupt-parent from DTS
v5:
* Sync up to v3 of the PHY driver
* Remove MSLIM wrapper functions
* Change the memory shutdown loop to use usleep_range
* Use devm_ioremap_resource instead devm_ioremap
* Remove suspend/resume functions as not needed
v4:
* Remove the ID property in DT
* Remove the temporary PHY direct function call and use PHY function
* Change printk to pr_debug
* Move the IOB flush addresses into the DT
* Remove the parameters retrieval function as no longer needed
* Remove the header file as no longer needed
* Require v2 patch of the SATA PHY driver. Require slightly modification
in the Kconfig as it is moved to folder driver/phy and use Kconfig
PHY_XGENE_SATA instead SATA_XGENE_PHY.
v3:
* Move out the SATA PHY to another driver
* Remove the clock-cells entry from DTS
* Remove debug wrapper
* Remove delay functions wrapper
* Clean up resource and IRQ query
* Remove query clock name
* Switch to use dma_set_mask/dma_coherent_mask
* Remove un-necessary devm_kfree
* Update GPL license header to v2
* Spilt up function xgene_ahci_hardreset
* Spilt up function xgene_ahci_probe
* Remove all reference of CONFIG_ARCH_MSLIM
* Clean up chip revision code
v2:
* Clean up file sata_xgene.c with Lindent and etc
* Clean up file sata_xgene_serdes.c with Lindent and etc
* Add description to each patch
v1:
* inital version
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Tuan Phan <tphan@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
---
Loc Ho (4):
ata: Export required functions by APM X-Gene SATA driver
Documentation: Add documentation for APM X-Gene SoC SATA host
controller DTS binding
ata: Add APM X-Gene SoC SATA host controller driver
arm64: Add APM X-Gene SoC SATA host controller DTS entries
.../devicetree/bindings/ata/apm-xgene.txt | 70 +++
arch/arm64/boot/dts/apm-storm.dtsi | 75 +++
drivers/ata/Kconfig | 8 +
drivers/ata/Makefile | 1 +
drivers/ata/ahci.h | 9 +
drivers/ata/libahci.c | 16 +-
drivers/ata/sata_xgene.c | 630 ++++++++++++++++++++
7 files changed, 803 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/apm-xgene.txt
create mode 100644 drivers/ata/sata_xgene.c
^ permalink raw reply [flat|nested] 58+ messages in thread* (unknown),
@ 2014-01-16 16:09 Loc Ho
0 siblings, 0 replies; 58+ messages in thread
From: Loc Ho @ 2014-01-16 16:09 UTC (permalink / raw)
To: olof, tj, arnd
Cc: linux-scsi, linux-ide, devicetree, linux-arm-kernel, dmilburn,
jcm, patches, Loc Ho, Tuan Phan, Suman Tripathi
This patch adds support for APM X-Gene SoC 15Gbps Multi-purpose PHY. This
is the physical layer interface for the corresponding host controller. This
driver uses the new PHY generic framework posted by Kishon Vijay Abrahm.
In addition, the new PHY generic framework is patched to provide an
function to set the speed of the PHY.
v8
* Update binding documentation
* Remove XGENE_PHY_DTS and XGENE_PHY_EXT_DTS defines
* Remove support for internal clock
* Remove support for external reference CMU
* Remove the need for external reference resource DTS entry and its related
code
v7
* Add/Update PHY CMU/lane parameters and its default values
* Rename variable enable_manual_cal to preA3Chip
* Remove function phy_rd, phy_wr, and phy_wr_flush
* Change function cmu_wr, cmu_rd, cmu_toggle1to0, cmu_clrbits, cmu_setbits,
serdes_wr, serdes_rd, serdes_clrbits, and serdes_setbits to take context
instead void *
* Remove function serdes_toggle1to0
* Decrease the polling time from 10ms to 1ms on CMU calibration complete
detection
* Move all SATA specify code in function xgene_phy_hw_initialize into
function xgene_phy_hw_init_sata
* Add usleep_range after starting summer/latch calibrations
* Add usleep_range between receiver reset (function xgene_phy_reset_rxd)
* Save and restore PHY register 31 instead writing 0 in function
xgene_phy_gen_avg_val
* Update function xgene_phy_sata_force_gen programming sequences
* Add support to reset the receiver lane in function xgene_phy_set_speed
if speed is 0
* Update PHY parameters in DTS per controller
* Some minor code clean up
v6
* Move PHY document to Documentation/devicetree/binding/phy
* Remove _ADDR from all register defines
* Update clock-names property for sataphy1clk, sataphy2clk, and sataphy3clk
v5
* Update DTS binding documentation
* Remove direct clock access and use clock interface instead
* Change override parameters to decimal instead hex values
* Change apm,tx-amplitude, apm,tx-pre-cursor1, apm,tx-pre-cursor2,
apm,tx-post-cursor to be unit of uV
v4
* Update documentation with 'apm,' instead 'apm-'
* Change DTS override parameter to have 'apm,'
* Add select GENERIC_PHY to Kconfig PHY_XGENE
* Make override parameters to be pair of three values instead one
* Some minor comment and indentation changes
* Remove error register addition offset
* Add ULL to constants
* Use module_init instead subsys_initcall
* Make DTS node based on first register address
* Update override setting values
v3
* Major re-write of the code based on various review comments
* Support external clock only at the moment
* Support SATA mode only at the moment
* No UEFI support at the moment
v2
* Remove port knowledge from functions
* Make all functions static
* Remove ID completely
* Make resource requirement based on compatible type
* Rename override PHY parameters with more descriptive name
* Add override PHY parameter for per controller, per port, and per speed
* Patch the generic PHY frame to expose set_speed operation
v1
* Initial version
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Tuan Phan <tphan@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
---
Loc Ho (4):
PHY: Add function set_speed to generic PHY framework
Documentation: Add APM X-Gene SoC 15Gbps Multi-purpose PHY driver
binding documentation
PHY: add APM X-Gene SoC 15Gbps Multi-purpose PHY driver
arm64: Add APM X-Gene SoC 15Gbps Multi-purpose PHY DTS entries
.../devicetree/bindings/phy/apm-xgene-phy.txt | 79 +
arch/arm64/boot/dts/apm-storm.dtsi | 75 +
drivers/phy/Kconfig | 7 +
drivers/phy/Makefile | 2 +
drivers/phy/phy-core.c | 21 +
drivers/phy/phy-xgene.c | 1793 ++++++++++++++++++++
include/linux/phy/phy.h | 8 +
7 files changed, 1985 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/apm-xgene-phy.txt
create mode 100644 drivers/phy/phy-xgene.c
^ permalink raw reply [flat|nested] 58+ messages in thread* (unknown), @ 2014-01-13 10:32 Lothar Waßmann 0 siblings, 0 replies; 58+ messages in thread From: Lothar Waßmann @ 2014-01-13 10:32 UTC (permalink / raw) To: linux-arm-kernel, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Shawn Guo, Sascha Hauer, devicetree, linux-kernel This patchset adds support for the Ka-Ro electronics i.MX53 based modules. The first patch adds a new pingroup for NAND pads that is used by the modules. ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2014-01-13 10:29 Lothar Waßmann 0 siblings, 0 replies; 58+ messages in thread From: Lothar Waßmann @ 2014-01-13 10:29 UTC (permalink / raw) To: linux-arm-kernel, Shawn Guo, Sascha Hauer, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Thierry Reding, devicetree, linux-kernel, linux-pwm This patchset adds support for inverting the PWM output in hardware by setting the POUTC bit in the PWMCR register. This feature is controlled via the standard DT flas for PWMs. The first patch does a minor source cleanup without any functional change. ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown) @ 2014-01-11 0:37 klightspeed-aslSrjg9ejhWX4hkXwHRhw 0 siblings, 0 replies; 58+ messages in thread From: klightspeed-aslSrjg9ejhWX4hkXwHRhw @ 2014-01-11 0:37 UTC (permalink / raw) >From f3b6db2e9607c22d1a7e16de9c4872539f4d786c Mon Sep 17 00:00:00 2001 To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, klightspeed-aslSrjg9ejhWX4hkXwHRhw@public.gmane.org Date: Sat, 11 Jan 2014 10:03:58 +1000 Subject: [PATCH] ARM: parameter initrd must override FDT initrd The initrd_start and initrd_end as set by FDT was overriding the phys_initrd_start and phys_initrd_size set by the initrd= kernel parameter. This patch will ignore the initrd_start and initrd_end set earlier if phys_initrd_start and phys_initrd_size (as set by the initrd= parameter) are set. Signed-off-by: Ben Peddell <klightspeed-aslSrjg9ejhWX4hkXwHRhw@public.gmane.org> --- arch/arm/mm/init.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 1f7b19a..819c539 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -345,10 +345,11 @@ void __init arm_memblock_init(struct meminfo *mi, #endif #ifdef CONFIG_BLK_DEV_INITRD /* FDT scan will populate initrd_start */ - if (initrd_start) { + if (initrd_start && !phys_initrd_size) { phys_initrd_start = __virt_to_phys(initrd_start); phys_initrd_size = initrd_end - initrd_start; } + initrd_start = initrd_end = 0; if (phys_initrd_size && !memblock_is_region_memory(phys_initrd_start, phys_initrd_size)) { pr_err("INITRD: 0x%08llx+0x%08lx is not a memory region - disabling initrd\n", -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 58+ messages in thread
* (unknown),
@ 2013-12-12 7:30 Loc Ho
0 siblings, 0 replies; 58+ messages in thread
From: Loc Ho @ 2013-12-12 7:30 UTC (permalink / raw)
To: olof, tj, arnd
Cc: linux-scsi, linux-ide, devicetree, linux-arm-kernel, jcm, patches,
Loc Ho, Tuan Phan, Suman Tripathi
This patch adds support for APM X-Gene SoC 15Gbps Multi-purpose PHY. This
is the physical layer interface for the corresponding host controller. This
driver uses the new PHY generic framework posted by Kishon Vijay Abrahm.
In addition, the new PHY generic framework is patched to provide an
function to set the speed of the PHY.
v4
* Update documentation with 'apm,' instead 'apm-'
* Change DTS override parameter to have 'apm,'
* Add select GENERIC_PHY to Kconfig PHY_XGENE
* Make override parameters to be pair of three values instead one
* Some minor comment and indentation changes
* Remove error register addition offset
* Add ULL to constants
* Use module_init instead subsys_initcall
* Make DTS node based on first register address
* Update override setting values
v3
* Major re-write of the code based on various review comments
* Support external clock only at the moment
* Support SATA mode only at the moment
* No UEFI support at the moment
v2
* Remove port knowledge from functions
* Make all functions static
* Remove ID completely
* Make resource requirement based on compatible type
* Rename override PHY parameters with more descriptive name
* Add override PHY parameter for per controller, per port, and per speed
* Patch the generic PHY frame to expose set_speed operation
v1
* Initial version
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Tuan Phan <tphan@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
---
Loc Ho (4):
PHY: Add function set_speed to generic PHY framework
Documentation: Add APM X-Gene SoC 15Gbps Multi-purpose PHY driver
binding documentation
PHY: add APM X-Gene SoC 15Gbps Multi-purpose PHY driver
arm64: Add APM X-Gene SoC 15Gbps Multi-purpose PHY DTS entries
.../devicetree/bindings/ata/apm-xgene-phy.txt | 89 +
arch/arm64/boot/dts/apm-storm.dtsi | 31 +
drivers/phy/Kconfig | 7 +
drivers/phy/Makefile | 2 +
drivers/phy/phy-core.c | 21 +
drivers/phy/phy-xgene.c | 1854 ++++++++++++++++++++
include/linux/phy/phy.h | 8 +
7 files changed, 2012 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/apm-xgene-phy.txt
create mode 100644 drivers/phy/phy-xgene.c
^ permalink raw reply [flat|nested] 58+ messages in thread* (unknown), @ 2013-12-05 7:01 Jagan Teki 0 siblings, 0 replies; 58+ messages in thread From: Jagan Teki @ 2013-12-05 7:01 UTC (permalink / raw) To: devicetree-u79uwXL29TY76Z2rM5mHXA -- Thanks, Jagan. -------- Jagannadha Sutradharudu Teki, E: jagannadh.teki-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, P: +91-9676773388 Engineer - System Software Hacker U-boot - SPI Custodian and Zynq APSOC Ln: http://www.linkedin.com/in/jaganteki -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2013-11-21 5:53 Management 0 siblings, 0 replies; 58+ messages in thread From: Management @ 2013-11-21 5:53 UTC (permalink / raw) This is an automatic message by the system to let you know that you have to confirm your account information. An Attempt has been made to login from a new computer. For the security of your account. Your Email account will be frozen temporary after 48 hours in order to protect it. The account will continue to be frozen until it is confirmed.Once you have updated your account records, your information will be confirmed and your account will start to work as normal once again. The process does not take more than 5 minutes To proceed to confirm your account information Click on this link or copy and paste in your browser tab: http://666-17-79187.webs.com/ -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown) @ 2013-11-08 20:28 Dave & Angela Dawes 0 siblings, 0 replies; 58+ messages in thread From: Dave & Angela Dawes @ 2013-11-08 20:28 UTC (permalink / raw) This is Dave and Angela, My wife and I won the biggest Euro Millions, we just commenced a Charity Donation by giving out to five (5) individuals; we listed you as a recipient of our cash donation. get back to us for more info and proof. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown), @ 2013-11-01 7:04 Xiubo Li 0 siblings, 0 replies; 58+ messages in thread From: Xiubo Li @ 2013-11-01 7:04 UTC (permalink / raw) To: r65073, timur, lgirdwood, broonie Cc: r64188, rob.herring, pawel.moll, mark.rutland, swarren, ian.campbell, rob, linux, perex, tiwai, grant.likely, fabio.estevam, LW, oskar, shawn.guo, b42378, b18965, devicetree, linux-doc, linux-kernel, linux-arm-kernel, alsa-devel, linuxppc-dev Hello, This patch series is mostly Freescale's SAI SoC Digital Audio Interface driver implementation. And the implementation is only compatible with device tree definition. This patch series is based on linux-next and has been tested on Vybrid VF610 Tower board using device tree. Changed in v2: - Use default settings for the generic dmaengine PCM driver. - Separate receive and transmit setting in most functions, but some couldn't for the HW limitation. - Drop some not reduntant code. - Use devm_snd_soc_register_component() instead of snd_soc_register_component(). - Use devm_snd_soc_register_card() instead of devm_snd_soc_register_card(). - Adjust the code sentences sequence. - Make the namespacing consistent. - Rename CONFIG_SND_SOC_FSL_SGTL5000 to CONFIG_SND_SOC_FSL_SGTL5000_VF610. - Drop some meaningless lines. - Rename the binding document file. Added in v1: - Add SAI SoC Digital Audio Interface driver. - Add Freescale SAI ALSA SoC Digital Audio Interface node for VF610. - Enables SAI ALSA SoC DAI device for Vybrid VF610 TOWER board. - Add device tree bindings for Freescale SAI. - Revise the bugs about the sgt15000 codec. - Add SGT15000 based audio machine driver. - Enable SGT15000 codec based audio driver node for VF610. - Add device tree bindings for Freescale VF610 sound. ^ permalink raw reply [flat|nested] 58+ messages in thread
* (unknown)
@ 2012-10-05 7:15 Robert Schwebel
0 siblings, 0 replies; 58+ messages in thread
From: Robert Schwebel @ 2012-10-05 7:15 UTC (permalink / raw)
To: Guennadi Liakhovetski
Cc: Steffen Trumtrar, devicetree-discuss, Rob Herring, linux-fbdev,
dri-devel, Laurent Pinchart, linux-media, TomiValkeinen
<tomi.valkeinen@ti.com>, pza
Bcc:
Subject: Re: [PATCH 1/2 v6] of: add helper to parse display timings
Reply-To:
In-Reply-To: <Pine.LNX.4.64.1210042307300.3744@axis700.grange>
X-Sent-From: Pengutronix Hildesheim
X-URL: http://www.pengutronix.de/
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0,61
On Thu, Oct 04, 2012 at 11:35:35PM +0200, Guennadi Liakhovetski wrote:
> > +optional properties:
> > + - hsync-active-high (bool): Hsync pulse is active high
> > + - vsync-active-high (bool): Vsync pulse is active high
>
> For the above two we also considered using bool properties but eventually
> settled down with integer ones:
>
> - hsync-active = <1>
>
> for active-high and 0 for active low. This has the added advantage of
> being able to omit this property in the .dts, which then doesn't mean,
> that the polarity is active low, but rather, that the hsync line is not
> used on this hardware. So, maybe it would be good to use the same binding
> here too?
Philipp, this is the same argumentation as we discussed yesterday for
the dual-link LVDS option, so that one could be modelled in a similar
way.
rsc
--
Pengutronix e.K. | |
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^ permalink raw reply [flat|nested] 58+ messages in thread* (unknown), @ 2012-04-25 6:57 jobhunts02 0 siblings, 0 replies; 58+ messages in thread From: jobhunts02 @ 2012-04-25 6:57 UTC (permalink / raw) To: gdb-thread.msg00270, gdb-thread.00270, raytaliaferro2, devicetree-discuss, gdb-thread.271, netfilter, wireshark-users-request, jordan_hargrave, linux-mtd http://www.jagsxc.com/templates/beez/easyJob12.html ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ ^ permalink raw reply [flat|nested] 58+ messages in thread
end of thread, other threads:[~2018-06-23 21:08 UTC | newest]
Thread overview: 58+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-05-24 1:21 (unknown), Loc Ho
[not found] ` <1400894467-1585-1-git-send-email-lho-qTEPVZfXA3Y@public.gmane.org>
2014-05-24 1:21 ` [PATCH v2 1/4] MAINTAINERS: Add entry for APM X-Gene SoC EDAC driver Loc Ho
[not found] ` <1400894467-1585-2-git-send-email-lho-qTEPVZfXA3Y@public.gmane.org>
2014-05-24 1:21 ` [PATCH v2 2/4] Documentation: Add documentation for the APM X-Gene SoC EDAC DTS binding Loc Ho
[not found] ` <1400894467-1585-3-git-send-email-lho-qTEPVZfXA3Y@public.gmane.org>
2014-05-24 1:21 ` [PATCH v2 3/4] edac: Add APM X-Gene SoC EDAC driver Loc Ho
[not found] ` <1400894467-1585-4-git-send-email-lho-qTEPVZfXA3Y@public.gmane.org>
2014-05-24 1:21 ` [PATCH v2 4/4] arm64: Add APM X-Gene SoC EDAC DTS entries Loc Ho
2014-05-30 10:29 ` [PATCH v2 3/4] edac: Add APM X-Gene SoC EDAC driver Borislav Petkov
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[not found] <1570038211.167595.1414613146892.JavaMail.yahoo@jws10056.mail.ne1.yahoo.com>
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[not found] ` <1488091663.147175.1414957674639.JavaMail.yahoo-pZijWUW3o9/uQS8rMknbopOW+3bF1jUfVpNB7YpNyf8@public.gmane.org>
2014-11-02 19:48 ` (unknown) MRS GRACE MANDA
2014-10-06 19:57 (unknown), Omar Hashim
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2014-09-29 3:16 (unknown), Shengchao Guo
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2014-03-11 3:29 (unknown), Christian Organization
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2014-01-13 10:29 (unknown), Lothar Waßmann
2014-01-11 0:37 (unknown) klightspeed-aslSrjg9ejhWX4hkXwHRhw
2013-12-12 7:30 (unknown), Loc Ho
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2013-11-21 5:53 (unknown), Management
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