From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kishon Vijay Abraham I Subject: [PATCH v2 06/18] ARM: dts: DRA7: Add divider table to optfclk_pciephy_div clock Date: Thu, 29 May 2014 12:08:08 +0530 Message-ID: <1401345500-20188-7-git-send-email-kishon@ti.com> References: <1401345500-20188-1-git-send-email-kishon@ti.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1401345500-20188-1-git-send-email-kishon@ti.com> Sender: linux-kernel-owner@vger.kernel.org To: devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: arnd@arndb.de, tony@atomide.com, jg1.han@samsung.com, kishon@ti.com, Keerthy , Rajendra Nayak , Tero Kristo , Paul Walmsley List-Id: devicetree@vger.kernel.org From: Keerthy Add divider table to optfclk_pciephy_div clock. The Documentation for divider clock can be found at ../clock/ti/divider.txt Cc: Rajendra Nayak Cc: Tero Kristo Cc: Paul Walmsley Signed-off-by: Keerthy Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index c767687..55e95c5 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1170,6 +1170,7 @@ clocks = <&apll_pcie_ck>; #clock-cells = <0>; reg = <0x021c>; + ti,dividers = <2>, <1>; ti,bit-shift = <8>; ti,max-div = <2>; }; -- 1.7.9.5