[RFC PATCH 0/7] ARM: OMAP4+: PRM: minor cleanups and dt support of interrupts

[RFC PATCH 0/7] ARM: OMAP4+: PRM: minor cleanups and dt support of interrupts

[Nishanth Menon]

Hi,

The following series is a minimal set of cleanups and generalization
in the direction of supporting daisychain wakeup on all OMAP4+
platforms. We cannot still add IO_WAKEUP ability for OMAP5/DRA7/AM437x
yet pending further pinctrl patches.

These do have a few cosmetic issues, but hope is to get a view about
the approach. Also note that documentation of bindings for ti,dra7-prm
etc are still pending.

Nishanth Menon (7):
  ARM: OMAP4+: prminst: provide function to find prm_dev instance
    offset
  ARM: OMAP4: prm use the generic prm_inst to allow logic to be
    abstracted
  ARM: OMAP4+: PRM: remove "wkup" event
  ARM: OMAP4+: PRM: register interrupt information from DT
  ARM: dts: OMAP4: Add PRM interrupt
  ARM: dts: OMAP5: add PRM interrupt
  ARM: dts: DRA7: add PRM interrupt

 arch/arm/boot/dts/dra7.dtsi       |    1 +
 arch/arm/boot/dts/omap4.dtsi      |    1 +
 arch/arm/boot/dts/omap5.dtsi      |    1 +
 arch/arm/mach-omap2/prm44xx.c     |   89 ++++++++++++++++++++++++++++++++-----
 arch/arm/mach-omap2/prminst44xx.c |   41 ++++++++++-------
 arch/arm/mach-omap2/prminst44xx.h |    3 ++
 6 files changed, 111 insertions(+), 25 deletions(-)

-- 
1.7.9.5

Regards,
Nishanth Menon

[RFC PATCH 1/7] ARM: OMAP4+: prminst: provide function to find prm_dev instance offset

[Nishanth Menon]

PRM device instance can vary depending on SoC. We already handle the
same during reset of the device, However, this is also needed
for other logic instances. So, first abstract this out to a generic
function.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/mach-omap2/prminst44xx.c |   41 +++++++++++++++++++++++--------------
 arch/arm/mach-omap2/prminst44xx.h |    3 +++
 2 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 69f0dd0..fd2549d 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -31,6 +31,8 @@
 
 static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
 
+static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN;
+
 /**
  * omap_prm_base_init - Populates the prm partitions
  *
@@ -41,6 +43,25 @@ void omap_prm_base_init(void)
 {
 	_prm_bases[OMAP4430_PRM_PARTITION] = prm_base;
 	_prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
+
+}
+
+s32 omap4_prmst_get_prm_dev_inst(void)
+{
+	if (prm_dev_inst != PRM_INSTANCE_UNKNOWN)
+		return prm_dev_inst;
+
+	/* This cannot be done way early at boot.. as things are not setup */
+	if (cpu_is_omap44xx())
+		prm_dev_inst = OMAP4430_PRM_DEVICE_INST;
+	else if (soc_is_omap54xx())
+		prm_dev_inst = OMAP54XX_PRM_DEVICE_INST;
+	else if (soc_is_dra7xx())
+		prm_dev_inst = DRA7XX_PRM_DEVICE_INST;
+	else if (soc_is_am43xx())
+		prm_dev_inst = AM43XX_PRM_DEVICE_INST;
+
+	return prm_dev_inst;
 }
 
 /* Read a register in a PRM instance */
@@ -169,28 +190,18 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
 void omap4_prminst_global_warm_sw_reset(void)
 {
 	u32 v;
-	s16 dev_inst;
+	s32 inst = omap4_prmst_get_prm_dev_inst();
 
-	if (cpu_is_omap44xx())
-		dev_inst = OMAP4430_PRM_DEVICE_INST;
-	else if (soc_is_omap54xx())
-		dev_inst = OMAP54XX_PRM_DEVICE_INST;
-	else if (soc_is_dra7xx())
-		dev_inst = DRA7XX_PRM_DEVICE_INST;
-	else if (soc_is_am43xx())
-		dev_inst = AM43XX_PRM_DEVICE_INST;
-	else
+	if (inst == PRM_INSTANCE_UNKNOWN)
 		return;
 
-	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, dev_inst,
+	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, inst,
 					OMAP4_PRM_RSTCTRL_OFFSET);
 	v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
 	omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
-				 dev_inst,
-				 OMAP4_PRM_RSTCTRL_OFFSET);
+				 inst, OMAP4_PRM_RSTCTRL_OFFSET);
 
 	/* OCP barrier */
 	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
-				    dev_inst,
-				    OMAP4_PRM_RSTCTRL_OFFSET);
+				    inst, OMAP4_PRM_RSTCTRL_OFFSET);
 }
diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
index a2ede2d..583aa37 100644
--- a/arch/arm/mach-omap2/prminst44xx.h
+++ b/arch/arm/mach-omap2/prminst44xx.h
@@ -12,6 +12,9 @@
 #ifndef __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H
 #define __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H
 
+#define PRM_INSTANCE_UNKNOWN	-1
+extern s32 omap4_prmst_get_prm_dev_inst(void);
+
 /*
  * In an ideal world, we would not export these low-level functions,
  * but this will probably take some time to fix properly
-- 
1.7.9.5

[RFC PATCH 2/7] ARM: OMAP4: prm use the generic prm_inst to allow logic to be abstracted

[Nishanth Menon]

use the generic function to pick up the prm_instance for a generic logic
which can be reused from OMAP4+

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/mach-omap2/prm44xx.c |   47 +++++++++++++++++++++++++++++++++--------
 1 file changed, 38 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a7f6ea2..d4d745e 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -154,21 +154,36 @@ void omap4_prm_vp_clear_txdone(u8 vp_id)
 
 u32 omap4_prm_vcvp_read(u8 offset)
 {
+	s32 inst = omap4_prmst_get_prm_dev_inst();
+
+	if (inst == PRM_INSTANCE_UNKNOWN)
+		return 0;
+
 	return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
-					   OMAP4430_PRM_DEVICE_INST, offset);
+					   inst, offset);
 }
 
 void omap4_prm_vcvp_write(u32 val, u8 offset)
 {
+	s32 inst = omap4_prmst_get_prm_dev_inst();
+
+	if (inst == PRM_INSTANCE_UNKNOWN)
+		return;
+
 	omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
-				     OMAP4430_PRM_DEVICE_INST, offset);
+				     inst, offset);
 }
 
 u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
 {
+	s32 inst = omap4_prmst_get_prm_dev_inst();
+
+	if (inst == PRM_INSTANCE_UNKNOWN)
+		return 0;
+
 	return omap4_prminst_rmw_inst_reg_bits(mask, bits,
 					       OMAP4430_PRM_PARTITION,
-					       OMAP4430_PRM_DEVICE_INST,
+					       inst,
 					       offset);
 }
 
@@ -275,14 +290,18 @@ void omap44xx_prm_restore_irqen(u32 *saved_mask)
 void omap44xx_prm_reconfigure_io_chain(void)
 {
 	int i = 0;
+	s32 inst = omap4_prmst_get_prm_dev_inst();
+
+	if (inst == PRM_INSTANCE_UNKNOWN)
+		return;
 
 	/* Trigger WUCLKIN enable */
 	omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
 				    OMAP4430_WUCLK_CTRL_MASK,
-				    OMAP4430_PRM_DEVICE_INST,
+				    inst,
 				    OMAP4_PRM_IO_PMCTRL_OFFSET);
 	omap_test_timeout(
-		(((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+		(((omap4_prm_read_inst_reg(inst,
 					   OMAP4_PRM_IO_PMCTRL_OFFSET) &
 		   OMAP4430_WUCLK_STATUS_MASK) >>
 		  OMAP4430_WUCLK_STATUS_SHIFT) == 1),
@@ -292,10 +311,10 @@ void omap44xx_prm_reconfigure_io_chain(void)
 
 	/* Trigger WUCLKIN disable */
 	omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
-				    OMAP4430_PRM_DEVICE_INST,
+				    inst,
 				    OMAP4_PRM_IO_PMCTRL_OFFSET);
 	omap_test_timeout(
-		(((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+		(((omap4_prm_read_inst_reg(inst,
 					   OMAP4_PRM_IO_PMCTRL_OFFSET) &
 		   OMAP4430_WUCLK_STATUS_MASK) >>
 		  OMAP4430_WUCLK_STATUS_SHIFT) == 0),
@@ -316,9 +335,14 @@ void omap44xx_prm_reconfigure_io_chain(void)
  */
 static void __init omap44xx_prm_enable_io_wakeup(void)
 {
+	s32 inst = omap4_prmst_get_prm_dev_inst();
+
+	if (inst == PRM_INSTANCE_UNKNOWN)
+		return;
+
 	omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
 				    OMAP4430_GLOBAL_WUEN_MASK,
-				    OMAP4430_PRM_DEVICE_INST,
+				    inst,
 				    OMAP4_PRM_IO_PMCTRL_OFFSET);
 }
 
@@ -333,8 +357,13 @@ static u32 omap44xx_prm_read_reset_sources(void)
 	struct prm_reset_src_map *p;
 	u32 r = 0;
 	u32 v;
+	s32 inst = omap4_prmst_get_prm_dev_inst();
+
+	if (inst == PRM_INSTANCE_UNKNOWN)
+		return 0;
+
 
-	v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+	v = omap4_prm_read_inst_reg(inst,
 				    OMAP4_RM_RSTST);
 
 	p = omap44xx_prm_reset_src_map;
-- 
1.7.9.5

[RFC PATCH 3/7] ARM: OMAP4+: PRM: remove "wkup" event

[Nishanth Menon]

"wkup" event at bit offset 0 exists only on OMAP3.
OMAP4430/60 PRM_IRQSTATUS_A9, OMAP5/DRA7 PRM_IRQSTATUS_MPU

register bit 0 is DPLL_CORE_RECAL_ST not wakeup event like OMAP3.

The same applies to AM437x as well.

Remove the wrong definition.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/mach-omap2/prm44xx.c |    1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index d4d745e..1ecf244 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -32,7 +32,6 @@
 /* Static data */
 
 static const struct omap_prcm_irq omap4_prcm_irqs[] = {
-	OMAP_PRCM_IRQ("wkup",   0,      0),
 	OMAP_PRCM_IRQ("io",     9,      1),
 };
 
-- 
1.7.9.5

[RFC PATCH 4/7] ARM: OMAP4+: PRM: register interrupt information from DT

[Nishanth Menon]

Allow the PRM interrupt information to be picked up from device tree.
the only exception is for OMAP4 which uses values pre-populated and allows
compatibility with older dtb.

Signed-off-by: Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>
---
 arch/arm/mach-omap2/prm44xx.c |   41 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 1ecf244..784b3e1 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -17,6 +17,7 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/of_irq.h>
 
 
 #include "soc.h"
@@ -698,11 +699,51 @@ int __init omap44xx_prm_init(void)
 	return prm_register(&omap44xx_prm_ll_data);
 }
 
+static struct of_device_id omap_prm_dt_match_table[] = {
+	{ .compatible = "ti,omap4-prm" },
+	{ .compatible = "ti,omap5-prm" },
+	{ .compatible = "ti,dra7-prm" },
+	{ }
+};
+
 static int omap44xx_prm_late_init(void)
 {
+	struct device_node *np;
+	int irq_num;
+
+	/* OMAP4+ is DT only now */
+	if (!of_have_populated_dt())
+		return 0;
+
 	if (!(prm_features & PRM_HAS_IO_WAKEUP))
 		return 0;
 
+	np = of_find_matching_node(NULL, omap_prm_dt_match_table);
+
+	if (!np) {
+		/* Default loaded up with OMAP4 values - older dtb compatible? */
+		if (!cpu_is_omap44xx())
+			return 0;
+	} else {
+		irq_num = of_irq_get(np, 0);
+		/*
+		 * Already have OMAP4 IRQ num. For all other platforms, we need
+		 * IRQ numbers from DT - old dtb compatible?
+		 */
+		if (irq_num < 0 && !cpu_is_omap44xx()) {
+
+			if (irq_num == -EPROBE_DEFER)
+				return irq_num;
+
+			/* Have nothing to do */
+			return 0;
+		}
+
+		/* Once OMAP4 DT is filled as well */
+		if (irq_num >= 0)
+			omap4_prcm_irq_setup.irq = irq_num;
+	}
+
 	omap44xx_prm_enable_io_wakeup();
 
 	return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
-- 
1.7.9.5

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[RFC PATCH 5/7] ARM: dts: OMAP4: Add PRM interrupt

[Nishanth Menon]

Provide OMAP4 interrupt number for PRM

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/boot/dts/omap4.dtsi |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 7e26d22..6d2827f 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -129,6 +129,7 @@
 		prm: prm@4a306000 {
 			compatible = "ti,omap4-prm";
 			reg = <0x4a306000 0x3000>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 
 			prm_clocks: clocks {
 				#address-cells = <1>;
-- 
1.7.9.5

[RFC PATCH 6/7] ARM: dts: OMAP5: add PRM interrupt

[Nishanth Menon]

Provide OMAP5 interrupt number for PRM

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/boot/dts/omap5.dtsi |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 3bfda16..ccced95 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -132,6 +132,7 @@
 		prm: prm@4ae06000 {
 			compatible = "ti,omap5-prm";
 			reg = <0x4ae06000 0x3000>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 
 			prm_clocks: clocks {
 				#address-cells = <1>;
-- 
1.7.9.5

[RFC PATCH 7/7] ARM: dts: DRA7: add PRM interrupt

[Nishanth Menon]

Provide default DRA7 crossbar mapped interrupt for prm interrupt

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index c29945e..38e8097 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -85,6 +85,7 @@
 		prm: prm@4ae06000 {
 			compatible = "ti,dra7-prm";
 			reg = <0x4ae06000 0x3000>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 
 			prm_clocks: clocks {
 				#address-cells = <1>;
-- 
1.7.9.5

Re: [RFC PATCH 0/7] ARM: OMAP4+: PRM: minor cleanups and dt support of interrupts

[Nishanth Menon]

On 06/05/2014 10:35 PM, Nishanth Menon wrote:
> 
> Hi,
> 
> The following series is a minimal set of cleanups and generalization
> in the direction of supporting daisychain wakeup on all OMAP4+
> platforms. We cannot still add IO_WAKEUP ability for OMAP5/DRA7/AM437x
> yet pending further pinctrl patches.
> 
> These do have a few cosmetic issues, but hope is to get a view about
> the approach. Also note that documentation of bindings for ti,dra7-prm
> etc are still pending.
> 
> Nishanth Menon (7):
>   ARM: OMAP4+: prminst: provide function to find prm_dev instance
>     offset
>   ARM: OMAP4: prm use the generic prm_inst to allow logic to be
>     abstracted
>   ARM: OMAP4+: PRM: remove "wkup" event
>   ARM: OMAP4+: PRM: register interrupt information from DT
>   ARM: dts: OMAP4: Add PRM interrupt
>   ARM: dts: OMAP5: add PRM interrupt
>   ARM: dts: DRA7: add PRM interrupt
> 
>  arch/arm/boot/dts/dra7.dtsi       |    1 +
>  arch/arm/boot/dts/omap4.dtsi      |    1 +
>  arch/arm/boot/dts/omap5.dtsi      |    1 +
>  arch/arm/mach-omap2/prm44xx.c     |   89 ++++++++++++++++++++++++++++++++-----
>  arch/arm/mach-omap2/prminst44xx.c |   41 ++++++++++-------
>  arch/arm/mach-omap2/prminst44xx.h |    3 ++
>  6 files changed, 111 insertions(+), 25 deletions(-)
> 
Gentle ping on this series? are we ok with this approach?

-- 
Regards,
Nishanth Menon

Re: [RFC PATCH 3/7] ARM: OMAP4+: PRM: remove "wkup" event

[Tony Lindgren]

* Nishanth Menon <nm@ti.com> [140605 20:37]:
> "wkup" event at bit offset 0 exists only on OMAP3.
> OMAP4430/60 PRM_IRQSTATUS_A9, OMAP5/DRA7 PRM_IRQSTATUS_MPU
> 
> register bit 0 is DPLL_CORE_RECAL_ST not wakeup event like OMAP3.

Hmm so why was it added originally then?

Do the PRM_IRQSTATUS line and the following line belong together
or is it missing something?

Regards,

Tony
 
> The same applies to AM437x as well.
> 
> Remove the wrong definition.
> 
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>  arch/arm/mach-omap2/prm44xx.c |    1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
> index d4d745e..1ecf244 100644
> --- a/arch/arm/mach-omap2/prm44xx.c
> +++ b/arch/arm/mach-omap2/prm44xx.c
> @@ -32,7 +32,6 @@
>  /* Static data */
>  
>  static const struct omap_prcm_irq omap4_prcm_irqs[] = {
> -	OMAP_PRCM_IRQ("wkup",   0,      0),
>  	OMAP_PRCM_IRQ("io",     9,      1),
>  };
>  
> -- 
> 1.7.9.5
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
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Re: [RFC PATCH 4/7] ARM: OMAP4+: PRM: register interrupt information from DT

[Tony Lindgren]

* Nishanth Menon <nm@ti.com> [140605 20:37]:
> Allow the PRM interrupt information to be picked up from device tree.
> the only exception is for OMAP4 which uses values pre-populated and allows
> compatibility with older dtb.
> 
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>  arch/arm/mach-omap2/prm44xx.c |   41 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 41 insertions(+)
> 
> diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
> index 1ecf244..784b3e1 100644
> --- a/arch/arm/mach-omap2/prm44xx.c
> +++ b/arch/arm/mach-omap2/prm44xx.c
> @@ -17,6 +17,7 @@
>  #include <linux/errno.h>
>  #include <linux/err.h>
>  #include <linux/io.h>
> +#include <linux/of_irq.h>
>  
>  
>  #include "soc.h"
> @@ -698,11 +699,51 @@ int __init omap44xx_prm_init(void)
>  	return prm_register(&omap44xx_prm_ll_data);
>  }
>  
> +static struct of_device_id omap_prm_dt_match_table[] = {
> +	{ .compatible = "ti,omap4-prm" },
> +	{ .compatible = "ti,omap5-prm" },
> +	{ .compatible = "ti,dra7-prm" },
> +	{ }
> +};
> +

I'd like to avoid adding more driver like stuff to mach-omap2
and parsing compatible flags and dealing with interupts sounds
very driver like.. But maybe just the handling can be moved
out?

Would a simple driver be doable that parses the compatible
flags, takes care of the IRQ chaining, and gets some SoC specific
function pointers as auxdata?

That would allow further work later on to remove the auxdata
dependencies possibly.

Regards,

Tony

Re: [RFC PATCH 3/7] ARM: OMAP4+: PRM: remove "wkup" event

[Nishanth Menon]

On Mon, Jul 21, 2014 at 5:44 AM, Tony Lindgren <tony@atomide.com> wrote:
>
> Hmm so why was it added originally then?
>
> Do the PRM_IRQSTATUS line and the following line belong together
> or is it missing something?


Seems like to have been a copy paste from OMAP3 code which did have
wakeup event at bit 0.

-- 
---
Regards,
Nishanth Menon

Re: [RFC PATCH 4/7] ARM: OMAP4+: PRM: register interrupt information from DT

[Nishanth Menon]

On Mon, Jul 21, 2014 at 5:51 AM, Tony Lindgren <tony@atomide.com> wrote:
>
>> +static struct of_device_id omap_prm_dt_match_table[] = {
>> +     { .compatible = "ti,omap4-prm" },
>> +     { .compatible = "ti,omap5-prm" },
>> +     { .compatible = "ti,dra7-prm" },
>> +     { }
>> +};
>> +
>
> I'd like to avoid adding more driver like stuff to mach-omap2
> and parsing compatible flags and dealing with interupts sounds
> very driver like.. But maybe just the handling can be moved
> out?

I understand your view, but, Handling of interrupts is already in
place even now in mach-omap2. Currently the prm devices are handled by
mach-omap2 and all this does it to prevent hardcoding of irq numbers
within the current code.
>
> Would a simple driver be doable that parses the compatible
> flags, takes care of the IRQ chaining, and gets some SoC specific
> function pointers as auxdata?

Tero has been trying to move PRM/CM stuff to a separate drivers of
thier own. With that there wont be a need for auxdata even. - this
current logic will get merged with that driver - if and when that is
ready. I am not actually adding any driver logic here - just reusing
the logic and providing glue for using dt description instead of
hardcoded logic that the current mach-omap2 driver does.

>
> That would allow further work later on to remove the auxdata
> dependencies possibly.




-- 
---
Regards,
Nishanth Menon

Re: [RFC PATCH 4/7] ARM: OMAP4+: PRM: register interrupt information from DT

[Tony Lindgren]

* Nishanth Menon <nm@ti.com> [140721 04:24]:
> On Mon, Jul 21, 2014 at 5:51 AM, Tony Lindgren <tony@atomide.com> wrote:
> >
> >> +static struct of_device_id omap_prm_dt_match_table[] = {
> >> +     { .compatible = "ti,omap4-prm" },
> >> +     { .compatible = "ti,omap5-prm" },
> >> +     { .compatible = "ti,dra7-prm" },
> >> +     { }
> >> +};
> >> +
> >
> > I'd like to avoid adding more driver like stuff to mach-omap2
> > and parsing compatible flags and dealing with interupts sounds
> > very driver like.. But maybe just the handling can be moved
> > out?
> 
> I understand your view, but, Handling of interrupts is already in
> place even now in mach-omap2. Currently the prm devices are handled by
> mach-omap2 and all this does it to prevent hardcoding of irq numbers
> within the current code.

Yeah but at a cost of no dev entry, no probe etc. I'd rather keep
that SoC specific data around until a driver can deal with it
in a standard way.

> > Would a simple driver be doable that parses the compatible
> > flags, takes care of the IRQ chaining, and gets some SoC specific
> > function pointers as auxdata?
> 
> Tero has been trying to move PRM/CM stuff to a separate drivers of
> thier own. With that there wont be a need for auxdata even. - this
> current logic will get merged with that driver - if and when that is
> ready. I am not actually adding any driver logic here - just reusing
> the logic and providing glue for using dt description instead of
> hardcoded logic that the current mach-omap2 driver does.

Well how about let's just leave out the non-standard parts for
now, then once the PRM/CM driver can deal with, it can do things
in a normal way?

Regards,

Tony

Re: [RFC PATCH 4/7] ARM: OMAP4+: PRM: register interrupt information from DT

[Nishanth Menon]

On Mon, Jul 21, 2014 at 6:28 AM, Tony Lindgren <tony@atomide.com> wrote:
> * Nishanth Menon <nm@ti.com> [140721 04:24]:
>> On Mon, Jul 21, 2014 at 5:51 AM, Tony Lindgren <tony@atomide.com> wrote:
>> >
>> >> +static struct of_device_id omap_prm_dt_match_table[] = {
>> >> +     { .compatible = "ti,omap4-prm" },
>> >> +     { .compatible = "ti,omap5-prm" },
>> >> +     { .compatible = "ti,dra7-prm" },
>> >> +     { }
>> >> +};
>> >> +
>> >
>> > I'd like to avoid adding more driver like stuff to mach-omap2
>> > and parsing compatible flags and dealing with interupts sounds
>> > very driver like.. But maybe just the handling can be moved
>> > out?
>>
>> I understand your view, but, Handling of interrupts is already in
>> place even now in mach-omap2. Currently the prm devices are handled by
>> mach-omap2 and all this does it to prevent hardcoding of irq numbers
>> within the current code.
>
> Yeah but at a cost of no dev entry, no probe etc. I'd rather keep
> that SoC specific data around until a driver can deal with it
> in a standard way.
>
>> > Would a simple driver be doable that parses the compatible
>> > flags, takes care of the IRQ chaining, and gets some SoC specific
>> > function pointers as auxdata?
>>
>> Tero has been trying to move PRM/CM stuff to a separate drivers of
>> thier own. With that there wont be a need for auxdata even. - this
>> current logic will get merged with that driver - if and when that is
>> ready. I am not actually adding any driver logic here - just reusing
>> the logic and providing glue for using dt description instead of
>> hardcoded logic that the current mach-omap2 driver does.
>
> Well how about let's just leave out the non-standard parts for
> now, then once the PRM/CM driver can deal with, it can do things
> in a normal way?

Broken PRCM interrupt handling for DRA7. but if you like to state
which parts are ok, I can probably repost with just those and leave
the rest for when ever PRM / CM driver happens to work out (and as a
result keep DRA7 daisy chain support broken till then - so probably
blocking low power features such as suspend-to-ram till that work is
complete.).

-- 
---
Regards,
Nishanth Menon

Re: [RFC PATCH 4/7] ARM: OMAP4+: PRM: register interrupt information from DT

[Tony Lindgren]

* Nishanth Menon <nm@ti.com> [140721 05:11]:
> On Mon, Jul 21, 2014 at 6:28 AM, Tony Lindgren <tony@atomide.com> wrote:
> > * Nishanth Menon <nm@ti.com> [140721 04:24]:
> >> On Mon, Jul 21, 2014 at 5:51 AM, Tony Lindgren <tony@atomide.com> wrote:
> >> >
> >> >> +static struct of_device_id omap_prm_dt_match_table[] = {
> >> >> +     { .compatible = "ti,omap4-prm" },
> >> >> +     { .compatible = "ti,omap5-prm" },
> >> >> +     { .compatible = "ti,dra7-prm" },
> >> >> +     { }
> >> >> +};
> >> >> +
> >> >
> >> > I'd like to avoid adding more driver like stuff to mach-omap2
> >> > and parsing compatible flags and dealing with interupts sounds
> >> > very driver like.. But maybe just the handling can be moved
> >> > out?
> >>
> >> I understand your view, but, Handling of interrupts is already in
> >> place even now in mach-omap2. Currently the prm devices are handled by
> >> mach-omap2 and all this does it to prevent hardcoding of irq numbers
> >> within the current code.
> >
> > Yeah but at a cost of no dev entry, no probe etc. I'd rather keep
> > that SoC specific data around until a driver can deal with it
> > in a standard way.
> >
> >> > Would a simple driver be doable that parses the compatible
> >> > flags, takes care of the IRQ chaining, and gets some SoC specific
> >> > function pointers as auxdata?
> >>
> >> Tero has been trying to move PRM/CM stuff to a separate drivers of
> >> thier own. With that there wont be a need for auxdata even. - this
> >> current logic will get merged with that driver - if and when that is
> >> ready. I am not actually adding any driver logic here - just reusing
> >> the logic and providing glue for using dt description instead of
> >> hardcoded logic that the current mach-omap2 driver does.
> >
> > Well how about let's just leave out the non-standard parts for
> > now, then once the PRM/CM driver can deal with, it can do things
> > in a normal way?
> 
> Broken PRCM interrupt handling for DRA7. but if you like to state
> which parts are ok, I can probably repost with just those and leave
> the rest for when ever PRM / CM driver happens to work out (and as a
> result keep DRA7 daisy chain support broken till then - so probably
> blocking low power features such as suspend-to-ram till that work is
> complete.).

Well if Tero is fine with this approach, looks OK for me. At least
the .dts entries should work in the long run.

Regards,

Tony