From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Bresticker Subject: [PATCH v1 7/9] ARM: tegra: Add Tegra124 XUSB mailbox and XHCI controller Date: Tue, 17 Jun 2014 23:16:18 -0700 Message-ID: <1403072180-4944-8-git-send-email-abrestic@chromium.org> References: <1403072180-4944-1-git-send-email-abrestic@chromium.org> Return-path: In-Reply-To: <1403072180-4944-1-git-send-email-abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Randy Dunlap , Stephen Warren , Thierry Reding , Russell King , Linus Walleij , Greg Kroah-Hartman , Mathias Nyman , Grant Likely , Alan Stern , Kishon Vijay Abraham I , Arnd Bergmann , Andrew Bresticker List-Id: devicetree@vger.kernel.org Add nodes for the Tegra XUSB mailbox and Tegra XHCI controller. Update the XUSB pad controller node with a phandle to the XUSB mailbox. Signed-off-by: Andrew Bresticker --- arch/arm/boot/dts/tegra124.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 514e490..4e1cd92 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -480,11 +480,42 @@ status = "disabled"; }; + usb@0,70090000 { + compatible = "nvidia,tegra124-xhci"; + reg = <0x0 0x70090000 0x0 0x8000>, + <0x0 0x70098000 0x0 0x1000>, + <0x0 0x70099000 0x0 0x1000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, + <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_SS>, + <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, + <&tegra_car TEGRA124_CLK_PLL_U_480M>, + <&tegra_car TEGRA124_CLK_CLK_M>, + <&tegra_car TEGRA124_CLK_PLL_E>; + clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", + "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", + "pll_u_480m", "clk_m", "pll_e"; + resets = <&tegra_car 89>, <&tegra_car 156>; + reset-names = "xusb_host", "xusb_ss"; + nvidia,xusb-mbox = <&mbox>; + status = "disabled"; + }; + + mbox: mailbox@0,70098000 { + compatible = "nvidia,tegra124-xusb-mbox"; + reg = <0x0 0x70098000 0x0 0x1000>; + interrupts = ; + }; + padctl: padctl@0,7009f000 { compatible = "nvidia,tegra124-xusb-padctl"; reg = <0x0 0x7009f000 0x0 0x1000>; resets = <&tegra_car 142>; reset-names = "padctl"; + nvidia,xusb-mbox = <&mbox>; #phy-cells = <1>; }; -- 2.0.0.526.g5318336