From mboxrd@z Thu Jan 1 00:00:00 1970 From: Boris BREZILLON Subject: [RESEND PATCH v3 09/11] ARM: at91/dt: define the HLCDC node available on sama5d3 SoCs Date: Mon, 7 Jul 2014 18:43:02 +0200 Message-ID: <1404751384-5077-10-git-send-email-boris.brezillon@free-electrons.com> References: <1404751384-5077-1-git-send-email-boris.brezillon@free-electrons.com> Return-path: In-Reply-To: <1404751384-5077-1-git-send-email-boris.brezillon@free-electrons.com> Sender: linux-pwm-owner@vger.kernel.org To: Samuel Ortiz , Lee Jones , Thierry Reding , linux-pwm@vger.kernel.org, David Airlie , dri-devel@lists.freedesktop.org, Nicolas Ferre , Jean-Christophe Plagniol-Villard , Alexandre Belloni , Andrew Victor Cc: Jean-Jacques Hiblot , Laurent Pinchart , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , devicetree@vger.kernel.org, Bo Shen , Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, Robert Nelson , Tim Niemeyer , Boris BREZILLON List-Id: devicetree@vger.kernel.org Define the HLCDC (HLCD Controller) IP available on some sama5d3 SoCs (i.e. sama5d31, sama5d33, sama5d34 and sama5d36) in sama5d3 dtsi file. Signed-off-by: Boris BREZILLON --- arch/arm/boot/dts/sama5d3_lcd.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi index 9642eef..f6aa637 100644 --- a/arch/arm/boot/dts/sama5d3_lcd.dtsi +++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi @@ -166,6 +166,26 @@ }; }; + hlcdc: hlcdc@f0030000 { + compatible = "atmel,sama5d3-hlcdc"; + reg = <0xf0030000 0x2000>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-dc"; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; + pmc: pmc@fffffc00 { periphck { lcdc_clk: lcdc_clk { -- 1.8.3.2