From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kishon Vijay Abraham I Subject: [RESEND PATCH 2/8] ARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck Date: Mon, 14 Jul 2014 16:12:17 +0530 Message-ID: <1405334543-25509-3-git-send-email-kishon@ti.com> References: <1405334543-25509-1-git-send-email-kishon@ti.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1405334543-25509-1-git-send-email-kishon@ti.com> Sender: linux-kernel-owner@vger.kernel.org To: linux-kernel@vger.kernel.org, tony@atomide.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org Cc: kishon@ti.com, Keerthy , Rajendra Nayak , Tero Kristo , Paul Walmsley List-Id: devicetree@vger.kernel.org From: Keerthy Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck from dpll_pcie_ref_ck. Figure 26-22. DPLL_PCIE_REF Functional Block Diagram in vE of DRA7xx ES1.0 TRM shows the signal name for the output of post divider (M2) is CLKOUTLDO. Figure 26-21. PCIe PHY Clock Generator Overview shows CLKOUTLDO is used as input to apll mux. So the actual output of dpll is dpll_pcie_ref_m2ldo_ck which is also the input of apll. Cc: Rajendra Nayak Cc: Tero Kristo Cc: Paul Walmsley Signed-off-by: Keerthy Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 7148e7c..f5dca1f 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1152,7 +1152,7 @@ apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { compatible = "ti,mux-clock"; - clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>; + clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; #clock-cells = <0>; reg = <0x021c 0x4>; ti,bit-shift = <7>; -- 1.7.9.5