From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kishon Vijay Abraham I Subject: [RESEND PATCH 3/8] ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY Date: Mon, 14 Jul 2014 16:12:18 +0530 Message-ID: <1405334543-25509-4-git-send-email-kishon@ti.com> References: <1405334543-25509-1-git-send-email-kishon@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1405334543-25509-1-git-send-email-kishon@ti.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: linux-kernel@vger.kernel.org, tony@atomide.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org Cc: Mark Rutland , Paul Walmsley , Pawel Moll , Rajendra Nayak , kishon@ti.com, Tero Kristo , Rob Herring , Kumar Gala List-Id: devicetree@vger.kernel.org Added missing 32KHz clock used by PCIe PHY. Figure 26-19. PCIe PHY Subsystem Integration in vE of DRA7xx ES1.0 TRM shows 32KHz is used by PCIe PHY. Cc: Rajendra Nayak Cc: Tero Kristo Cc: Paul Walmsley Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index f5dca1f..3ff6d7c 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1165,6 +1165,14 @@ reg = <0x021c>, <0x0220>; }; + optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 { + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + #clock-cells = <0>; + reg = <0x13b0>; + ti,bit-shift = <8>; + }; + optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { compatible = "ti,divider-clock"; clocks = <&apll_pcie_ck>; -- 1.7.9.5