From: Gabriel FERNANDEZ <gabriel.fernandez@st.com>
To: mturquette@linaro.org, robh+dt@kernel.org, pawel.moll@arm.com,
mark.rutland@arm.com, ijc+devicetree@hellion.org.uk,
galak@codeaurora.org
Cc: devicetree@vger.kernel.org, kernel@stlinux.com,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
Gabriel Fernandez <gabriel.fernandez@linaro.org>,
Lee Jones <lee.jones@linaro.org>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 03/15] drivers: clk: st: use static const for clkgen_pll_data tables
Date: Tue, 15 Jul 2014 17:20:19 +0200 [thread overview]
Message-ID: <1405437631-23623-4-git-send-email-gabriel.fernandez@linaro.org> (raw)
In-Reply-To: <1405437631-23623-1-git-send-email-gabriel.fernandez@linaro.org>
converts clkgen_pll_data tables into static const
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
drivers/clk/st/clkgen-pll.c | 30 ++++++++++++++----------------
1 file changed, 14 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index d8b9b1a..cdf23db 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -59,7 +59,7 @@ static const struct clk_ops st_pll800c65_ops;
static const struct clk_ops stm_pll3200c32_ops;
static const struct clk_ops st_pll1200c32_ops;
-static struct clkgen_pll_data st_pll1600c65_ax = {
+static const struct clkgen_pll_data st_pll1600c65_ax = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 19),
.locked_status = CLKGEN_FIELD(0x0, 0x1, 31),
.mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL1600_MASK, 0),
@@ -67,7 +67,7 @@ static struct clkgen_pll_data st_pll1600c65_ax = {
.ops = &st_pll1600c65_ops
};
-static struct clkgen_pll_data st_pll800c65_ax = {
+static const struct clkgen_pll_data st_pll800c65_ax = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 19),
.locked_status = CLKGEN_FIELD(0x0, 0x1, 31),
.mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL800_MASK, 0),
@@ -76,7 +76,7 @@ static struct clkgen_pll_data st_pll800c65_ax = {
.ops = &st_pll800c65_ops
};
-static struct clkgen_pll_data st_pll3200c32_a1x_0 = {
+static const struct clkgen_pll_data st_pll3200c32_a1x_0 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 31),
.locked_status = CLKGEN_FIELD(0x4, 0x1, 31),
.ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 0x0),
@@ -93,7 +93,7 @@ static struct clkgen_pll_data st_pll3200c32_a1x_0 = {
.ops = &stm_pll3200c32_ops,
};
-static struct clkgen_pll_data st_pll3200c32_a1x_1 = {
+static const struct clkgen_pll_data st_pll3200c32_a1x_1 = {
.pdn_status = CLKGEN_FIELD(0xC, 0x1, 31),
.locked_status = CLKGEN_FIELD(0x10, 0x1, 31),
.ndiv = CLKGEN_FIELD(0xC, C32_NDIV_MASK, 0x0),
@@ -111,7 +111,7 @@ static struct clkgen_pll_data st_pll3200c32_a1x_1 = {
};
/* 415 specific */
-static struct clkgen_pll_data st_pll3200c32_a9_415 = {
+static const struct clkgen_pll_data st_pll3200c32_a9_415 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
.locked_status = CLKGEN_FIELD(0x6C, 0x1, 0),
.ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 9),
@@ -122,7 +122,7 @@ static struct clkgen_pll_data st_pll3200c32_a9_415 = {
.ops = &stm_pll3200c32_ops,
};
-static struct clkgen_pll_data st_pll3200c32_ddr_415 = {
+static const struct clkgen_pll_data st_pll3200c32_ddr_415 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
.locked_status = CLKGEN_FIELD(0x100, 0x1, 0),
.ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
@@ -135,7 +135,7 @@ static struct clkgen_pll_data st_pll3200c32_ddr_415 = {
.ops = &stm_pll3200c32_ops,
};
-static struct clkgen_pll_data st_pll1200c32_gpu_415 = {
+static const struct clkgen_pll_data st_pll1200c32_gpu_415 = {
.pdn_status = CLKGEN_FIELD(0x144, 0x1, 3),
.locked_status = CLKGEN_FIELD(0x168, 0x1, 0),
.ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
@@ -146,7 +146,7 @@ static struct clkgen_pll_data st_pll1200c32_gpu_415 = {
};
/* 416 specific */
-static struct clkgen_pll_data st_pll3200c32_a9_416 = {
+static const struct clkgen_pll_data st_pll3200c32_a9_416 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
.locked_status = CLKGEN_FIELD(0x6C, 0x1, 0),
.ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
@@ -157,7 +157,7 @@ static struct clkgen_pll_data st_pll3200c32_a9_416 = {
.ops = &stm_pll3200c32_ops,
};
-static struct clkgen_pll_data st_pll3200c32_ddr_416 = {
+static const struct clkgen_pll_data st_pll3200c32_ddr_416 = {
.pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
.locked_status = CLKGEN_FIELD(0x10C, 0x1, 0),
.ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
@@ -170,7 +170,7 @@ static struct clkgen_pll_data st_pll3200c32_ddr_416 = {
.ops = &stm_pll3200c32_ops,
};
-static struct clkgen_pll_data st_pll1200c32_gpu_416 = {
+static const struct clkgen_pll_data st_pll1200c32_gpu_416 = {
.pdn_status = CLKGEN_FIELD(0x8E4, 0x1, 3),
.locked_status = CLKGEN_FIELD(0x90C, 0x1, 0),
.ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
@@ -450,9 +450,8 @@ static void __init clkgena_c65_pll_setup(struct device_node *np)
* PLL0 HS (high speed) output
*/
clk_data->clks[0] = clkgen_pll_register(parent_name,
- &st_pll1600c65_ax,
- reg + CLKGENAx_PLL0_OFFSET,
- clk_name);
+ (struct clkgen_pll_data *) &st_pll1600c65_ax,
+ reg + CLKGENAx_PLL0_OFFSET, clk_name);
if (IS_ERR(clk_data->clks[0]))
goto err;
@@ -480,9 +479,8 @@ static void __init clkgena_c65_pll_setup(struct device_node *np)
* PLL1 output
*/
clk_data->clks[2] = clkgen_pll_register(parent_name,
- &st_pll800c65_ax,
- reg + CLKGENAx_PLL1_OFFSET,
- clk_name);
+ (struct clkgen_pll_data *) &st_pll800c65_ax,
+ reg + CLKGENAx_PLL1_OFFSET, clk_name);
if (IS_ERR(clk_data->clks[2]))
goto err;
--
1.9.1
next prev parent reply other threads:[~2014-07-15 15:20 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-15 15:20 [PATCH v3 00/15] Add Flexgen Clock support Gabriel FERNANDEZ
2014-07-15 15:20 ` [PATCH v3 01/15] clk: st: Update ST clock binding documentation Gabriel FERNANDEZ
2014-07-15 15:20 ` [PATCH v3 02/15] drivers: clk: st: use static const for stm_fs tables Gabriel FERNANDEZ
2014-07-15 15:20 ` Gabriel FERNANDEZ [this message]
2014-07-15 15:20 ` [PATCH v3 04/15] drivers: clk: st: Remove uncessary (void *) cast Gabriel FERNANDEZ
2014-07-15 15:20 ` [PATCH v3 05/15] clk: st: Adds Flexgen clock binding Gabriel FERNANDEZ
2014-07-15 15:20 ` [PATCH v3 06/15] drivers: clk: st: STiH407: Support for Flexgen Clocks Gabriel FERNANDEZ
2014-07-29 5:31 ` Mike Turquette
2014-08-03 10:58 ` Gabriel Fernandez
2014-07-15 15:20 ` [PATCH v3 07/15] drivers: clk: st: STiH407: Support for A9 MUX Clocks Gabriel FERNANDEZ
2014-07-15 15:20 ` [PATCH v3 08/15] drivers: clk: st: STiH407: Support for clockgenA0 Gabriel FERNANDEZ
[not found] ` <1405437631-23623-1-git-send-email-gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2014-07-15 15:20 ` [PATCH v3 09/15] drivers: clk: st: Add polarity bit indication Gabriel FERNANDEZ
2014-07-15 15:20 ` [PATCH v3 10/15] drivers: clk: st: Add quadfs reset handling Gabriel FERNANDEZ
2014-07-15 15:20 ` [PATCH v3 11/15] drivers: clk: st: STiH407: Support for clockgenC0 Gabriel FERNANDEZ
2014-07-15 15:20 ` [PATCH v3 12/15] drivers: clk: st: STiH407: Support for clockgenD0/D2/D3 Gabriel FERNANDEZ
2014-07-15 15:20 ` [PATCH v3 13/15] drivers: clk: st: STiH407: Support for clockgenA9 Gabriel FERNANDEZ
2014-07-15 15:20 ` [PATCH v3 14/15] drivers: clk: st: Update frequency tables for fs660c32 and fs432c65 Gabriel FERNANDEZ
2014-07-15 15:20 ` [PATCH v3 15/15] drivers: clk: st: Use round to closest divider flag Gabriel FERNANDEZ
2014-07-29 5:44 ` [PATCH v3 00/15] Add Flexgen Clock support Mike Turquette
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