From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [PATCH v2 11/11] ARM: dts: zynq: Add AXI clkgen for Parallella Date: Fri, 25 Jul 2014 01:00:20 +0200 Message-ID: <1406242820-20140-12-git-send-email-afaerber@suse.de> References: <1406242820-20140-1-git-send-email-afaerber@suse.de> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <1406242820-20140-1-git-send-email-afaerber@suse.de> Sender: linux-kernel-owner@vger.kernel.org To: Michal Simek Cc: Andreas Olofsson , Matteo Vit , Sean Rickerd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King List-Id: devicetree@vger.kernel.org Signed-off-by: Andreas F=C3=A4rber --- v2: New =20 arch/arm/boot/dts/zynq-parallella.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/= zynq-parallella.dts index 65fbd8b..d2eefad 100644 --- a/arch/arm/boot/dts/zynq-parallella.dts +++ b/arch/arm/boot/dts/zynq-parallella.dts @@ -57,6 +57,13 @@ }; }; =20 + axi_clkgen: axi-clkgen@66000000 { + compatible =3D "adi,axi-clkgen-1.00.a"; + reg =3D <0x66000000 0x10000>; + #clock-cells =3D <0>; + clocks =3D <&clkc 17>; + }; + audio_clock: audio-clock { compatible =3D "fixed-clock"; #clock-cells =3D <0>; --=20 1.9.3