[PATCH v2 00/11] ARM: dts: zynq: Prepare Parallella

[PATCH v2 00/11] ARM: dts: zynq: Prepare Parallella

[Andreas Färber]

Hello,

This patch series adds an initial device tree for the Parallella board.
UART, SD card, Ethernet are enabled.
Not yet enabled are HDMI, QSPI flash and 2x USB.

v2 adds some SPI and FPGA pieces and tidies the device tree with a 
compatible string and matching documentation.

Not having all pieces for testing all of this (most notably I'm missing 
ADI ADV7513 and AXI-HDMI support for VDMA and axi-clkgen, as well as 
the 25Q128A flash chip for QSPI), I've kept new things in separate patches
so that we can make progress on the basic version and possibly squash
further cherry-picked pieces.

Punnaiah Choudary Kalluri had recently proposed to extend the Chipidea 
USB driver for Zynq; it kept complaining about the PHY though, and I 
haven't spotted a revised version based on the generic driver yet.
https://patchwork.kernel.org/patch/4434681/

My rebasing work branch is here:
https://github.com/afaerber/linux/commits/parallella-next

Regards,
Andreas

Cc: Punnaiah Choudary Kalluri <punnaia-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org> (USB)
Cc: Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org> (HDMI)

Andreas Färber (11):
  Documentation: devicetree: Adapteva vendor prefix
  Documentation: devicetree: Adapteva boards
  ARM: dts: zynq: Add Parallella device tree
  ARM: dts: zynq: Update deprecated xuartps clock names
  ARM: dts: zynq: Add QSPI for Parallella
  ARM: dts: zynq: Add DMAC for Parallella
  Documentation: devicetree: Fix Xilinx VDMA specification
  ARM: dts: zynq: Add VDMA to Parallella
  Documentation: devicetree: Fix ADI AXI SPDIF specification
  ARM: dts: zynq: Add SPDIF for Parallella
  ARM: dts: zynq: Add AXI clkgen for Parallella

 Documentation/devicetree/bindings/arm/adapteva.txt |   7 ++
 .../devicetree/bindings/dma/xilinx/xilinx_vdma.txt |   2 +-
 .../devicetree/bindings/sound/adi,axi-spdif-tx.txt |   2 +-
 .../devicetree/bindings/vendor-prefixes.txt        |   1 +
 arch/arm/boot/dts/Makefile                         |   4 +-
 arch/arm/boot/dts/zynq-7000.dtsi                   |  58 +++++++++-
 arch/arm/boot/dts/zynq-parallella.dts              | 119 +++++++++++++++++++++
 7 files changed, 188 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/adapteva.txt
 create mode 100644 arch/arm/boot/dts/zynq-parallella.dts

-- 
1.9.3

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[PATCH v2 01/11] Documentation: devicetree: Adapteva vendor prefix

[Andreas Färber]

Cc: Andreas Olofsson <andreas@adapteva.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v2: New
 
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 46a311e..a8708c7 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -6,6 +6,7 @@ using them to avoid name-space collisions.
 abilis	Abilis Systems
 active-semi	Active-Semi International Inc
 ad	Avionic Design GmbH
+adapteva	Adapteva, Inc.
 adi	Analog Devices, Inc.
 aeroflexgaisler	Aeroflex Gaisler AB
 ak	Asahi Kasei Corp.
-- 
1.9.3

Re: [PATCH v2 01/11] Documentation: devicetree: Adapteva vendor prefix

[Michal Simek]

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On 07/25/2014 01:00 AM, Andreas Färber wrote:
> Cc: Andreas Olofsson <andreas-hhg9azYwhpdWk0Htik3J/w@public.gmane.org>
> Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
> ---
>  v2: New
>  
>  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index 46a311e..a8708c7 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -6,6 +6,7 @@ using them to avoid name-space collisions.
>  abilis	Abilis Systems
>  active-semi	Active-Semi International Inc
>  ad	Avionic Design GmbH
> +adapteva	Adapteva, Inc.
>  adi	Analog Devices, Inc.
>  aeroflexgaisler	Aeroflex Gaisler AB
>  ak	Asahi Kasei Corp.
> 

Applied zynq/dt branch.
https://github.com/Xilinx/linux-xlnx/commits/zynq/dt

Thanks,
Michal


-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform



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[PATCH v2 02/11] Documentation: devicetree: Adapteva boards

[Andreas Färber]

We're about to add a device tree for the Parallella board.

Cc: Andreas Olofsson <andreas@adapteva.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v2: New
 
 Documentation/devicetree/bindings/arm/adapteva.txt | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/adapteva.txt

diff --git a/Documentation/devicetree/bindings/arm/adapteva.txt b/Documentation/devicetree/bindings/arm/adapteva.txt
new file mode 100644
index 0000000..1d8af9e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/adapteva.txt
@@ -0,0 +1,7 @@
+Adapteva Platforms Device Tree Bindings
+---------------------------------------
+
+Parallella board
+
+Required root node properties:
+    - compatible = "adapteva,parallella";
-- 
1.9.3


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Re: [PATCH v2 02/11] Documentation: devicetree: Adapteva boards

[Michal Simek]

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On 07/25/2014 01:00 AM, Andreas Färber wrote:
> We're about to add a device tree for the Parallella board.
> 
> Cc: Andreas Olofsson <andreas-hhg9azYwhpdWk0Htik3J/w@public.gmane.org>
> Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
> ---
>  v2: New
>  
>  Documentation/devicetree/bindings/arm/adapteva.txt | 7 +++++++
>  1 file changed, 7 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/adapteva.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/adapteva.txt b/Documentation/devicetree/bindings/arm/adapteva.txt
> new file mode 100644
> index 0000000..1d8af9e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/adapteva.txt
> @@ -0,0 +1,7 @@
> +Adapteva Platforms Device Tree Bindings
> +---------------------------------------
> +
> +Parallella board
> +
> +Required root node properties:
> +    - compatible = "adapteva,parallella";
> 


Applied to zynq/dt branch.
https://github.com/Xilinx/linux-xlnx/commits/zynq/dt

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform



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[PATCH v2 03/11] ARM: dts: zynq: Add Parallella device tree

[Andreas Färber]

This allows to boot the Adapteva Parallella board to serial console.

Cc: Andreas Olofsson <andreas@adapteva.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v1 -> v2:
 * Added board-specific compatible string (Olof Johansson).
 * Added /chosen linux,stdout-path property (Olof Johansson).
 * Fixed /memory reg size 0x20000000 -> 0x40000000 (0 considered).
 * Added vendor name to root node's model property (Olof Johansson).
 
 arch/arm/boot/dts/Makefile            |  4 ++-
 arch/arm/boot/dts/zynq-parallella.dts | 64 +++++++++++++++++++++++++++++++++++
 2 files changed, 67 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/zynq-parallella.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index adb5ed9..976720f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -419,7 +419,9 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
 	wm8650-mid.dtb \
 	wm8750-apc8750.dtb \
 	wm8850-w70v2.dtb
-dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
+dtb-$(CONFIG_ARCH_ZYNQ) += \
+	zynq-parallella.dtb \
+	zynq-zc702.dtb \
 	zynq-zc706.dtb \
 	zynq-zed.dtb
 dtb-$(CONFIG_MACH_ARMADA_370) += \
diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
new file mode 100644
index 0000000..41afd9d
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2014 SUSE LINUX Products GmbH
+ *
+ * Derived from zynq-zed.dts:
+ *
+ *  Copyright (C) 2011 Xilinx
+ *  Copyright (C) 2012 National Instruments Corp.
+ *  Copyright (C) 2013 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+	model = "Adapteva Parallella Board";
+	compatible = "adapteva,parallella", "xlnx,zynq-7000";
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x40000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
+		linux,stdout-path = "/amba/serial@e0001000";
+	};
+};
+
+&gem0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	ethernet_phy: ethernet-phy@0 {
+		/* Marvell 88E1318 */
+		compatible = "ethernet-phy-id0141.0e90",
+		             "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+		marvell,reg-init = <0x3 0x10 0xff00 0x1e>,
+		                   <0x3 0x11 0xfff0 0xa>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&sdhci1 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
-- 
1.9.3

Re: [PATCH v2 03/11] ARM: dts: zynq: Add Parallella device tree

[Michal Simek]

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On 07/25/2014 01:00 AM, Andreas Färber wrote:
> This allows to boot the Adapteva Parallella board to serial console.
> 
> Cc: Andreas Olofsson <andreas@adapteva.com>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
>  v1 -> v2:
>  * Added board-specific compatible string (Olof Johansson).
>  * Added /chosen linux,stdout-path property (Olof Johansson).
>  * Fixed /memory reg size 0x20000000 -> 0x40000000 (0 considered).
>  * Added vendor name to root node's model property (Olof Johansson).
>  
>  arch/arm/boot/dts/Makefile            |  4 ++-
>  arch/arm/boot/dts/zynq-parallella.dts | 64 +++++++++++++++++++++++++++++++++++
>  2 files changed, 67 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/zynq-parallella.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index adb5ed9..976720f 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -419,7 +419,9 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
>  	wm8650-mid.dtb \
>  	wm8750-apc8750.dtb \
>  	wm8850-w70v2.dtb
> -dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
> +dtb-$(CONFIG_ARCH_ZYNQ) += \
> +	zynq-parallella.dtb \
> +	zynq-zc702.dtb \
>  	zynq-zc706.dtb \
>  	zynq-zed.dtb
>  dtb-$(CONFIG_MACH_ARMADA_370) += \
> diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
> new file mode 100644
> index 0000000..41afd9d
> --- /dev/null
> +++ b/arch/arm/boot/dts/zynq-parallella.dts
> @@ -0,0 +1,64 @@
> +/*
> + * Copyright (c) 2014 SUSE LINUX Products GmbH
> + *
> + * Derived from zynq-zed.dts:
> + *
> + *  Copyright (C) 2011 Xilinx
> + *  Copyright (C) 2012 National Instruments Corp.
> + *  Copyright (C) 2013 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +/dts-v1/;
> +/include/ "zynq-7000.dtsi"
> +
> +/ {
> +	model = "Adapteva Parallella Board";
> +	compatible = "adapteva,parallella", "xlnx,zynq-7000";
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0 0x40000000>;
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
> +		linux,stdout-path = "/amba/serial@e0001000";
> +	};
> +};
> +
> +&gem0 {
> +	status = "okay";
> +	phy-mode = "rgmii-id";
> +	phy-handle = <&ethernet_phy>;
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	ethernet_phy: ethernet-phy@0 {
> +		/* Marvell 88E1318 */
> +		compatible = "ethernet-phy-id0141.0e90",
> +		             "ethernet-phy-ieee802.3-c22";
> +		reg = <0>;
> +		marvell,reg-init = <0x3 0x10 0xff00 0x1e>,
> +		                   <0x3 0x11 0xfff0 0xa>;
> +	};
> +};
> +
> +&i2c0 {
> +	status = "okay";
> +};
> +
> +&sdhci1 {
> +	status = "okay";
> +};
> +
> +&uart1 {
> +	status = "okay";
> +};
> 


Applied to zynq/dt branch.
https://github.com/Xilinx/linux-xlnx/commits/zynq/dt

Thanks,
Michal


-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform



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[PATCH v2 04/11] ARM: dts: zynq: Update deprecated xuartps clock names

[Andreas Färber]

Avoids deprecation warning messages.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v2: New
 
 arch/arm/boot/dts/zynq-7000.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 760bbc4..8fd826a 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -108,7 +108,7 @@
 			compatible = "xlnx,xuartps";
 			status = "disabled";
 			clocks = <&clkc 23>, <&clkc 40>;
-			clock-names = "ref_clk", "aper_clk";
+			clock-names = "uart_clk", "pclk";
 			reg = <0xE0000000 0x1000>;
 			interrupts = <0 27 4>;
 		};
@@ -117,7 +117,7 @@
 			compatible = "xlnx,xuartps";
 			status = "disabled";
 			clocks = <&clkc 24>, <&clkc 41>;
-			clock-names = "ref_clk", "aper_clk";
+			clock-names = "uart_clk", "pclk";
 			reg = <0xE0001000 0x1000>;
 			interrupts = <0 50 4>;
 		};
-- 
1.9.3


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Re: [PATCH v2 04/11] ARM: dts: zynq: Update deprecated xuartps clock names

[Sören Brinkmann]

On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
> Avoids deprecation warning messages.

A patch that updates those names is already in armsoc.

	Sören

Re: [PATCH v2 04/11] ARM: dts: zynq: Update deprecated xuartps clock names

[Andreas Färber]

Am 25.07.2014 01:09, schrieb Sören Brinkmann:
> On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
>> Avoids deprecation warning messages.
> 
> A patch that updates those names is already in armsoc.

Which tree/branch should I base this series on then? It seemed the
Xilinx branches were all heavily outdated some days ago, so this is
against vanilla v3.16-rc6.

Thanks,
Andreas

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Re: [PATCH v2 04/11] ARM: dts: zynq: Update deprecated xuartps clock names

[Sören Brinkmann]

On Fri, 2014-07-25 at 01:13AM +0200, Andreas Färber wrote:
> Am 25.07.2014 01:09, schrieb Sören Brinkmann:
> > On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
> >> Avoids deprecation warning messages.
> > 
> > A patch that updates those names is already in armsoc.
> 
> Which tree/branch should I base this series on then? It seemed the
> Xilinx branches were all heavily outdated some days ago, so this is
> against vanilla v3.16-rc6.

That is something for the maintainers to answer. But in general, you're
adding a lot of stuff that is not yet upstream, AFAIK. Some is still
under review I think (like QSPI), others are just staged for the next
merge window and parts are still in flight. Michal hopefully has a
better overview.
This particular patch can simply be omitted I think.

	Sören

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Re: [PATCH v2 04/11] ARM: dts: zynq: Update deprecated xuartps clock names

[Michal Simek]

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On 07/25/2014 01:24 AM, Sören Brinkmann wrote:
> On Fri, 2014-07-25 at 01:13AM +0200, Andreas Färber wrote:
>> Am 25.07.2014 01:09, schrieb Sören Brinkmann:
>>> On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
>>>> Avoids deprecation warning messages.
>>>
>>> A patch that updates those names is already in armsoc.
>>
>> Which tree/branch should I base this series on then? It seemed the
>> Xilinx branches were all heavily outdated some days ago, so this is
>> against vanilla v3.16-rc6.

I have updated that branches. From my experience none is looking
at these branches and I mainly use them for communication
with arm-soc where sign tags are used which you can see them there.

> 
> That is something for the maintainers to answer. But in general, you're
> adding a lot of stuff that is not yet upstream, AFAIK. Some is still
> under review I think (like QSPI), others are just staged for the next
> merge window and parts are still in flight. Michal hopefully has a
> better overview.
> This particular patch can simply be omitted I think.

There are several options and I think the best is arm-soc tree
where you can see what have been accepted.
And also I believe all arm-soc trees are added to linux-next.

That's why I would use linux-next or arm-soc.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform



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[PATCH v2 05/11] ARM: dts: zynq: Add QSPI for Parallella

[Andreas Färber]

Prepare SPI0 and SPI1 while at it.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v2: New
 
 arch/arm/boot/dts/zynq-7000.dtsi      | 37 +++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/zynq-parallella.dts |  4 ++++
 2 files changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 8fd826a..eed3df0 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -122,6 +122,30 @@
 			interrupts = <0 50 4>;
 		};
 
+		spi0: spi@e0006000 {
+			compatible = "xlnx,zynq-spi-r1p6";
+			reg = <0xe0006000 0x1000>;
+			status = "disabled";
+			interrupt-parent = <&intc>;
+			interrupts = <0 26 4>;
+			clocks = <&clkc 25>, <&clkc 34>;
+			clock-names = "ref_clk", "pclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi@e0007000 {
+			compatible = "xlnx,zynq-spi-r1p6";
+			reg = <0xe0007000 0x1000>;
+			status = "disabled";
+			interrupt-parent = <&intc>;
+			interrupts = <0 49 4>;
+			clocks = <&clkc 26>, <&clkc 35>;
+			clock-names = "ref_clk", "pclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		gem0: ethernet@e000b000 {
 			compatible = "cdns,gem";
 			reg = <0xe000b000 0x4000>;
@@ -140,6 +164,19 @@
 			clock-names = "pclk", "hclk", "tx_clk";
 		};
 
+		qspi: qspi@e000d000 {
+			compatible = "xlnx,zynq-spi-r1p6";
+			reg = <0xe000d000 0x1000>;
+			status = "disabled";
+			interrupt-parent = <&intc>;
+			interrupts = <0 19 4>;
+			clocks = <&clkc 10>, <&clkc 43>;
+			clock-names = "ref_clk", "pclk";
+			num-cs = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		sdhci0: sdhci@e0100000 {
 			compatible = "arasan,sdhci-8.9a";
 			status = "disabled";
diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index 41afd9d..56f68ea 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -55,6 +55,10 @@
 	status = "okay";
 };
 
+&qspi {
+	status = "okay";
+};
+
 &sdhci1 {
 	status = "okay";
 };
-- 
1.9.3


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Re: [PATCH v2 05/11] ARM: dts: zynq: Add QSPI for Parallella

[Sören Brinkmann]

On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
> Prepare SPI0 and SPI1 while at it.
> 
> Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
> ---
>  v2: New
>  
>  arch/arm/boot/dts/zynq-7000.dtsi      | 37 +++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/zynq-parallella.dts |  4 ++++
>  2 files changed, 41 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
> index 8fd826a..eed3df0 100644
> --- a/arch/arm/boot/dts/zynq-7000.dtsi
> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
> @@ -122,6 +122,30 @@
>  			interrupts = <0 50 4>;
>  		};
>  
> +		spi0: spi@e0006000 {
> +			compatible = "xlnx,zynq-spi-r1p6";
> +			reg = <0xe0006000 0x1000>;
> +			status = "disabled";
> +			interrupt-parent = <&intc>;
> +			interrupts = <0 26 4>;
> +			clocks = <&clkc 25>, <&clkc 34>;
> +			clock-names = "ref_clk", "pclk";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		spi1: spi@e0007000 {
> +			compatible = "xlnx,zynq-spi-r1p6";
> +			reg = <0xe0007000 0x1000>;
> +			status = "disabled";
> +			interrupt-parent = <&intc>;
> +			interrupts = <0 49 4>;
> +			clocks = <&clkc 26>, <&clkc 35>;
> +			clock-names = "ref_clk", "pclk";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
Until here things look good.

>  		gem0: ethernet@e000b000 {
>  			compatible = "cdns,gem";
>  			reg = <0xe000b000 0x4000>;
> @@ -140,6 +164,19 @@
>  			clock-names = "pclk", "hclk", "tx_clk";
>  		};
>  
> +		qspi: qspi@e000d000 {
> +			compatible = "xlnx,zynq-spi-r1p6";
> +			reg = <0xe000d000 0x1000>;
> +			status = "disabled";
> +			interrupt-parent = <&intc>;
> +			interrupts = <0 19 4>;
> +			clocks = <&clkc 10>, <&clkc 43>;
> +			clock-names = "ref_clk", "pclk";
> +			num-cs = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
I'm not sure what the status of this driver is. I think QSPI is still
under review on the mailing lists and I don't think we should add this
yet.

	Sören

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Re: [PATCH v2 05/11] ARM: dts: zynq: Add QSPI for Parallella

[Michal Simek]

[-- Attachment #1: Type: text/plain, Size: 3018 bytes --]

On 07/25/2014 01:18 AM, Sören Brinkmann wrote:
> On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
>> Prepare SPI0 and SPI1 while at it.

Patch subject is incorrect. You are adding SPI and QSPI.

>>
>> Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
>> ---
>>  v2: New
>>  
>>  arch/arm/boot/dts/zynq-7000.dtsi      | 37 +++++++++++++++++++++++++++++++++++
>>  arch/arm/boot/dts/zynq-parallella.dts |  4 ++++
>>  2 files changed, 41 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
>> index 8fd826a..eed3df0 100644
>> --- a/arch/arm/boot/dts/zynq-7000.dtsi
>> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
>> @@ -122,6 +122,30 @@
>>  			interrupts = <0 50 4>;
>>  		};
>>  
>> +		spi0: spi@e0006000 {
>> +			compatible = "xlnx,zynq-spi-r1p6";
>> +			reg = <0xe0006000 0x1000>;
>> +			status = "disabled";
>> +			interrupt-parent = <&intc>;
>> +			interrupts = <0 26 4>;
>> +			clocks = <&clkc 25>, <&clkc 34>;
>> +			clock-names = "ref_clk", "pclk";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		spi1: spi@e0007000 {
>> +			compatible = "xlnx,zynq-spi-r1p6";
>> +			reg = <0xe0007000 0x1000>;
>> +			status = "disabled";
>> +			interrupt-parent = <&intc>;
>> +			interrupts = <0 49 4>;
>> +			clocks = <&clkc 26>, <&clkc 35>;
>> +			clock-names = "ref_clk", "pclk";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
> Until here things look good.
> 
>>  		gem0: ethernet@e000b000 {
>>  			compatible = "cdns,gem";
>>  			reg = <0xe000b000 0x4000>;
>> @@ -140,6 +164,19 @@
>>  			clock-names = "pclk", "hclk", "tx_clk";
>>  		};
>>  
>> +		qspi: qspi@e000d000 {
>> +			compatible = "xlnx,zynq-spi-r1p6";
>> +			reg = <0xe000d000 0x1000>;
>> +			status = "disabled";
>> +			interrupt-parent = <&intc>;
>> +			interrupts = <0 19 4>;
>> +			clocks = <&clkc 10>, <&clkc 43>;
>> +			clock-names = "ref_clk", "pclk";
>> +			num-cs = <1>;
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
> I'm not sure what the status of this driver is. I think QSPI is still
> under review on the mailing lists and I don't think we should add this
> yet.

Driver for qspi is not in the mainline yet but it doesn't mean
that this fragment won't work.
Harini: Can you please correct me if I am wrong?

I would prefer to send two separate patches.

1. just add SPI to zynq
2. if Harini confirms that it is working I think that make sense to enable
at least simple mode for qspi. That's why not a problem to add it too.
It means qspi patch with enabling for your board as second patch.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform



[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 263 bytes --]

Re: [PATCH v2 05/11] ARM: dts: zynq: Add QSPI for Parallella

[Andreas Färber]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Am 25.07.2014 09:59, schrieb Michal Simek:
> On 07/25/2014 01:18 AM, Sören Brinkmann wrote:
>> On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
>>> Prepare SPI0 and SPI1 while at it.
> 
> Patch subject is incorrect. You are adding SPI and QSPI.

Yes, it originally added only QSPI, but I considered it a good deed to
add SPI as well while already reading that part of the TRM. :)

>>> 
>>> Signed-off-by: Andreas Färber <afaerber@suse.de> --- v2: New
>>> 
>>> arch/arm/boot/dts/zynq-7000.dtsi      | 37
>>> +++++++++++++++++++++++++++++++++++ 
>>> arch/arm/boot/dts/zynq-parallella.dts |  4 ++++ 2 files
>>> changed, 41 insertions(+)
>>> 
>>> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
>>> b/arch/arm/boot/dts/zynq-7000.dtsi index 8fd826a..eed3df0
>>> 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++
>>> b/arch/arm/boot/dts/zynq-7000.dtsi @@ -122,6 +122,30 @@ 
>>> interrupts = <0 50 4>; };
>>> 
>>> +		spi0: spi@e0006000 { +			compatible = "xlnx,zynq-spi-r1p6"; 
>>> +			reg = <0xe0006000 0x1000>; +			status = "disabled"; +
>>> interrupt-parent = <&intc>; +			interrupts = <0 26 4>; +
>>> clocks = <&clkc 25>, <&clkc 34>; +			clock-names = "ref_clk",
>>> "pclk"; +			#address-cells = <1>; +			#size-cells = <0>; +		}; 
>>> + +		spi1: spi@e0007000 { +			compatible =
>>> "xlnx,zynq-spi-r1p6"; +			reg = <0xe0007000 0x1000>; +			status
>>> = "disabled"; +			interrupt-parent = <&intc>; +			interrupts =
>>> <0 49 4>; +			clocks = <&clkc 26>, <&clkc 35>; +			clock-names
>>> = "ref_clk", "pclk"; +			#address-cells = <1>; +			#size-cells
>>> = <0>; +		}; +
>> Until here things look good.
>> 
>>> gem0: ethernet@e000b000 { compatible = "cdns,gem"; reg =
>>> <0xe000b000 0x4000>; @@ -140,6 +164,19 @@ clock-names = "pclk",
>>> "hclk", "tx_clk"; };
>>> 
>>> +		qspi: qspi@e000d000 { +			compatible =
>>> "xlnx,zynq-spi-r1p6"; +			reg = <0xe000d000 0x1000>; +			status
>>> = "disabled"; +			interrupt-parent = <&intc>; +			interrupts =
>>> <0 19 4>; +			clocks = <&clkc 10>, <&clkc 43>; +			clock-names
>>> = "ref_clk", "pclk"; +			num-cs = <1>; +			#address-cells =
>>> <1>; +			#size-cells = <0>; +		}; +
>> I'm not sure what the status of this driver is. I think QSPI is
>> still under review on the mailing lists and I don't think we
>> should add this yet.
> 
> Driver for qspi is not in the mainline yet but it doesn't mean that
> this fragment won't work. Harini: Can you please correct me if I am
> wrong?

It did seem to find the flash chip (cf. parallella-next branch), but I
didn't find a driver capable of handling its ID. The downstream tree
was using m25p80; I tried both micron,n25q128a11 and ...a13 based on
U-Boot output.

> I would prefer to send two separate patches.

Will do.

> 1. just add SPI to zynq

As I don't have any of the other Zynq boards, can you please advise
whether either of them should be enabled for some board?

> 2. if Harini confirms that it is working I think that make sense to
> enable at least simple mode for qspi. That's why not a problem to
> add it too. It means qspi patch with enabling for your board as
> second patch.

Thanks,
Andreas

- -- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
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Re: [PATCH v2 05/11] ARM: dts: zynq: Add QSPI for Parallella

[Michal Simek]

[-- Attachment #1.1: Type: text/plain, Size: 3211 bytes --]

On 07/25/2014 10:42 AM, Andreas Färber wrote:
> Am 25.07.2014 09:59, schrieb Michal Simek:
>> On 07/25/2014 01:18 AM, Sören Brinkmann wrote:
>>> On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
>>>> Prepare SPI0 and SPI1 while at it.
> 
>> Patch subject is incorrect. You are adding SPI and QSPI.
> 
> Yes, it originally added only QSPI, but I considered it a good deed to
> add SPI as well while already reading that part of the TRM. :)
> 
>>>>
>>>> Signed-off-by: Andreas Färber <afaerber@suse.de> --- v2: New
>>>>
>>>> arch/arm/boot/dts/zynq-7000.dtsi      | 37
>>>> +++++++++++++++++++++++++++++++++++ 
>>>> arch/arm/boot/dts/zynq-parallella.dts |  4 ++++ 2 files
>>>> changed, 41 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
>>>> b/arch/arm/boot/dts/zynq-7000.dtsi index 8fd826a..eed3df0
>>>> 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++
>>>> b/arch/arm/boot/dts/zynq-7000.dtsi @@ -122,6 +122,30 @@ 
>>>> interrupts = <0 50 4>; };
>>>>
>>>> +		spi0: spi@e0006000 { +			compatible = "xlnx,zynq-spi-r1p6"; 
>>>> +			reg = <0xe0006000 0x1000>; +			status = "disabled"; +
>>>> interrupt-parent = <&intc>; +			interrupts = <0 26 4>; +
>>>> clocks = <&clkc 25>, <&clkc 34>; +			clock-names = "ref_clk",
>>>> "pclk"; +			#address-cells = <1>; +			#size-cells = <0>; +		}; 
>>>> + +		spi1: spi@e0007000 { +			compatible =
>>>> "xlnx,zynq-spi-r1p6"; +			reg = <0xe0007000 0x1000>; +			status
>>>> = "disabled"; +			interrupt-parent = <&intc>; +			interrupts =
>>>> <0 49 4>; +			clocks = <&clkc 26>, <&clkc 35>; +			clock-names
>>>> = "ref_clk", "pclk"; +			#address-cells = <1>; +			#size-cells
>>>> = <0>; +		}; +
>>> Until here things look good.
>>>
>>>> gem0: ethernet@e000b000 { compatible = "cdns,gem"; reg =
>>>> <0xe000b000 0x4000>; @@ -140,6 +164,19 @@ clock-names = "pclk",
>>>> "hclk", "tx_clk"; };
>>>>
>>>> +		qspi: qspi@e000d000 { +			compatible =
>>>> "xlnx,zynq-spi-r1p6"; +			reg = <0xe000d000 0x1000>; +			status
>>>> = "disabled"; +			interrupt-parent = <&intc>; +			interrupts =
>>>> <0 19 4>; +			clocks = <&clkc 10>, <&clkc 43>; +			clock-names
>>>> = "ref_clk", "pclk"; +			num-cs = <1>; +			#address-cells =
>>>> <1>; +			#size-cells = <0>; +		}; +
>>> I'm not sure what the status of this driver is. I think QSPI is
>>> still under review on the mailing lists and I don't think we
>>> should add this yet.
> 
>> Driver for qspi is not in the mainline yet but it doesn't mean that
>> this fragment won't work. Harini: Can you please correct me if I am
>> wrong?
> 
> It did seem to find the flash chip (cf. parallella-next branch), but I
> didn't find a driver capable of handling its ID. The downstream tree
> was using m25p80; I tried both micron,n25q128a11 and ...a13 based on
> U-Boot output.
> 
>> I would prefer to send two separate patches.
> 
> Will do.
> 
>> 1. just add SPI to zynq
> 
> As I don't have any of the other Zynq boards, can you please advise
> whether either of them should be enabled for some board?

we don't have them enabled for any board in default configuration
that's why just adding nodes with status = "disabled" is fine.

Thanks,
Michal


[-- Attachment #1.2: OpenPGP digital signature --]
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[PATCH v3] ARM: dts: zynq: Add SPI

[Andreas Färber]

Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
---
 v3: Split off from QSPI (Michal Simek).
 
 arch/arm/boot/dts/zynq-7000.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index cf0f3e4..ef11dab 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -140,6 +140,30 @@
 			interrupts = <0 50 4>;
 		};
 
+		spi0: spi@e0006000 {
+			compatible = "xlnx,zynq-spi-r1p6";
+			reg = <0xe0006000 0x1000>;
+			status = "disabled";
+			interrupt-parent = <&intc>;
+			interrupts = <0 26 4>;
+			clocks = <&clkc 25>, <&clkc 34>;
+			clock-names = "ref_clk", "pclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi@e0007000 {
+			compatible = "xlnx,zynq-spi-r1p6";
+			reg = <0xe0007000 0x1000>;
+			status = "disabled";
+			interrupt-parent = <&intc>;
+			interrupts = <0 49 4>;
+			clocks = <&clkc 26>, <&clkc 35>;
+			clock-names = "ref_clk", "pclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		gem0: ethernet@e000b000 {
 			compatible = "cdns,gem";
 			reg = <0xe000b000 0x4000>;
-- 
1.9.3

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Re: [PATCH v3] ARM: dts: zynq: Add SPI

[Sören Brinkmann]

On Fri, 2014-07-25 at 01:12PM +0200, Andreas Färber wrote:
> Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
Reviewed-by: Soren Brinkmann <soren.brinkmann-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>

	Sören

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Re: [PATCH v3] ARM: dts: zynq: Add SPI

[Michal Simek]

On 07/25/2014 04:42 PM, Sören Brinkmann wrote:
> On Fri, 2014-07-25 at 01:12PM +0200, Andreas Färber wrote:
>> Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
> Reviewed-by: Soren Brinkmann <soren.brinkmann-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>

Applied to zynq/dt.

Thanks,
Michal


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RE: [PATCH v2 05/11] ARM: dts: zynq: Add QSPI for Parallella

[Harini Katakam]

Hi,

> -----Original Message-----
> From: Michal Simek [mailto:michal.simek@xilinx.com]
> Sent: Friday, July 25, 2014 3:08 PM
> To: Andreas Färber; monstr@monstr.eu; Soren Brinkmann
> Cc: Harini Katakam; Michal Simek; Andreas Olofsson; Matteo Vit; Sean
> Rickerd; devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; Rob Herring; Pawel Moll; Mark Rutland; Ian
> Campbell; Kumar Gala; Russell King
> Subject: Re: [PATCH v2 05/11] ARM: dts: zynq: Add QSPI for Parallella
> 
> On 07/25/2014 10:42 AM, Andreas Färber wrote:
> > Am 25.07.2014 09:59, schrieb Michal Simek:
> >> On 07/25/2014 01:18 AM, Sören Brinkmann wrote:
> >>> On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
> >>>> Prepare SPI0 and SPI1 while at it.
> >
> >> Patch subject is incorrect. You are adding SPI and QSPI.
> >
> > Yes, it originally added only QSPI, but I considered it a good deed to
> > add SPI as well while already reading that part of the TRM. :)
> >
> >>>>
> >>>> Signed-off-by: Andreas Färber <afaerber@suse.de> --- v2: New
> >>>>
> >>>> arch/arm/boot/dts/zynq-7000.dtsi      | 37
> >>>> +++++++++++++++++++++++++++++++++++
> >>>> arch/arm/boot/dts/zynq-parallella.dts |  4 ++++ 2 files
> >>>> changed, 41 insertions(+)
> >>>>
> >>>> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
> >>>> b/arch/arm/boot/dts/zynq-7000.dtsi index 8fd826a..eed3df0
> >>>> 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++
> >>>> b/arch/arm/boot/dts/zynq-7000.dtsi @@ -122,6 +122,30 @@
> >>>> interrupts = <0 50 4>; };
> >>>>
> >>>> +		spi0: spi@e0006000 { +			compatible =
> "xlnx,zynq-spi-r1p6";
> >>>> +			reg = <0xe0006000 0x1000>; +			status
> = "disabled"; +
> >>>> interrupt-parent = <&intc>; +			interrupts = <0 26 4>;
> +
> >>>> clocks = <&clkc 25>, <&clkc 34>; +			clock-names =
> "ref_clk",
> >>>> "pclk"; +			#address-cells = <1>; +			#size-
> cells = <0>; +		};
> >>>> + +		spi1: spi@e0007000 { +			compatible =
> >>>> "xlnx,zynq-spi-r1p6"; +			reg = <0xe0007000 0x1000>; +
> 			status
> >>>> = "disabled"; +			interrupt-parent = <&intc>; +
> 		interrupts =
> >>>> <0 49 4>; +			clocks = <&clkc 26>, <&clkc 35>; +
> 		clock-names
> >>>> = "ref_clk", "pclk"; +			#address-cells = <1>; +
> 		#size-cells
> >>>> = <0>; +		}; +
> >>> Until here things look good.
> >>>
> >>>> gem0: ethernet@e000b000 { compatible = "cdns,gem"; reg =
> >>>> <0xe000b000 0x4000>; @@ -140,6 +164,19 @@ clock-names = "pclk",
> >>>> "hclk", "tx_clk"; };
> >>>>
> >>>> +		qspi: qspi@e000d000 { +			compatible =
> >>>> "xlnx,zynq-spi-r1p6"; +			reg = <0xe000d000 0x1000>; +
> 			status
> >>>> = "disabled"; +			interrupt-parent = <&intc>; +
> 		interrupts =
> >>>> <0 19 4>; +			clocks = <&clkc 10>, <&clkc 43>; +
> 		clock-names
> >>>> = "ref_clk", "pclk"; +			num-cs = <1>; +
> 	#address-cells =
> >>>> <1>; +			#size-cells = <0>; +		}; +
> >>> I'm not sure what the status of this driver is. I think QSPI is
> >>> still under review on the mailing lists and I don't think we
> >>> should add this yet.
> >
> >> Driver for qspi is not in the mainline yet but it doesn't mean that
> >> this fragment won't work. Harini: Can you please correct me if I am
> >> wrong?
> >

It can be added but it will have to be disabled as there is no qspi driver
at the moment in mainline.

Regards,
Harini

Re: [PATCH v2 05/11] ARM: dts: zynq: Add QSPI for Parallella

[Andreas Färber]

Hi Harini,

Am 25.07.2014 12:31, schrieb Harini Katakam:
>> -----Original Message-----
>> From: Michal Simek [mailto:michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org]
>> Sent: Friday, July 25, 2014 3:08 PM
>> To: Andreas Färber; monstr-pSz03upnqPeHXe+LvDLADg@public.gmane.org; Soren Brinkmann
>> Cc: Harini Katakam; Michal Simek; Andreas Olofsson; Matteo Vit; Sean
>> Rickerd; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-kernel-IAPFreCvJWM9gwCICpdfJQ@public.gmane.orgd.org;
>> linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Rob Herring; Pawel Moll; Mark Rutland; Ian
>> Campbell; Kumar Gala; Russell King
>> Subject: Re: [PATCH v2 05/11] ARM: dts: zynq: Add QSPI for Parallella
>>
>> On 07/25/2014 10:42 AM, Andreas Färber wrote:
>>> Am 25.07.2014 09:59, schrieb Michal Simek:
>>>> On 07/25/2014 01:18 AM, Sören Brinkmann wrote:
>>>>> On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
>>>>>> Prepare SPI0 and SPI1 while at it.
>>>
>>>> Patch subject is incorrect. You are adding SPI and QSPI.
>>>
>>> Yes, it originally added only QSPI, but I considered it a good deed to
>>> add SPI as well while already reading that part of the TRM. :)
>>>
>>>>>>
>>>>>> Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org> --- v2: New
>>>>>>
>>>>>> arch/arm/boot/dts/zynq-7000.dtsi      | 37
>>>>>> +++++++++++++++++++++++++++++++++++
>>>>>> arch/arm/boot/dts/zynq-parallella.dts |  4 ++++ 2 files
>>>>>> changed, 41 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
>>>>>> b/arch/arm/boot/dts/zynq-7000.dtsi index 8fd826a..eed3df0
>>>>>> 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++
>>>>>> b/arch/arm/boot/dts/zynq-7000.dtsi @@ -122,6 +122,30 @@
>>>>>> interrupts = <0 50 4>; };
>>>>>>
>>>>>> +		spi0: spi@e0006000 { +			compatible =
>> "xlnx,zynq-spi-r1p6";
>>>>>> +			reg = <0xe0006000 0x1000>; +			status
>> = "disabled"; +
>>>>>> interrupt-parent = <&intc>; +			interrupts = <0 26 4>;
>> +
>>>>>> clocks = <&clkc 25>, <&clkc 34>; +			clock-names =
>> "ref_clk",
>>>>>> "pclk"; +			#address-cells = <1>; +			#size-
>> cells = <0>; +		};
>>>>>> + +		spi1: spi@e0007000 { +			compatible =
>>>>>> "xlnx,zynq-spi-r1p6"; +			reg = <0xe0007000 0x1000>; +
>> 			status
>>>>>> = "disabled"; +			interrupt-parent = <&intc>; +
>> 		interrupts =
>>>>>> <0 49 4>; +			clocks = <&clkc 26>, <&clkc 35>; +
>> 		clock-names
>>>>>> = "ref_clk", "pclk"; +			#address-cells = <1>; +
>> 		#size-cells
>>>>>> = <0>; +		}; +
>>>>> Until here things look good.
>>>>>
>>>>>> gem0: ethernet@e000b000 { compatible = "cdns,gem"; reg =
>>>>>> <0xe000b000 0x4000>; @@ -140,6 +164,19 @@ clock-names = "pclk",
>>>>>> "hclk", "tx_clk"; };
>>>>>>
>>>>>> +		qspi: qspi@e000d000 { +			compatible =
>>>>>> "xlnx,zynq-spi-r1p6"; +			reg = <0xe000d000 0x1000>; +
>> 			status
>>>>>> = "disabled"; +			interrupt-parent = <&intc>; +
>> 		interrupts =
>>>>>> <0 19 4>; +			clocks = <&clkc 10>, <&clkc 43>; +
>> 		clock-names
>>>>>> = "ref_clk", "pclk"; +			num-cs = <1>; +
>> 	#address-cells =
>>>>>> <1>; +			#size-cells = <0>; +		}; +
>>>>> I'm not sure what the status of this driver is. I think QSPI is
>>>>> still under review on the mailing lists and I don't think we
>>>>> should add this yet.
>>>
>>>> Driver for qspi is not in the mainline yet but it doesn't mean that
>>>> this fragment won't work. Harini: Can you please correct me if I am
>>>> wrong?
>>>
> 
> It can be added but it will have to be disabled as there is no qspi driver
> at the moment in mainline.

Did you read the actual patch? It's using the upstream SPI driver for
now, and it's disabled for anything but the new board I'm adding.

https://patchwork.kernel.org/patch/4620201/

Wouldn't a dedicated QSPI driver only result in a compatible string
being prepended before the SPI compatible string?

Andreas

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RE: [PATCH v2 05/11] ARM: dts: zynq: Add QSPI for Parallella

[Harini Katakam]

Hi,

> -----Original Message-----
> From: Harini Katakam
> Sent: Friday, July 25, 2014 4:01 PM
> To: 'Michal Simek'; Andreas Färber; monstr@monstr.eu; Soren Brinkmann
> Cc: Michal Simek; Andreas Olofsson; Matteo Vit; Sean Rickerd;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; Rob Herring; Pawel Moll; Mark Rutland; Ian
> Campbell; Kumar Gala; Russell King
> Subject: RE: [PATCH v2 05/11] ARM: dts: zynq: Add QSPI for Parallella
> 
> Hi,
> 
> > -----Original Message-----
> > From: Michal Simek [mailto:michal.simek@xilinx.com]
> > Sent: Friday, July 25, 2014 3:08 PM
> > To: Andreas Färber; monstr@monstr.eu; Soren Brinkmann
> > Cc: Harini Katakam; Michal Simek; Andreas Olofsson; Matteo Vit; Sean
> > Rickerd; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org;
> > linux-kernel@vger.kernel.org; Rob Herring; Pawel Moll; Mark Rutland; Ian
> > Campbell; Kumar Gala; Russell King
> > Subject: Re: [PATCH v2 05/11] ARM: dts: zynq: Add QSPI for Parallella
> >
> > On 07/25/2014 10:42 AM, Andreas Färber wrote:
> > > Am 25.07.2014 09:59, schrieb Michal Simek:
> > >> On 07/25/2014 01:18 AM, Sören Brinkmann wrote:
> > >>> On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
> > >>>> Prepare SPI0 and SPI1 while at it.
> > >
> > >> Patch subject is incorrect. You are adding SPI and QSPI.
> > >
> > > Yes, it originally added only QSPI, but I considered it a good deed to
> > > add SPI as well while already reading that part of the TRM. :)
> > >
> > >>>>
> > >>>> Signed-off-by: Andreas Färber <afaerber@suse.de> --- v2: New
> > >>>>
> > >>>> arch/arm/boot/dts/zynq-7000.dtsi      | 37
> > >>>> +++++++++++++++++++++++++++++++++++
> > >>>> arch/arm/boot/dts/zynq-parallella.dts |  4 ++++ 2 files
> > >>>> changed, 41 insertions(+)
> > >>>>
> > >>>> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
> > >>>> b/arch/arm/boot/dts/zynq-7000.dtsi index 8fd826a..eed3df0
> > >>>> 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++
> > >>>> b/arch/arm/boot/dts/zynq-7000.dtsi @@ -122,6 +122,30 @@
> > >>>> interrupts = <0 50 4>; };
> > >>>>
> > >>>> +		spi0: spi@e0006000 { +			compatible =
> > "xlnx,zynq-spi-r1p6";
> > >>>> +			reg = <0xe0006000 0x1000>; +
> 	status
> > = "disabled"; +
> > >>>> interrupt-parent = <&intc>; +			interrupts = <0 26 4>;
> > +
> > >>>> clocks = <&clkc 25>, <&clkc 34>; +			clock-names
> =
> > "ref_clk",
> > >>>> "pclk"; +			#address-cells = <1>; +			#size-
> > cells = <0>; +		};
> > >>>> + +		spi1: spi@e0007000 { +			compatible =
> > >>>> "xlnx,zynq-spi-r1p6"; +			reg = <0xe0007000 0x1000>; +
> > 			status
> > >>>> = "disabled"; +			interrupt-parent = <&intc>; +
> > 		interrupts =
> > >>>> <0 49 4>; +			clocks = <&clkc 26>, <&clkc 35>; +
> > 		clock-names
> > >>>> = "ref_clk", "pclk"; +			#address-cells = <1>; +
> > 		#size-cells
> > >>>> = <0>; +		}; +
> > >>> Until here things look good.
> > >>>
> > >>>> gem0: ethernet@e000b000 { compatible = "cdns,gem"; reg =
> > >>>> <0xe000b000 0x4000>; @@ -140,6 +164,19 @@ clock-names = "pclk",
> > >>>> "hclk", "tx_clk"; };
> > >>>>
> > >>>> +		qspi: qspi@e000d000 { +
> 	compatible =
> > >>>> "xlnx,zynq-spi-r1p6"; +			reg = <0xe000d000 0x1000>; +
> > 			status
> > >>>> = "disabled"; +			interrupt-parent = <&intc>; +
> > 		interrupts =
> > >>>> <0 19 4>; +			clocks = <&clkc 10>, <&clkc 43>; +
> > 		clock-names
> > >>>> = "ref_clk", "pclk"; +			num-cs = <1>; +
> > 	#address-cells =
> > >>>> <1>; +			#size-cells = <0>; +		}; +
> > >>> I'm not sure what the status of this driver is. I think QSPI is
> > >>> still under review on the mailing lists and I don't think we
> > >>> should add this yet.
> > >
> > >> Driver for qspi is not in the mainline yet but it doesn't mean that
> > >> this fragment won't work. Harini: Can you please correct me if I am
> > >> wrong?
> > >
> 
> It can be added but it will have to be disabled as there is no qspi driver
> at the moment in mainline.
> 

The cadence spi driver can't be used for qspi directly.
It’s better not to add qspi now. Once qspi driver is in mainline, qspi
can be added with the corresponding compatibility string.

Regards,
Harini

[PATCH v2 06/11] ARM: dts: zynq: Add DMAC for Parallella

[Andreas Färber]

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v2: New
 
 arch/arm/boot/dts/zynq-7000.dtsi      | 17 +++++++++++++++++
 arch/arm/boot/dts/zynq-parallella.dts |  4 ++++
 2 files changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index eed3df0..1a70277 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -223,6 +223,23 @@
 			};
 		};
 
+		dmac_s: dmac@f8003000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0xf8003000 0x1000>;
+			status = "disabled";
+			interrupt-parent = <&intc>;
+			interrupts = <0 13 4>,
+			             <0 14 4>, <0 15 4>,
+			             <0 16 4>, <0 17 4>,
+			             <0 40 4>, <0 41 4>,
+			             <0 42 4>, <0 43 4>;
+			#dma-cells = <1>;
+			#dma-channels = <8>;
+			#dma-requests = <4>;
+			clocks = <&clkc 27>;
+			clock-names = "apb_pclk";
+		};
+
 		devcfg: devcfg@f8007000 {
 			compatible = "xlnx,zynq-devcfg-1.0";
 			reg = <0xf8007000 0x100>;
diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index 56f68ea..e60a0a9 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -34,6 +34,10 @@
 	};
 };
 
+&dmac_s {
+	status = "okay";
+};
+
 &gem0 {
 	status = "okay";
 	phy-mode = "rgmii-id";
-- 
1.9.3

Re: [PATCH v2 06/11] ARM: dts: zynq: Add DMAC for Parallella

[Sören Brinkmann]

On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
>  v2: New
>  
>  arch/arm/boot/dts/zynq-7000.dtsi      | 17 +++++++++++++++++
>  arch/arm/boot/dts/zynq-parallella.dts |  4 ++++
>  2 files changed, 21 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
> index eed3df0..1a70277 100644
> --- a/arch/arm/boot/dts/zynq-7000.dtsi
> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
> @@ -223,6 +223,23 @@
>  			};
>  		};
>  
> +		dmac_s: dmac@f8003000 {
> +			compatible = "arm,pl330", "arm,primecell";
> +			reg = <0xf8003000 0x1000>;
> +			status = "disabled";
I think for this IP we can omit the 'status' property since it is always
enabled. I don't see a reason to override it in each board DT.

> +			interrupt-parent = <&intc>;
> +			interrupts = <0 13 4>,
> +			             <0 14 4>, <0 15 4>,
> +			             <0 16 4>, <0 17 4>,
> +			             <0 40 4>, <0 41 4>,
> +			             <0 42 4>, <0 43 4>;
> +			#dma-cells = <1>;
> +			#dma-channels = <8>;
> +			#dma-requests = <4>;
> +			clocks = <&clkc 27>;
> +			clock-names = "apb_pclk";
> +		};
> +

Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

	Sören

Re: [PATCH v2 06/11] ARM: dts: zynq: Add DMAC for Parallella

[Michal Simek]

[-- Attachment #1: Type: text/plain, Size: 1854 bytes --]

On 07/25/2014 01:28 AM, Sören Brinkmann wrote:
> On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
>> Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
>> ---
>>  v2: New
>>  
>>  arch/arm/boot/dts/zynq-7000.dtsi      | 17 +++++++++++++++++
>>  arch/arm/boot/dts/zynq-parallella.dts |  4 ++++
>>  2 files changed, 21 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
>> index eed3df0..1a70277 100644
>> --- a/arch/arm/boot/dts/zynq-7000.dtsi
>> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
>> @@ -223,6 +223,23 @@
>>  			};
>>  		};
>>  
>> +		dmac_s: dmac@f8003000 {
>> +			compatible = "arm,pl330", "arm,primecell";
>> +			reg = <0xf8003000 0x1000>;
>> +			status = "disabled";
> I think for this IP we can omit the 'status' property since it is always
> enabled. I don't see a reason to override it in each board DT.

Done this change myself

> 
>> +			interrupt-parent = <&intc>;
>> +			interrupts = <0 13 4>,
>> +			             <0 14 4>, <0 15 4>,
>> +			             <0 16 4>, <0 17 4>,
>> +			             <0 40 4>, <0 41 4>,
>> +			             <0 42 4>, <0 43 4>;
>> +			#dma-cells = <1>;
>> +			#dma-channels = <8>;
>> +			#dma-requests = <4>;
>> +			clocks = <&clkc 27>;
>> +			clock-names = "apb_pclk";
>> +		};
>> +
> 
> Acked-by: Soren Brinkmann <soren.brinkmann-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>


Applied to zynq/dt branch.
https://github.com/Xilinx/linux-xlnx/commits/zynq/dt

Thanks,
Michal

-- 
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w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform



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Re: [PATCH v2 06/11] ARM: dts: zynq: Add DMAC for Parallella

[Andreas Färber]

[-- Attachment #1: Type: text/plain, Size: 2064 bytes --]

Am 25.07.2014 10:02, schrieb Michal Simek:
> On 07/25/2014 01:28 AM, Sören Brinkmann wrote:
>> On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
>>> Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
>>> ---
>>>  v2: New
>>>  
>>>  arch/arm/boot/dts/zynq-7000.dtsi      | 17 +++++++++++++++++
>>>  arch/arm/boot/dts/zynq-parallella.dts |  4 ++++
>>>  2 files changed, 21 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
>>> index eed3df0..1a70277 100644
>>> --- a/arch/arm/boot/dts/zynq-7000.dtsi
>>> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
>>> @@ -223,6 +223,23 @@
>>>  			};
>>>  		};
>>>  
>>> +		dmac_s: dmac@f8003000 {
>>> +			compatible = "arm,pl330", "arm,primecell";
>>> +			reg = <0xf8003000 0x1000>;
>>> +			status = "disabled";
>> I think for this IP we can omit the 'status' property since it is always
>> enabled. I don't see a reason to override it in each board DT.
> 
> Done this change myself

Fine with me, but allow me to point out that the TRM documents the DMAC
being mapped as DMAC S at the above address, and as DMAC NS at F800_4000
(secure vs. non-secure, ch. 4.6, p. 116). Not sure how this would be
handled driver-wise if not through alternative dt nodes?

>>> +			interrupt-parent = <&intc>;
>>> +			interrupts = <0 13 4>,
>>> +			             <0 14 4>, <0 15 4>,
>>> +			             <0 16 4>, <0 17 4>,
>>> +			             <0 40 4>, <0 41 4>,
>>> +			             <0 42 4>, <0 43 4>;
>>> +			#dma-cells = <1>;
>>> +			#dma-channels = <8>;
>>> +			#dma-requests = <4>;
>>> +			clocks = <&clkc 27>;
>>> +			clock-names = "apb_pclk";
>>> +		};
>>> +
>>
>> Acked-by: Soren Brinkmann <soren.brinkmann-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> 
> 
> Applied to zynq/dt branch.
> https://github.com/Xilinx/linux-xlnx/commits/zynq/dt

Thanks,
Andreas

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Re: [PATCH v2 06/11] ARM: dts: zynq: Add DMAC for Parallella

[Michal Simek]

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On 07/25/2014 10:24 AM, Andreas Färber wrote:
> Am 25.07.2014 10:02, schrieb Michal Simek:
>> On 07/25/2014 01:28 AM, Sören Brinkmann wrote:
>>> On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
>>>> Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
>>>> ---
>>>>  v2: New
>>>>  
>>>>  arch/arm/boot/dts/zynq-7000.dtsi      | 17 +++++++++++++++++
>>>>  arch/arm/boot/dts/zynq-parallella.dts |  4 ++++
>>>>  2 files changed, 21 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
>>>> index eed3df0..1a70277 100644
>>>> --- a/arch/arm/boot/dts/zynq-7000.dtsi
>>>> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
>>>> @@ -223,6 +223,23 @@
>>>>  			};
>>>>  		};
>>>>  
>>>> +		dmac_s: dmac@f8003000 {
>>>> +			compatible = "arm,pl330", "arm,primecell";
>>>> +			reg = <0xf8003000 0x1000>;
>>>> +			status = "disabled";
>>> I think for this IP we can omit the 'status' property since it is always
>>> enabled. I don't see a reason to override it in each board DT.
>>
>> Done this change myself
> 
> Fine with me, but allow me to point out that the TRM documents the DMAC
> being mapped as DMAC S at the above address, and as DMAC NS at F800_4000
> (secure vs. non-secure, ch. 4.6, p. 116). Not sure how this would be
> handled driver-wise if not through alternative dt nodes?

Kernel on zynq runs in secure world. All the sw on zynq from beginning runs in secure world.
I haven't had any time to look at switching kernel to NS.
That's why having dmac in this dts as default configuration in secure world
is fine.

It is not about how driver will handle - driver shouldn't care.
It is how users will handle that kernel runs in non secure
and how to change DTS to reflect this.
Bootloader can do this change for example. Or if there is an option
to detect at run time by kernel that we are in NS than kernel itself can
patch dmac node and use different address.
Definitely bootloader or setup correct address by user is preferred way.

Thanks,
Michal



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Re: [PATCH v2 06/11] ARM: dts: zynq: Add DMAC for Parallella

[Sören Brinkmann]

On Fri, 2014-07-25 at 10:24AM +0200, Andreas Färber wrote:
> Am 25.07.2014 10:02, schrieb Michal Simek:
> > On 07/25/2014 01:28 AM, Sören Brinkmann wrote:
> >> On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
> >>> Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
> >>> ---
> >>>  v2: New
> >>>  
> >>>  arch/arm/boot/dts/zynq-7000.dtsi      | 17 +++++++++++++++++
> >>>  arch/arm/boot/dts/zynq-parallella.dts |  4 ++++
> >>>  2 files changed, 21 insertions(+)
> >>>
> >>> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
> >>> index eed3df0..1a70277 100644
> >>> --- a/arch/arm/boot/dts/zynq-7000.dtsi
> >>> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
> >>> @@ -223,6 +223,23 @@
> >>>  			};
> >>>  		};
> >>>  
> >>> +		dmac_s: dmac@f8003000 {
> >>> +			compatible = "arm,pl330", "arm,primecell";
> >>> +			reg = <0xf8003000 0x1000>;
> >>> +			status = "disabled";
> >> I think for this IP we can omit the 'status' property since it is always
> >> enabled. I don't see a reason to override it in each board DT.
> > 
> > Done this change myself
> 
> Fine with me, but allow me to point out that the TRM documents the DMAC
> being mapped as DMAC S at the above address, and as DMAC NS at F800_4000
> (secure vs. non-secure, ch. 4.6, p. 116). Not sure how this would be
> handled driver-wise if not through alternative dt nodes?

The upstream Linux runs in secure state on Zynq, hence I think this is fine. If
somebody wants to run Linux on Zynq non-secure they have to do some work
anyhow. This way the standard configuration can use the DMA engine.

	Sören

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[PATCH v2 07/11] Documentation: devicetree: Fix Xilinx VDMA specification

[Andreas Färber]

The specification requires xlnx,data-width, but example and driver use
xlnx,datawidth. Change the specification to match the implementation.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v2: New
 
 Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
index 1405ed0..e4c4d47 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
@@ -25,7 +25,7 @@ Required child node properties:
 - compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or
 	"xlnx,axi-vdma-s2mm-channel".
 - interrupts: Should contain per channel VDMA interrupts.
-- xlnx,data-width: Should contain the stream data width, take values
+- xlnx,datawidth: Should contain the stream data width, take values
 	{32,64...1024}.
 
 Optional child node properties:
-- 
1.9.3

Re: [PATCH v2 07/11] Documentation: devicetree: Fix Xilinx VDMA specification

[Michal Simek]

[-- Attachment #1: Type: text/plain, Size: 1646 bytes --]

Hi Vinod,

On 07/25/2014 01:00 AM, Andreas Färber wrote:
> The specification requires xlnx,data-width, but example and driver use
> xlnx,datawidth. Change the specification to match the implementation.
> 
> Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
> ---
>  v2: New
>  
>  Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
> index 1405ed0..e4c4d47 100644
> --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
> +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
> @@ -25,7 +25,7 @@ Required child node properties:
>  - compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or
>  	"xlnx,axi-vdma-s2mm-channel".
>  - interrupts: Should contain per channel VDMA interrupts.
> -- xlnx,data-width: Should contain the stream data width, take values
> +- xlnx,datawidth: Should contain the stream data width, take values
>  	{32,64...1024}.
>  
>  Optional child node properties:
> 

Can you please take this patch through your tree?

Reviewed-by: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>

Thanks,
Michal

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w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform



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Re: [PATCH v2 07/11] Documentation: devicetree: Fix Xilinx VDMA specification

[Andreas Färber]

[-- Attachment #1: Type: text/plain, Size: 1775 bytes --]

Hi Michal,

Am 25.07.2014 09:49, schrieb Michal Simek:
> On 07/25/2014 01:00 AM, Andreas Färber wrote:
>> The specification requires xlnx,data-width, but example and driver use
>> xlnx,datawidth. Change the specification to match the implementation.
>>
>> Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
>> ---
>>  v2: New
>>  
>>  Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
>> index 1405ed0..e4c4d47 100644
>> --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
>> +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
>> @@ -25,7 +25,7 @@ Required child node properties:
>>  - compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or
>>  	"xlnx,axi-vdma-s2mm-channel".
>>  - interrupts: Should contain per channel VDMA interrupts.
>> -- xlnx,data-width: Should contain the stream data width, take values
>> +- xlnx,datawidth: Should contain the stream data width, take values
>>  	{32,64...1024}.

BTW I just notice that this values specification is ambiguous as to
whether 96 is a valid value or only powers of 2 like 128. Maybe you want
to clarify that in a follow-up patch?

Cheers,
Andreas

>>  
>>  Optional child node properties:
>>
> 
> Can you please take this patch through your tree?
> 
> Reviewed-by: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> 
> Thanks,
> Michal

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Re: [PATCH v2 07/11] Documentation: devicetree: Fix Xilinx VDMA specification

[Michal Simek]

[-- Attachment #1: Type: text/plain, Size: 1579 bytes --]

Hi Andreas,

On 07/25/2014 10:46 AM, Andreas Färber wrote:
> Hi Michal,
> 
> Am 25.07.2014 09:49, schrieb Michal Simek:
>> On 07/25/2014 01:00 AM, Andreas Färber wrote:
>>> The specification requires xlnx,data-width, but example and driver use
>>> xlnx,datawidth. Change the specification to match the implementation.
>>>
>>> Signed-off-by: Andreas Färber <afaerber@suse.de>
>>> ---
>>>  v2: New
>>>  
>>>  Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
>>> index 1405ed0..e4c4d47 100644
>>> --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
>>> +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
>>> @@ -25,7 +25,7 @@ Required child node properties:
>>>  - compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or
>>>  	"xlnx,axi-vdma-s2mm-channel".
>>>  - interrupts: Should contain per channel VDMA interrupts.
>>> -- xlnx,data-width: Should contain the stream data width, take values
>>> +- xlnx,datawidth: Should contain the stream data width, take values
>>>  	{32,64...1024}.
> 
> BTW I just notice that this values specification is ambiguous as to
> whether 96 is a valid value or only powers of 2 like 128. Maybe you want
> to clarify that in a follow-up patch?

really appreciate your help for improving this.
Srikanth T: Can you please look at it?

Thanks,
Michal




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RE: [PATCH v2 07/11] Documentation: devicetree: Fix Xilinx VDMA specification

[Srikanth Thokala]

Hi Andreas,

> -----Original Message-----
> From: Michal Simek [mailto:michal.simek@xilinx.com]
> Sent: Friday, July 25, 2014 3:10 PM
> To: Andreas Färber; monstr@monstr.eu; Srikanth Thokala
> Cc: Vinod Koul; Michal Simek; Andreas Olofsson; Matteo Vit; Sean Rickerd;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; Rob Herring; Pawel Moll; Mark Rutland; Ian Campbell;
> Kumar Gala
> Subject: Re: [PATCH v2 07/11] Documentation: devicetree: Fix Xilinx VDMA
> specification
>
> Hi Andreas,
>
> On 07/25/2014 10:46 AM, Andreas Färber wrote:
> > Hi Michal,
> >
> > Am 25.07.2014 09:49, schrieb Michal Simek:
> >> On 07/25/2014 01:00 AM, Andreas Färber wrote:
> >>> The specification requires xlnx,data-width, but example and driver
> >>> use xlnx,datawidth. Change the specification to match the implementation.
> >>>
> >>> Signed-off-by: Andreas Färber <afaerber@suse.de>
> >>> ---
> >>>  v2: New
> >>>
> >>>  Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt | 2 +-
> >>>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>>
> >>> diff --git
> >>> a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
> >>> b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
> >>> index 1405ed0..e4c4d47 100644
> >>> --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
> >>> +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
> >>> @@ -25,7 +25,7 @@ Required child node properties:
> >>>  - compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or
> >>>   "xlnx,axi-vdma-s2mm-channel".
> >>>  - interrupts: Should contain per channel VDMA interrupts.
> >>> -- xlnx,data-width: Should contain the stream data width, take
> >>> values
> >>> +- xlnx,datawidth: Should contain the stream data width, take values
> >>>   {32,64...1024}.
> >
> > BTW I just notice that this values specification is ambiguous as to
> > whether 96 is a valid value or only powers of 2 like 128. Maybe you
> > want to clarify that in a follow-up patch?
>
> really appreciate your help for improving this.
> Srikanth T: Can you please look at it?

It should be only power of 2.  I could send a patch, but it is design-specific and
the design will not allow to take the intermediate values and so the device-tree
script.  So, I feel it should be fine to keep this way.

Thanks for this patch.

Srikanth

>
> Thanks,
> Michal
>
>



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[PATCH v2 08/11] ARM: dts: zynq: Add VDMA to Parallella

[Andreas Färber]

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v2: New
 
 arch/arm/boot/dts/zynq-parallella.dts | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index e60a0a9..8beaacc 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -32,6 +32,31 @@
 		bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
 		linux,stdout-path = "/amba/serial@e0001000";
 	};
+
+	fpga {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		axi_vdma: axi-vdma@43000000 {
+			compatible = "xlnx,axi-vdma-1.00.a";
+			reg = <0x43000000 0x1000>;
+			#dma-cells = <1>;
+			xlnx,num-fstores = <3>;
+			xlnx,include-sg = <0>;
+			xlnx,flush-fsync = <2>;
+
+			dma-channel@43000000 {
+				compatible = "xlnx,axi-vdma-mm2s-channel";
+				interrupt-parent = <&intc>;
+				interrupts = <0 59 4>;
+				xlnx,datawidth = <64>;
+				xlnx,include-dre = <0>;
+				xlnx,genlock-mode = <0>;
+			};
+		};
+	};
 };
 
 &dmac_s {
-- 
1.9.3

Re: [PATCH v2 08/11] ARM: dts: zynq: Add VDMA to Parallella

[Sören Brinkmann]

On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
> Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
> ---
>  v2: New
>  
>  arch/arm/boot/dts/zynq-parallella.dts | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
> index e60a0a9..8beaacc 100644
> --- a/arch/arm/boot/dts/zynq-parallella.dts
> +++ b/arch/arm/boot/dts/zynq-parallella.dts
> @@ -32,6 +32,31 @@
>  		bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
>  		linux,stdout-path = "/amba/serial@e0001000";
>  	};
> +
> +	fpga {
Do you really want FPGA components in this DT?
If somebody tries booting with this DT without programming with a
corresponding bitstream, the whole system might hang.
Just something to consider.

	Sören

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Re: [PATCH v2 08/11] ARM: dts: zynq: Add VDMA to Parallella

[Andreas Färber]

Hi Sören,

Am 25.07.2014 01:22, schrieb Sören Brinkmann:
> On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
>> Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
>> ---
>>  v2: New
>>  
>>  arch/arm/boot/dts/zynq-parallella.dts | 25 +++++++++++++++++++++++++
>>  1 file changed, 25 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
>> index e60a0a9..8beaacc 100644
>> --- a/arch/arm/boot/dts/zynq-parallella.dts
>> +++ b/arch/arm/boot/dts/zynq-parallella.dts
>> @@ -32,6 +32,31 @@
>>  		bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
>>  		linux,stdout-path = "/amba/serial@e0001000";
>>  	};
>> +
>> +	fpga {
> Do you really want FPGA components in this DT?
> If somebody tries booting with this DT without programming with a
> corresponding bitstream, the whole system might hang.
> Just something to consider.

Well, that's related to a question that remained unanswered on v1:
whether we may need to turn this into a .dtsi to cope with variations.

The Parallella has an on-board µHDMI connector, and two bitstreams are
delivered - one for HDMI and one for headless usage. In my testing I am
using the original HDMI bitstream but serial console for lack of
upstream HDMI drivers. Do you think we need to provide
zynq-parallella-hdmi.dts and zynq-parallella-headless.dts? (It gets
worse if at some point we need to handle variations of the on-board
Epiphany chip plus the bitstreams - at least the Z7010 vs. Z7020 doesn't
affect DT AFAICT.)

Since, as noted in the cover letter, these FPGA patches are not yet
fully testable, I wouldn't mind deferring them, but wanted to get them
out for review early.

http://www.parallella.org/2014/07/14/new-parallella-product-offerings/
indicates there will be a new variation in gen2 without USB/HDMI. Would
it be valid to #include a .dts (rather than .dtsi) to override status
and keep number of Parallella files low?

Regards,
Andreas

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Re: [PATCH v2 08/11] ARM: dts: zynq: Add VDMA to Parallella

[Sören Brinkmann]

On Fri, 2014-07-25 at 11:47AM +0200, Andreas Färber wrote:
> Hi Sören,
> 
> Am 25.07.2014 01:22, schrieb Sören Brinkmann:
> > On Fri, 2014-07-25 at 01:00AM +0200, Andreas Färber wrote:
> >> Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
> >> ---
> >>  v2: New
> >>  
> >>  arch/arm/boot/dts/zynq-parallella.dts | 25 +++++++++++++++++++++++++
> >>  1 file changed, 25 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
> >> index e60a0a9..8beaacc 100644
> >> --- a/arch/arm/boot/dts/zynq-parallella.dts
> >> +++ b/arch/arm/boot/dts/zynq-parallella.dts
> >> @@ -32,6 +32,31 @@
> >>  		bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
> >>  		linux,stdout-path = "/amba/serial@e0001000";
> >>  	};
> >> +
> >> +	fpga {
> > Do you really want FPGA components in this DT?
> > If somebody tries booting with this DT without programming with a
> > corresponding bitstream, the whole system might hang.
> > Just something to consider.
> 
> Well, that's related to a question that remained unanswered on v1:
> whether we may need to turn this into a .dtsi to cope with variations.
> 
> The Parallella has an on-board µHDMI connector, and two bitstreams are
> delivered - one for HDMI and one for headless usage. In my testing I am
> using the original HDMI bitstream but serial console for lack of
> upstream HDMI drivers. Do you think we need to provide
> zynq-parallella-hdmi.dts and zynq-parallella-headless.dts? (It gets
> worse if at some point we need to handle variations of the on-board
> Epiphany chip plus the bitstreams - at least the Z7010 vs. Z7020 doesn't
> affect DT AFAICT.)
> 
> Since, as noted in the cover letter, these FPGA patches are not yet
> fully testable, I wouldn't mind deferring them, but wanted to get them
> out for review early.
> 
> http://www.parallella.org/2014/07/14/new-parallella-product-offerings/
> indicates there will be a new variation in gen2 without USB/HDMI. Would
> it be valid to #include a .dts (rather than .dtsi) to override status
> and keep number of Parallella files low?

For these FPGA devices, it would be nice if it was possible to include
a dts file. I think there were problems with that, but don't know what
the current status of that is. Then it would be possible to have the SOC
dtsi a board dts and systems with FPGA components can include the board
dts.
I also heard that some people are getting upset with all the includes
going on in the dts files.

And the next question would be: How many dts files do you really want
in the upstream kernel tree? Since we deal with FPGAs, there is
virtually and infinite number of different systems that you could
create relatively easily.

	Sören

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[PATCH v2 09/11] Documentation: devicetree: Fix ADI AXI SPDIF specification

[Andreas Färber]

The specification requires compatible = "adi,axi-spdif-1.00.a" but
driver and example and file name indicate "adi,axi-spdif-tx-1.00.a".
Change the specification to match the implementation.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v2: New
 
 Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt b/Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt
index 46f3449..4eb7997 100644
--- a/Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt
+++ b/Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt
@@ -1,7 +1,7 @@
 ADI AXI-SPDIF controller
 
 Required properties:
- - compatible : Must be "adi,axi-spdif-1.00.a"
+ - compatible : Must be "adi,axi-spdif-tx-1.00.a"
  - reg : Must contain SPDIF core's registers location and length
  - clocks : Pairs of phandle and specifier referencing the controller's clocks.
    The controller expects two clocks, the clock used for the AXI interface and
-- 
1.9.3

Re: [PATCH v2 09/11] Documentation: devicetree: Fix ADI AXI SPDIF specification

[Lars-Peter Clausen]

On 07/25/2014 01:00 AM, Andreas Färber wrote:
> The specification requires compatible = "adi,axi-spdif-1.00.a" but
> driver and example and file name indicate "adi,axi-spdif-tx-1.00.a".
> Change the specification to match the implementation.
>
> Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>

Acked-by: Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>

Thanks.

> ---
>   v2: New
>
>   Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt b/Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt
> index 46f3449..4eb7997 100644
> --- a/Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt
> +++ b/Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt
> @@ -1,7 +1,7 @@
>   ADI AXI-SPDIF controller
>
>   Required properties:
> - - compatible : Must be "adi,axi-spdif-1.00.a"
> + - compatible : Must be "adi,axi-spdif-tx-1.00.a"
>    - reg : Must contain SPDIF core's registers location and length
>    - clocks : Pairs of phandle and specifier referencing the controller's clocks.
>      The controller expects two clocks, the clock used for the AXI interface and
>

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Re: [PATCH v2 09/11] Documentation: devicetree: Fix ADI AXI SPDIF specification

[Michal Simek]

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Hi Mark,

On 07/25/2014 09:42 AM, Lars-Peter Clausen wrote:
> On 07/25/2014 01:00 AM, Andreas Färber wrote:
>> The specification requires compatible = "adi,axi-spdif-1.00.a" but
>> driver and example and file name indicate "adi,axi-spdif-tx-1.00.a".
>> Change the specification to match the implementation.
>>
>> Signed-off-by: Andreas Färber <afaerber@suse.de>
> 
> Acked-by: Lars-Peter Clausen <lars@metafoo.de>

All these patches have been added through your tree that's why I think
you should take this fix through his tree.

Here is my:
Reviewed-by: Michal Simek <michal.simek@xilinx.com>

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform



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Re: [PATCH v2 09/11] Documentation: devicetree: Fix ADI AXI SPDIF specification

[Mark Brown]

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On Fri, Jul 25, 2014 at 10:08:06AM +0200, Michal Simek wrote:

> All these patches have been added through your tree that's why I think
> you should take this fix through his tree.

If someone could send me patches I'll take a look at them.

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Re: [PATCH v2 09/11] Documentation: devicetree: Fix ADI AXI SPDIF specification

[Andreas Färber]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Am 25.07.2014 12:18, schrieb Mark Brown:
> On Fri, Jul 25, 2014 at 10:08:06AM +0200, Michal Simek wrote:
> 
>> All these patches have been added through your tree that's why I
>> think you should take this fix through his tree.
> 
> If someone could send me patches I'll take a look at them.

I used scripts/get_maintainer.pl --nogit-fallback. If you were not
CC'ed and need to be, please submit a MAINTAINERS patch. :)

Maybe this works for you?
https://patchwork.kernel.org/patch/4620191/

Otherwise I can resend with Ab/Rb.

Andreas

- -- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
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Re: [PATCH v2 09/11] Documentation: devicetree: Fix ADI AXI SPDIF specification

[Mark Brown]

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On Fri, Jul 25, 2014 at 12:32:43PM +0200, Andreas Färber wrote:

> I used scripts/get_maintainer.pl --nogit-fallback. If you were not
> CC'ed and need to be, please submit a MAINTAINERS patch. :)

You need to think about what you're doing when you use get_maintainer,
it gives both false positives and false negatives.

> Maybe this works for you?
> https://patchwork.kernel.org/patch/4620191/

> Otherwise I can resend with Ab/Rb.

Documentation/SubmittingPatches.

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Re: [PATCH v2 09/11] Documentation: devicetree: Fix ADI AXI SPDIF specification

[Andreas Färber]

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Mark,

Am 25.07.2014 12:39, schrieb Mark Brown:
> On Fri, Jul 25, 2014 at 12:32:43PM +0200, Andreas Färber wrote:
> 
>> I used scripts/get_maintainer.pl --nogit-fallback. If you were not
>> CC'ed and need to be, please submit a MAINTAINERS patch. :)
> 
> You need to think about what you're doing when you use get_maintainer,
> it gives both false positives and false negatives.
> 
>> Maybe this works for you?
>> https://patchwork.kernel.org/patch/4620191/
> 
>> Otherwise I can resend with Ab/Rb.
> 
> Documentation/SubmittingPatches.

Not helpful here, nor is
Documentation/devicetree/bindings/submitting-patches.txt. It's separate
from code changes, sent via git-send-email, has a Sob, went to LKML and
LAKML and DTML. I could add a Fixes: header and CC trivial for this
one-line fix IIUC.
Doesn't tell me which patches I should CC you on in the future though.
Therefore my request to fix the false negative in MAINTAINERS so that me
and other kernel newbies don't run into it again.

I'll simply interpret your reply as "yes, please resend with
broonie@kernel.org CC'ed" then.

Regards,
Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg


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Re: [PATCH v2 09/11] Documentation: devicetree: Fix ADI AXI SPDIF specification

[Mark Brown]

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On Mon, Jul 28, 2014 at 01:43:02PM +0200, Andreas Färber wrote:
> Am 25.07.2014 12:39, schrieb Mark Brown:
> > On Fri, Jul 25, 2014 at 12:32:43PM +0200, Andreas Färber wrote:

> >> Maybe this works for you?
> >> https://patchwork.kernel.org/patch/4620191/

> >> Otherwise I can resend with Ab/Rb.

> > Documentation/SubmittingPatches.

> Not helpful here, nor is
> Documentation/devicetree/bindings/submitting-patches.txt. It's separate
> from code changes, sent via git-send-email, has a Sob, went to LKML and
> LAKML and DTML. I could add a Fixes: header and CC trivial for this
> one-line fix IIUC.

It's telling you that the kernel process is to review patches sent via
e-mail, not random links to web appliations - notice the context to
which I'm replying, I'm saying that sending a link to something on the
web isn't a good way of submitting a patch.

> Doesn't tell me which patches I should CC you on in the future though.
> Therefore my request to fix the false negative in MAINTAINERS so that me
> and other kernel newbies don't run into it again.

Feel free to submit patches if you want to see changes.

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Re: [PATCH v2 09/11] Documentation: devicetree: Fix ADI AXI SPDIF specification

[Andreas Färber]

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Am 28.07.2014 14:20, schrieb Mark Brown:
> On Mon, Jul 28, 2014 at 01:43:02PM +0200, Andreas Färber wrote:
>> Am 25.07.2014 12:39, schrieb Mark Brown:
>>> On Fri, Jul 25, 2014 at 12:32:43PM +0200, Andreas Färber wrote:
> 
>>>> Maybe this works for you?
>>>> https://patchwork.kernel.org/patch/4620191/
> 
>>>> Otherwise I can resend with Ab/Rb.
> 
>>> Documentation/SubmittingPatches.
> 
>> Not helpful here, nor is
>> Documentation/devicetree/bindings/submitting-patches.txt. It's separate
>> from code changes, sent via git-send-email, has a Sob, went to LKML and
>> LAKML and DTML. I could add a Fixes: header and CC trivial for this
>> one-line fix IIUC.
> 
> It's telling you that the kernel process is to review patches sent via
> e-mail, not random links to web appliations - notice the context to
> which I'm replying, I'm saying that sending a link to something on the
> web isn't a good way of submitting a patch.
> 
>> Doesn't tell me which patches I should CC you on in the future though.
>> Therefore my request to fix the false negative in MAINTAINERS so that me
>> and other kernel newbies don't run into it again.
> 
> Feel free to submit patches if you want to see changes.

Dude, this patch *was* submitted and has been reviewed by two people.
Don't pretend I didn't follow the SubmittingPatches workflow.

The link I gave you contains an mbox-format link that can be used with
wget and git-am to *apply* the patch if you apparently missed it on the
mailing lists.

I will *re*-submit it for your convenience.

Andreas

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GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg


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Re: [PATCH v2 09/11] Documentation: devicetree: Fix ADI AXI SPDIF specification

[Mark Brown]

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On Mon, Jul 28, 2014 at 02:28:12PM +0200, Andreas Färber wrote:

> Dude, this patch *was* submitted and has been reviewed by two people.
> Don't pretend I didn't follow the SubmittingPatches workflow.

> The link I gave you contains an mbox-format link that can be used with
> wget and git-am to *apply* the patch if you apparently missed it on the
> mailing lists.

> I will *re*-submit it for your convenience.

Which is what I originally requested when I got CCed into the thread -
I'm being grumpy because instead of getting the patch sent to me as
requested I got sent a link to patchwork.

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Re: [PATCH v2 09/11] Documentation: devicetree: Fix ADI AXI SPDIF specification

[Andreas Färber]

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Am 28.07.2014 15:44, schrieb Mark Brown:
> On Mon, Jul 28, 2014 at 02:28:12PM +0200, Andreas Färber wrote:
> 
>> I will *re*-submit it for your convenience.
> 
> Which is what I originally requested when I got CCed into the thread -
> I'm being grumpy because instead of getting the patch sent to me as
> requested I got sent a link to patchwork.

Hindsight, had you simply replied with "Yes, please." instead of the
non-telling "Documentation/SubmittingPatches.", you would've spared
yourself keystrokes and us four mailing list messages. ;)

Similarly, your statement about false negatives didn't really help in
resolving the not-CC'ed problem. I now know to CC you if I ever have
something for adi,axi-spdif-tx.txt again, but the next person might make
you grumpy again and potentially demotivates new contributors, so
certainly worth fixing.

Regmap, SPI, regulators, touchscreen MAINTAINERS entries seem unrelated.
Should your "SOUND - SOC LAYER / DYNAMIC AUDIO POWER MANAGEMENT (ASoC)"
MAINTAINERS entry get an
F: Documentation/devicetree/bindings/sound/
or is the "ANALOG DEVICES Inc ASOC DRIVERS" entry missing a line
F: sound/soc/adi/
F: Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt
(which would then still not CC you)
or is a new MAINTAINERS section needed that CCs specifically Lars-Peter
and you on the latter?

Regards,
Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg


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Re: [PATCH v2 09/11] Documentation: devicetree: Fix ADI AXI SPDIF specification

[Mark Brown]

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On Mon, Jul 28, 2014 at 05:39:46PM +0200, Andreas Färber wrote:

> Similarly, your statement about false negatives didn't really help in
> resolving the not-CC'ed problem. I now know to CC you if I ever have
> something for adi,axi-spdif-tx.txt again, but the next person might make
> you grumpy again and potentially demotivates new contributors, so
> certainly worth fixing.

> Regmap, SPI, regulators, touchscreen MAINTAINERS entries seem unrelated.
> Should your "SOUND - SOC LAYER / DYNAMIC AUDIO POWER MANAGEMENT (ASoC)"
> MAINTAINERS entry get an
> F: Documentation/devicetree/bindings/sound/
> or is the "ANALOG DEVICES Inc ASOC DRIVERS" entry missing a line
> F: sound/soc/adi/
> F: Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt
> (which would then still not CC you)
> or is a new MAINTAINERS section needed that CCs specifically Lars-Peter
> and you on the latter?

What you're really talking about is making MAINTAINERS complete which is
a very big job; even if only looking at the DT bindings you'd need to go
through every binding and make sure that MAINTAINERS says the same
things as it does for the matching driver code, and where there are
missing entries add them.  In the immediate case both bits are missing.

Really as with so much else it's much better advice to ask people to
look and think about what they're doing; it's the same thing as ensuring
that commit logs match the standard style for the thing being edited
(especially the subject lines) and that if there's people who normally
apply patches and work on the code they're included.

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[PATCH v2 10/11] ARM: dts: zynq: Add SPDIF for Parallella

[Andreas Färber]

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v2: New
 
 arch/arm/boot/dts/zynq-parallella.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index 8beaacc..65fbd8b 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -56,6 +56,21 @@
 				xlnx,genlock-mode = <0>;
 			};
 		};
+
+		audio_clock: audio-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <12288000>;
+		};
+
+		axi-spdif-tx@0x75c00000 {
+			compatible = "adi,axi-spdif-tx-1.00.a";
+			reg = <0x75c00000 0x1000>;
+			clocks = <&clkc 15>, <&audio_clock>;
+			clock-names = "axi", "ref";
+			dmas = <&dmac_s 0>;
+			dma-names = "tx";
+		};
 	};
 };
 
-- 
1.9.3

[PATCH v2 11/11] ARM: dts: zynq: Add AXI clkgen for Parallella

[Andreas Färber]

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v2: New
 
 arch/arm/boot/dts/zynq-parallella.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index 65fbd8b..d2eefad 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -57,6 +57,13 @@
 			};
 		};
 
+		axi_clkgen: axi-clkgen@66000000 {
+			compatible = "adi,axi-clkgen-1.00.a";
+			reg = <0x66000000 0x10000>;
+			#clock-cells = <0>;
+			clocks = <&clkc 17>;
+		};
+
 		audio_clock: audio-clock {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-- 
1.9.3

RE: [PATCH v2 00/11] ARM: dts: zynq: Prepare Parallella

[Punnaiah Choudary Kalluri]

Hi Andreas,

>-----Original Message-----
>From: Andreas Färber [mailto:afaerber@suse.de]
>Sent: Friday, July 25, 2014 4:30 AM
>To: Michal Simek
>Cc: Andreas Olofsson; Matteo Vit; Sean Rickerd; devicetree@vger.kernel.org;
>linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Andreas
>Färber; Punnaiah Choudary Kalluri; Lars-Peter Clausen
>Subject: [PATCH v2 00/11] ARM: dts: zynq: Prepare Parallella
>
>Hello,
>
>This patch series adds an initial device tree for the Parallella board.
>UART, SD card, Ethernet are enabled.
>Not yet enabled are HDMI, QSPI flash and 2x USB.
>
>v2 adds some SPI and FPGA pieces and tidies the device tree with a
>compatible string and matching documentation.
>
>Not having all pieces for testing all of this (most notably I'm missing
>ADI ADV7513 and AXI-HDMI support for VDMA and axi-clkgen, as well as
>the 25Q128A flash chip for QSPI), I've kept new things in separate patches
>so that we can make progress on the basic version and possibly squash
>further cherry-picked pieces.
>
>Punnaiah Choudary Kalluri had recently proposed to extend the Chipidea
>USB driver for Zynq; it kept complaining about the PHY though, and I
>haven't spotted a revised version based on the generic driver yet.
>https://patchwork.kernel.org/patch/4434681/

The plan is, go with generic chip idea driver which is currently under review. 
http://www.spinics.net/lists/linux-usb/msg109576.html

So, please wait some more time for extending the Chip idea driver support
 to zynq.

Punnaiah
>
>My rebasing work branch is here:
>https://github.com/afaerber/linux/commits/parallella-next
>
>Regards,
>Andreas
>
>Cc: Punnaiah Choudary Kalluri <punnaia@xilinx.com> (USB)
>Cc: Lars-Peter Clausen <lars@metafoo.de> (HDMI)
>
>Andreas Färber (11):
>  Documentation: devicetree: Adapteva vendor prefix
>  Documentation: devicetree: Adapteva boards
>  ARM: dts: zynq: Add Parallella device tree
>  ARM: dts: zynq: Update deprecated xuartps clock names
>  ARM: dts: zynq: Add QSPI for Parallella
>  ARM: dts: zynq: Add DMAC for Parallella
>  Documentation: devicetree: Fix Xilinx VDMA specification
>  ARM: dts: zynq: Add VDMA to Parallella
>  Documentation: devicetree: Fix ADI AXI SPDIF specification
>  ARM: dts: zynq: Add SPDIF for Parallella
>  ARM: dts: zynq: Add AXI clkgen for Parallella
>
> Documentation/devicetree/bindings/arm/adapteva.txt |   7 ++
> .../devicetree/bindings/dma/xilinx/xilinx_vdma.txt |   2 +-
> .../devicetree/bindings/sound/adi,axi-spdif-tx.txt |   2 +-
> .../devicetree/bindings/vendor-prefixes.txt        |   1 +
> arch/arm/boot/dts/Makefile                         |   4 +-
> arch/arm/boot/dts/zynq-7000.dtsi                   |  58 +++++++++-
> arch/arm/boot/dts/zynq-parallella.dts              | 119
>+++++++++++++++++++++
> 7 files changed, 188 insertions(+), 5 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/adapteva.txt
> create mode 100644 arch/arm/boot/dts/zynq-parallella.dts
>
>--
>1.9.3

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Re: [PATCH v2 00/11] ARM: dts: zynq: Prepare Parallella

[Andreas Färber]

Hi Punnaiah,

Am 25.07.2014 05:49, schrieb Punnaiah Choudary Kalluri:
>> Punnaiah Choudary Kalluri had recently proposed to extend the Chipidea
>> USB driver for Zynq; it kept complaining about the PHY though, and I
>> haven't spotted a revised version based on the generic driver yet.
>> https://patchwork.kernel.org/patch/4434681/
> 
> The plan is, go with generic chip idea driver which is currently under review. 
> http://www.spinics.net/lists/linux-usb/msg109576.html
> 
> So, please wait some more time for extending the Chip idea driver support
>  to zynq.

Thanks, I did understand that from the Patchwork link. I was however
wondering whether you already have some work branch based on Antoine
Ténart's series that you could share?

When we get HDMI working, a USB keyboard will come very handy. ;)

Otherwise, could you please take a look at my branch and let me know
whether I'm doing something fundamentally wrong in wiring your old
driver up in my DT? I did not see any .dts example doing so.

Cheers,
Andreas

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Re: [PATCH v2 00/11] ARM: dts: zynq: Prepare Parallella

[Andreas Färber]

Hi Lars-Peter,

Am 25.07.2014 01:00, schrieb Andreas Färber:
> most notably I'm missing 
> ADI ADV7513 and AXI-HDMI support
[...]
> Cc: Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org> (HDMI)

Could you please enlighten us what the status of upstreaming
ADV7511/ADV7513 support is? It is declared "work in progress" here:

http://wiki.analog.com/resources/tools-software/linux-drivers/drm/adv7511

I see some adv7511 V4L bits in drivers/media/i2c/adv7511.c, but no
drivers/gpu/drm/i2c/adv7511_{core,audio}.c as on the xcomm_zynq branch,
nor any devicetree documentation. Patchwork doesn't show any recent
submissions to LKML.

Is any major rework needed for you to get the 3.14.12 based driver upstream?

AXI SPDIF I found in 3.16, as you noticed; what about AXI HDMI? [*]
Is there any work ongoing to get that upstream as well?

Any pointers appreciated.

Thanks,
Andreas

[*]
http://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq

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Re: [PATCH v2 00/11] ARM: dts: zynq: Prepare Parallella

[Lars-Peter Clausen]

On 07/28/2014 06:17 PM, Andreas Färber wrote:
> Hi Lars-Peter,
>
> Am 25.07.2014 01:00, schrieb Andreas Färber:
>> most notably I'm missing
>> ADI ADV7513 and AXI-HDMI support
> [...]
>> Cc: Lars-Peter Clausen <lars@metafoo.de> (HDMI)
>
> Could you please enlighten us what the status of upstreaming
> ADV7511/ADV7513 support is? It is declared "work in progress" here:
>
> http://wiki.analog.com/resources/tools-software/linux-drivers/drm/adv7511
>
> I see some adv7511 V4L bits in drivers/media/i2c/adv7511.c, but no
> drivers/gpu/drm/i2c/adv7511_{core,audio}.c as on the xcomm_zynq branch,
> nor any devicetree documentation. Patchwork doesn't show any recent
> submissions to LKML.
>
> Is any major rework needed for you to get the 3.14.12 based driver upstream?
>

It's complicated. The plan for the driver was to wait for the common display 
framework (CDF) and convert it to use CDF and then submit it upstream. The 
CDF has been rejected though. Meanwhile the V4L2 adv7511 driver has been 
merged. So now we are in the ugly situation that we have two different 
drivers for two different frameworks. To fix this we need to merge these two 
drivers while still exposing the interfaces to both frameworks.

> AXI SPDIF I found in 3.16, as you noticed; what about AXI HDMI? [*]
> Is there any work ongoing to get that upstream as well?

We need to teach the DMAengine framework about cyclic interleaved transfers 
before the AXI HDMI driver can be submitted upstream.

- Lars

Re: [PATCH v2 00/11] ARM: dts: zynq: Prepare Parallella

[Olof Johansson]

Hi Andreas,

On Thu, Jul 24, 2014 at 4:00 PM, Andreas Färber <afaerber@suse.de> wrote:
> Hello,
>
> This patch series adds an initial device tree for the Parallella board.
> UART, SD card, Ethernet are enabled.
> Not yet enabled are HDMI, QSPI flash and 2x USB.

Andreas (Olofsson) kindly sent me a board, and I added it to the boot
farm today, it'll be included in boot reports from here on.

I did a test run with yesterday's -next It looks like networking isn't
working there at the moment, clock related. Same happens with 3.17 and
latest mainline, config multi_v7_defconfig:

[WARN] [    7.943648] macb e000b000.ethernet eth0: unable to generate
target frequency: 125000000 Hz
[WARN] [   10.948681] macb e000b000.ethernet eth0: unable to generate
target frequency: 125000000 Hz

Full boot log at:

http://arm-soc.lixom.net/bootlogs/misc/next-20141017/parallella-arm-multi_v7_defconfig.html

I'll be happy to try things, but I'm a bit short on cycles to debug
myself. Should hopefully be easy to reproduce.


-Olof

RE: [PATCH v2 00/11] ARM: dts: zynq: Prepare Parallella

[Soren Brinkmann]

Sorry, for top-posting, but I currently just have Outlook webmail.
The cause for this issue is relatively easily identified. The ethernet drivers sets the Ethernet clock according to the negotioated link speed. For this adjustment a 6-bit divider in the clock path is used. In this case, it seems, the input to the 6-bit divider doesn't allow generating the full range of required frequencies for all supported link speeds.

I guess this could be solved in multiple ways.
1. Disable 1G mode/auto negotiation, the other modes are probably fine (yeah, not a solution, but might give you a working ethernet link)
2. Ensure the divider input allows to generate all required frequencies. This essentially means to go back into Xilinx tools and play around with the clock/PLL setup and re-generating a bootloader that sets things up with the updated values.
3. Support to run-time-adust the PLLs in Zynq. This is definitely the most complex one. I never seriously pursued this, since it seemed close to impossible to change the PLLs at run-time without crashing pretty much every downstream user except for the one that requested the frequency change. And even if every driver would be able to handle such a change, I could imagine that frequency constraints from  all the drivers together would still prevent any change.

        Thanks,
        Sören

________________________________________
From: devicetree-owner@vger.kernel.org [devicetree-owner@vger.kernel.org] on behalf of Olof Johansson [olof@lixom.net]
Sent: Friday, October 17, 2014 9:28 PM
To: Andreas Färber
Cc: Michal Simek; Andreas Olofsson; Matteo Vit; Sean Rickerd; devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Punnaiah Choudary Kalluri; Lars-Peter Clausen
Subject: Re: [PATCH v2 00/11] ARM: dts: zynq: Prepare Parallella

Hi Andreas,

On Thu, Jul 24, 2014 at 4:00 PM, Andreas Färber <afaerber@suse.de> wrote:
> Hello,
>
> This patch series adds an initial device tree for the Parallella board.
> UART, SD card, Ethernet are enabled.
> Not yet enabled are HDMI, QSPI flash and 2x USB.

Andreas (Olofsson) kindly sent me a board, and I added it to the boot
farm today, it'll be included in boot reports from here on.

I did a test run with yesterday's -next It looks like networking isn't
working there at the moment, clock related. Same happens with 3.17 and
latest mainline, config multi_v7_defconfig:

[WARN] [    7.943648] macb e000b000.ethernet eth0: unable to generate
target frequency: 125000000 Hz
[WARN] [   10.948681] macb e000b000.ethernet eth0: unable to generate
target frequency: 125000000 Hz

Full boot log at:

http://arm-soc.lixom.net/bootlogs/misc/next-20141017/parallella-arm-multi_v7_defconfig.html

I'll be happy to try things, but I'm a bit short on cycles to debug
myself. Should hopefully be easy to reproduce.


-Olof
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Re: [PATCH v2 00/11] ARM: dts: zynq: Prepare Parallella

[Andreas Färber]

[-- Attachment #1: Type: text/plain, Size: 1386 bytes --]

Hi Olof and Sören,

Am 18.10.2014 um 06:28 schrieb Olof Johansson:
> On Thu, Jul 24, 2014 at 4:00 PM, Andreas Färber <afaerber@suse.de> wrote:
>> Hello,
>>
>> This patch series adds an initial device tree for the Parallella board.
>> UART, SD card, Ethernet are enabled.
>> Not yet enabled are HDMI, QSPI flash and 2x USB.
> 
> Andreas (Olofsson) kindly sent me a board, and I added it to the boot
> farm today, it'll be included in boot reports from here on.

Good to hear.

> I did a test run with yesterday's -next It looks like networking isn't
> working there at the moment, clock related. Same happens with 3.17 and
> latest mainline, config multi_v7_defconfig:
> 
> [WARN] [    7.943648] macb e000b000.ethernet eth0: unable to generate
> target frequency: 125000000 Hz
> [WARN] [   10.948681] macb e000b000.ethernet eth0: unable to generate
> target frequency: 125000000 Hz

I am unable to reproduce this in my setup - at Linus' tip
c2661b806092d8ea2dccb7b02b65776555e0ee47 (v3.18-rc1-68-gc2661b8), make
oldconfig'ing my /proc/config.gz.

Sören, in light of your explanations, should I be expecting problems
with 1GbE or with 100MbE? My board is connected to a 1GbE switch.

Regards,
Andreas

-- 
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GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg


[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

Re: [PATCH v2 00/11] ARM: dts: zynq: Prepare Parallella

[Sören Brinkmann]

On Tue, 2014-10-21 at 10:52PM +0200, Andreas Färber wrote:
> Hi Olof and Sören,
> 
> Am 18.10.2014 um 06:28 schrieb Olof Johansson:
> > On Thu, Jul 24, 2014 at 4:00 PM, Andreas Färber <afaerber@suse.de> wrote:
> >> Hello,
> >>
> >> This patch series adds an initial device tree for the Parallella board.
> >> UART, SD card, Ethernet are enabled.
> >> Not yet enabled are HDMI, QSPI flash and 2x USB.
> > 
> > Andreas (Olofsson) kindly sent me a board, and I added it to the boot
> > farm today, it'll be included in boot reports from here on.
> 
> Good to hear.
> 
> > I did a test run with yesterday's -next It looks like networking isn't
> > working there at the moment, clock related. Same happens with 3.17 and
> > latest mainline, config multi_v7_defconfig:
> > 
> > [WARN] [    7.943648] macb e000b000.ethernet eth0: unable to generate
> > target frequency: 125000000 Hz
> > [WARN] [   10.948681] macb e000b000.ethernet eth0: unable to generate
> > target frequency: 125000000 Hz
> 
> I am unable to reproduce this in my setup - at Linus' tip
> c2661b806092d8ea2dccb7b02b65776555e0ee47 (v3.18-rc1-68-gc2661b8), make
> oldconfig'ing my /proc/config.gz.
> 
> Sören, in light of your explanations, should I be expecting problems
> with 1GbE or with 100MbE? My board is connected to a 1GbE switch.

Not in general. As I said, I haven't seen that on our boards yet and I
did a little bit of testing making sure that the fundamental code to
switch between frequencies works. I.e. on our zc706 and zc702 boards I
usually can use ethtool to force a certain speed on the interface and
Zynq adjusts to it just fine.

But as I said, it does rely on the divider being sourced with a
frequency that allows generating the required Ethernet clock by
adjusting the 6-bit divider only. If this requirement is not met,
I expect you may see issues like Olof posted.

Are you (Andreas/Olof) using the same bootloaders?

I hope that helps.

	Sören

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Re: [PATCH v2 00/11] ARM: dts: zynq: Prepare Parallella

[Olof Johansson]

On Tue, Oct 21, 2014 at 1:52 PM, Andreas Färber <afaerber@suse.de> wrote:
> Hi Olof and Sören,
>
> Am 18.10.2014 um 06:28 schrieb Olof Johansson:
>> On Thu, Jul 24, 2014 at 4:00 PM, Andreas Färber <afaerber@suse.de> wrote:
>>> Hello,
>>>
>>> This patch series adds an initial device tree for the Parallella board.
>>> UART, SD card, Ethernet are enabled.
>>> Not yet enabled are HDMI, QSPI flash and 2x USB.
>>
>> Andreas (Olofsson) kindly sent me a board, and I added it to the boot
>> farm today, it'll be included in boot reports from here on.
>
> Good to hear.
>
>> I did a test run with yesterday's -next It looks like networking isn't
>> working there at the moment, clock related. Same happens with 3.17 and
>> latest mainline, config multi_v7_defconfig:
>>
>> [WARN] [    7.943648] macb e000b000.ethernet eth0: unable to generate
>> target frequency: 125000000 Hz
>> [WARN] [   10.948681] macb e000b000.ethernet eth0: unable to generate
>> target frequency: 125000000 Hz
>
> I am unable to reproduce this in my setup - at Linus' tip
> c2661b806092d8ea2dccb7b02b65776555e0ee47 (v3.18-rc1-68-gc2661b8), make
> oldconfig'ing my /proc/config.gz.
>
> Sören, in light of your explanations, should I be expecting problems
> with 1GbE or with 100MbE? My board is connected to a 1GbE switch.

My board might have old firmware/bitstream on it? It reports as:

U-Boot 2012.10-00003-g792c31c (Jan 03 2014 - 12:24:08)


-Olof

Re: [PATCH v2 00/11] ARM: dts: zynq: Prepare Parallella

[Andreas Färber]

Am 21.10.2014 um 23:01 schrieb Olof Johansson:
> On Tue, Oct 21, 2014 at 1:52 PM, Andreas Färber <afaerber@suse.de> wrote:
>> Am 18.10.2014 um 06:28 schrieb Olof Johansson:
>>> I did a test run with yesterday's -next It looks like networking isn't
>>> working there at the moment, clock related. Same happens with 3.17 and
>>> latest mainline, config multi_v7_defconfig:
>>>
>>> [WARN] [    7.943648] macb e000b000.ethernet eth0: unable to generate
>>> target frequency: 125000000 Hz
>>> [WARN] [   10.948681] macb e000b000.ethernet eth0: unable to generate
>>> target frequency: 125000000 Hz
>>
>> I am unable to reproduce this in my setup - at Linus' tip
>> c2661b806092d8ea2dccb7b02b65776555e0ee47 (v3.18-rc1-68-gc2661b8), make
>> oldconfig'ing my /proc/config.gz.
>>
>> Sören, in light of your explanations, should I be expecting problems
>> with 1GbE or with 100MbE? My board is connected to a 1GbE switch.
> 
> My board might have old firmware/bitstream on it? It reports as:
> 
> U-Boot 2012.10-00003-g792c31c (Jan 03 2014 - 12:24:08)

Mine reports the same version.

sha512sum of non-headless bitstream:
decb37222a7da0de39b1c1eb95714500cc006506cc86d85ed9c6c7b30c7cd7b91ef3592b886311f4285b5ce0079b4ffcd83f91ae275435ac15cefefe7db00b08
 /mnt/parallella.bit.bin

Andreas

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Re: [PATCH v2 00/11] ARM: dts: zynq: Prepare Parallella

[Olof Johansson]

On Tue, Oct 21, 2014 at 2:07 PM, Andreas Färber <afaerber@suse.de> wrote:
> Am 21.10.2014 um 23:01 schrieb Olof Johansson:
>> On Tue, Oct 21, 2014 at 1:52 PM, Andreas Färber <afaerber@suse.de> wrote:
>>> Am 18.10.2014 um 06:28 schrieb Olof Johansson:
>>>> I did a test run with yesterday's -next It looks like networking isn't
>>>> working there at the moment, clock related. Same happens with 3.17 and
>>>> latest mainline, config multi_v7_defconfig:
>>>>
>>>> [WARN] [    7.943648] macb e000b000.ethernet eth0: unable to generate
>>>> target frequency: 125000000 Hz
>>>> [WARN] [   10.948681] macb e000b000.ethernet eth0: unable to generate
>>>> target frequency: 125000000 Hz
>>>
>>> I am unable to reproduce this in my setup - at Linus' tip
>>> c2661b806092d8ea2dccb7b02b65776555e0ee47 (v3.18-rc1-68-gc2661b8), make
>>> oldconfig'ing my /proc/config.gz.
>>>
>>> Sören, in light of your explanations, should I be expecting problems
>>> with 1GbE or with 100MbE? My board is connected to a 1GbE switch.
>>
>> My board might have old firmware/bitstream on it? It reports as:
>>
>> U-Boot 2012.10-00003-g792c31c (Jan 03 2014 - 12:24:08)
>
> Mine reports the same version.
>
> sha512sum of non-headless bitstream:
> decb37222a7da0de39b1c1eb95714500cc006506cc86d85ed9c6c7b30c7cd7b91ef3592b886311f4285b5ce0079b4ffcd83f91ae275435ac15cefefe7db00b08
>  /mnt/parallella.bit.bin

Mine is booting with whatever bitstream is flashed, and i'm not sure
how to actually look at what that is.

'fpga dump 0 0x10000000 0x1000000' doesn't do what I expect it to
(target memory isn't modified).


-Olof

Re: [PATCH v2 00/11] ARM: dts: zynq: Prepare Parallella

[Michal Simek]

On 10/21/2014 11:18 PM, Olof Johansson wrote:
> On Tue, Oct 21, 2014 at 2:07 PM, Andreas Färber <afaerber@suse.de> wrote:
>> Am 21.10.2014 um 23:01 schrieb Olof Johansson:
>>> On Tue, Oct 21, 2014 at 1:52 PM, Andreas Färber <afaerber@suse.de> wrote:
>>>> Am 18.10.2014 um 06:28 schrieb Olof Johansson:
>>>>> I did a test run with yesterday's -next It looks like networking isn't
>>>>> working there at the moment, clock related. Same happens with 3.17 and
>>>>> latest mainline, config multi_v7_defconfig:
>>>>>
>>>>> [WARN] [    7.943648] macb e000b000.ethernet eth0: unable to generate
>>>>> target frequency: 125000000 Hz
>>>>> [WARN] [   10.948681] macb e000b000.ethernet eth0: unable to generate
>>>>> target frequency: 125000000 Hz
>>>>
>>>> I am unable to reproduce this in my setup - at Linus' tip
>>>> c2661b806092d8ea2dccb7b02b65776555e0ee47 (v3.18-rc1-68-gc2661b8), make
>>>> oldconfig'ing my /proc/config.gz.
>>>>
>>>> Sören, in light of your explanations, should I be expecting problems
>>>> with 1GbE or with 100MbE? My board is connected to a 1GbE switch.
>>>
>>> My board might have old firmware/bitstream on it? It reports as:
>>>
>>> U-Boot 2012.10-00003-g792c31c (Jan 03 2014 - 12:24:08)
>>
>> Mine reports the same version.
>>
>> sha512sum of non-headless bitstream:
>> decb37222a7da0de39b1c1eb95714500cc006506cc86d85ed9c6c7b30c7cd7b91ef3592b886311f4285b5ce0079b4ffcd83f91ae275435ac15cefefe7db00b08
>>  /mnt/parallella.bit.bin
> 
> Mine is booting with whatever bitstream is flashed, and i'm not sure
> how to actually look at what that is.
> 
> 'fpga dump 0 0x10000000 0x1000000' doesn't do what I expect it to
> (target memory isn't modified).

Dumping bitstream is not supported in u-boot that's why it won't work.

I have tested the board I have here and no problem to run at 100 or 1000Mbit/s.

[  188.898563] macb e000b000.ethernet eth0: link down
[  192.898600] macb e000b000.ethernet eth0: link up (1000/Full)
[  708.898556] macb e000b000.ethernet eth0: link down
[  715.898696] macb e000b000.ethernet eth0: link up (100/Full)
[  749.909764] macb e000b000.ethernet eth0: link down
[  761.915769] macb e000b000.ethernet eth0: link up (1000/Full)

I will send you my boot.bin in private email which you can try.

Thanks,
Michal






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