From mboxrd@z Thu Jan 1 00:00:00 1970 From: Subject: [PATCHv10 2/2] arm: dts: Add Altera SDRAM EDAC bindings & devicetree entries. Date: Mon, 11 Aug 2014 10:18:13 -0500 Message-ID: <1407770293-27190-3-git-send-email-tthayer@opensource.altera.com> References: <1407770293-27190-1-git-send-email-tthayer@opensource.altera.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1407770293-27190-1-git-send-email-tthayer@opensource.altera.com> Sender: linux-kernel-owner@vger.kernel.org To: robherring2@gmail.com, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, rob@landley.net, linux@arm.linux.org.uk, atull@opensource.altera.com, delicious.quinoa@gmail.com, dinguyen@opensource.altera.com, dougthompson@xmission.com, grant.likely@linaro.org, bp@alien8.de, sameo@linux.intel.com, lee.jones@linaro.org Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tthayer.linux@gmail.com, tthayer@opensource.altera.com List-Id: devicetree@vger.kernel.org From: Thor Thayer Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC project. Signed-off-by: Thor Thayer --- v2: Changes to SoC SDRAM EDAC code. v3: Implement code suggestions for SDRAM EDAC code. v4: Remove syscon from SDRAM controller bindings. v5: No Change, bump version for consistency. v6: Only map the ctrlcfg register as syscon. v7: No change. Bump for consistency. v8: No change. Bump for consistency. v9: Changes to support a MFD SDRAM controller with nested EDAC. v10: Revert to using syscon based on feedback. --- .../bindings/arm/altera/socfpga-sdram-edac.txt | 15 +++++++++++++++ arch/arm/boot/dts/socfpga.dtsi | 11 +++++++++++ 2 files changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt new file mode 100644 index 0000000..d0ce01d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt @@ -0,0 +1,15 @@ +Altera SOCFPGA SDRAM Error Detection & Correction [EDAC] +The EDAC accesses a range of registers in the SDRAM controller. + +Required properties: +- compatible : should contain "altr,sdram-edac"; +- altr,sdr-syscon : phandle of the sdr module +- interrupts : Should contain the SDRAM ECC IRQ in the + appropriate format for the IRQ controller. + +Example: + sdramedac { + compatible = "altr,sdram-edac"; + altr,sdr-syscon = <&sdr>; + interrupts = <0 39 4>; + }; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 4676f25..45b361e 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -603,6 +603,17 @@ }; }; + sdr: sdr@ffc25000 { + compatible = "syscon"; + reg = <0xffc25000 0x1000>; + }; + + sdramedac { + compatible = "altr,sdram-edac"; + altr,sdr-syscon = <&sdr>; + interrupts = <0 39 4>; + }; + L2: l2-cache@fffef000 { compatible = "arm,pl310-cache"; reg = <0xfffef000 0x1000>; -- 1.7.9.5