[PATCH v2 0/5] ARM: add Broadcom BCM63138 support

[PATCH v2 0/5] ARM: add Broadcom BCM63138 support

[Florian Fainelli]

Hi all,

This patchset adds very minimal support for the BCM63138 SoC which is
a xDSL SoC using a dual Cortex A9 CPU complex.

Future work will focus on:

- clock device/driver/providers
- SMP support
- enabling more existing bcm63xx drivers to be DT enabled

Florian Fainelli (5):
  ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC
  ARM: BCM63XX: add low-level UART debug support
  ARM: BCM63XX: add BCM63138 minimal Device Tree
  ARM: BCM63XX: add BCM963138DVT Reference platform DTS
  MAINTAINERS: add entry for the Broadcom BCM63xx ARM SoCs

 .../devicetree/bindings/arm/bcm/bcm63138.txt       |   9 ++
 MAINTAINERS                                        |   8 ++
 arch/arm/Kconfig.debug                             |  18 ++-
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/bcm63138.dtsi                    | 134 +++++++++++++++++++++
 arch/arm/boot/dts/bcm963138dvt.dts                 |  25 ++++
 arch/arm/include/debug/bcm63xx.S                   |  33 +++++
 arch/arm/mach-bcm/Kconfig                          |  17 +++
 arch/arm/mach-bcm/Makefile                         |   3 +
 arch/arm/mach-bcm/bcm63xx.c                        |  41 +++++++
 10 files changed, 287 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/bcm63138.txt
 create mode 100644 arch/arm/boot/dts/bcm63138.dtsi
 create mode 100644 arch/arm/boot/dts/bcm963138dvt.dts
 create mode 100644 arch/arm/include/debug/bcm63xx.S
 create mode 100644 arch/arm/mach-bcm/bcm63xx.c

-- 
1.9.1

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[PATCH v2 1/5] ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC

[Florian Fainelli]

This patch adds basic support for the Broadcom BCM63138 DSL SoC which is
using a dual-core Cortex A9 system. Add the very minimum required code
boot Linux on this SoC.

Signed-off-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
Changes in v2:
- removed custom map_io() function since it is not necessary
- removed custom PL310 cache controller initialization, this has
  been submitted as part of more general patch

 .../devicetree/bindings/arm/bcm/bcm63138.txt       |  9 +++++
 arch/arm/mach-bcm/Kconfig                          | 17 +++++++++
 arch/arm/mach-bcm/Makefile                         |  3 ++
 arch/arm/mach-bcm/bcm63xx.c                        | 41 ++++++++++++++++++++++
 4 files changed, 70 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/bcm63138.txt
 create mode 100644 arch/arm/mach-bcm/bcm63xx.c

diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm63138.txt b/Documentation/devicetree/bindings/arm/bcm/bcm63138.txt
new file mode 100644
index 000000000000..bd49987a8812
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/bcm63138.txt
@@ -0,0 +1,9 @@
+Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
+-----------------------------------------------------------
+
+Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
+following properties:
+
+Required root node property:
+
+compatible: should be "brcm,bcm63138"
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index fc938005ad39..2abad742516d 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -99,6 +99,23 @@ config ARCH_BCM_5301X
 	  different SoC or with the older BCM47XX and BCM53XX based
 	  network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
 
+config ARCH_BCM_63XX
+	bool "Broadcom BCM63xx DSL SoC" if ARCH_MULTI_V7
+	depends on MMU
+	select ARM_ERRATA_754322
+	select ARM_ERRATA_764369 if SMP
+	select ARM_GIC
+	select ARM_GLOBAL_TIMER
+	select CACHE_L2X0
+	select HAVE_ARM_ARCH_TIMER
+	select HAVE_ARM_TWD if SMP
+	select HAVE_ARM_SCU if SMP
+	select HAVE_SMP
+	help
+	  This enables support for systems based on Broadcom DSL SoCs.
+	  It currently supports the 'BCM63XX' ARM-based family, which includes
+	  the BCM63138 variant.
+
 config ARCH_BRCMSTB
 	bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7
 	depends on MMU
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 67c492aabf4d..cbbb0be54554 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -34,6 +34,9 @@ obj-$(CONFIG_ARCH_BCM2835)	+= board_bcm2835.o
 # BCM5301X
 obj-$(CONFIG_ARCH_BCM_5301X)	+= bcm_5301x.o
 
+# BCM63XXx
+obj-$(CONFIG_ARCH_BCM_63XX)	:= bcm63xx.o
+
 ifeq ($(CONFIG_ARCH_BRCMSTB),y)
 obj-y				+= brcmstb.o
 obj-$(CONFIG_SMP)		+= headsmp-brcmstb.o platsmp-brcmstb.o
diff --git a/arch/arm/mach-bcm/bcm63xx.c b/arch/arm/mach-bcm/bcm63xx.c
new file mode 100644
index 000000000000..be69f414ebf0
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm63xx.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/of_platform.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/clocksource.h>
+#include <linux/irqchip.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/hardware/cache-l2x0.h>
+
+static void __init bcm63xx_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table, NULL,
+		&platform_bus);
+	l2x0_of_init(0, ~0);
+}
+
+static const char * const bcm63xx_dt_compat[] = {
+	"brcm,bcm63138",
+	NULL
+};
+
+DT_MACHINE_START(BCM63XXX_DT, "BCM63xx DSL SoC")
+	.init_machine	= bcm63xx_init,
+	.dt_compat	= bcm63xx_dt_compat,
+MACHINE_END
-- 
1.9.1

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[PATCH v2 2/5] ARM: BCM63XX: add low-level UART debug support

[Florian Fainelli]

Broadcom BCM63xx DSL SoCs have a different UART implementation for which
we need specially crafted low-level debug assembly code to support. Add
support for this using the standard definitions provided in
include/linux/serial_bcm63xx.h (shared with their MIPS counterparts).

Signed-off-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
Changes in v2:
- rebased

 arch/arm/Kconfig.debug           | 18 ++++++++++++++++--
 arch/arm/include/debug/bcm63xx.S | 33 +++++++++++++++++++++++++++++++++
 2 files changed, 49 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/include/debug/bcm63xx.S

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index b11ad54f8d17..07e9dd5eda26 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -122,6 +122,11 @@ choice
 		  mobile SoCs in the Kona family of chips (e.g. bcm28155,
 		  bcm11351, etc...)
 
+	config DEBUG_BCM63XX
+		bool "Kernel low-level debugging on BCM63XX UART"
+		depends on ARCH_BCM_63XX
+		select DEBUG_UART_BCM63XX
+
 	config DEBUG_BERLIN_UART
 		bool "Marvell Berlin SoC Debug UART"
 		depends on ARCH_BERLIN
@@ -1038,6 +1043,7 @@ config DEBUG_LL_INCLUDE
 	default "debug/vf.S" if DEBUG_VF_UART
 	default "debug/vt8500.S" if DEBUG_VT8500_UART0
 	default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
+	default "debug/bcm63xx.S" if DEBUG_UART_BCM63XX
 	default "mach/debug-macro.S"
 
 # Compatibility options for PL01x
@@ -1057,6 +1063,10 @@ config DEBUG_UART_8250
 		ARCH_IOP33X || ARCH_IXP4XX || \
 		ARCH_LPC32XX || ARCH_MV78XX0 || ARCH_ORION5X || ARCH_RPC
 
+# Compatibility options for BCM63xx
+config DEBUG_UART_BCM63XX
+	def_bool ARCH_BCM_63XX
+
 config DEBUG_UART_PHYS
 	hex "Physical base address of debug UART"
 	default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0
@@ -1122,11 +1132,13 @@ config DEBUG_UART_PHYS
 	default 0xffc02000 if DEBUG_SOCFPGA_UART
 	default 0xffd82340 if ARCH_IOP13XX
 	default 0xfff36000 if DEBUG_HIGHBANK_UART
+	default 0xfffe8600 if DEBUG_UART_BCM63XX
 	default 0xfffff700 if ARCH_IOP33X
 	depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
 		DEBUG_LL_UART_EFM32 || \
 		DEBUG_UART_8250 || DEBUG_UART_PL01X || \
-		DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART
+		DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
+		DEBUG_UART_BCM63XX
 
 config DEBUG_UART_VIRT
 	hex "Virtual base address of debug UART"
@@ -1157,6 +1169,7 @@ config DEBUG_UART_VIRT
 	default 0xfa71e000 if DEBUG_QCOM_UARTDM
 	default 0xfb009000 if DEBUG_REALVIEW_STD_PORT
 	default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT
+	default 0xfcfe8600 if DEBUG_UART_BCM63XX
 	default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX
 	default 0xfd000000 if ARCH_SPEAR13XX
 	default 0xfd012000 if ARCH_MV78XX0
@@ -1194,7 +1207,8 @@ config DEBUG_UART_VIRT
 	default DEBUG_UART_PHYS if !MMU
 	depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
 		DEBUG_UART_8250 || DEBUG_UART_PL01X || \
-		DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART
+		DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
+		DEBUG_UART_BCM63XX
 
 config DEBUG_UART_8250_SHIFT
 	int "Register offset shift for the 8250 debug UART"
diff --git a/arch/arm/include/debug/bcm63xx.S b/arch/arm/include/debug/bcm63xx.S
new file mode 100644
index 000000000000..e7164d570f44
--- /dev/null
+++ b/arch/arm/include/debug/bcm63xx.S
@@ -0,0 +1,33 @@
+/*
+ * Broadcom BCM63xx low-level UART debug
+ *
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/serial_bcm63xx.h>
+
+	.macro	addruart, rp, rv, tmp
+	ldr	\rp, =CONFIG_DEBUG_UART_PHYS
+	ldr	\rv, =CONFIG_DEBUG_UART_VIRT
+	.endm
+
+	.macro	senduart, rd, rx
+	/* word access do not work */
+	strb	\rd, [\rx, #UART_FIFO_REG]
+	.endm
+
+	.macro	waituart, rd, rx
+1001:	ldr	\rd, [\rx, #UART_IR_REG]
+	tst	\rd, #(1 << UART_IR_TXEMPTY)
+	beq	1001b
+	.endm
+
+	.macro	busyuart, rd, rx
+1002:	ldr	\rd, [\rx, #UART_IR_REG]
+	tst	\rd, #(1 << UART_IR_TXTRESH)
+	beq	1002b
+	.endm
-- 
1.9.1

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[PATCH v2 3/5] ARM: BCM63XX: add BCM63138 minimal Device Tree

[Florian Fainelli]

Add a very minimalistic BCM63138 Device Tree include file which
describes the BCM63138 SoC with only the basic set of required
peripherals:

- Cortex A9 CPUs
- ARM GIC
- ARM SCU
- PL310 Level-2 cache controller
- ARM TWD & Global timers
- ARM TWD watchdog
- legacy MIPS bus (UBUS)
- BCM6345-style UARTs (disabled by default)

Since the PL310 L2 cache controller does not come out of reset with
correct default values, we need to override the 'cache-sets' and
'cache-size' properties to get its geometry right.

Signed-off-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
Changes in v2:
- removed buses 'reg' properties since they are unused
- align buses 'ranges' properties on a nicer boundary
- moved mpcore peripherals one level higher in the axi bus
- added uart nodes since we have a driver for it (bcm63xx_uart)

 arch/arm/boot/dts/bcm63138.dtsi | 134 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 134 insertions(+)
 create mode 100644 arch/arm/boot/dts/bcm63138.dtsi

diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi
new file mode 100644
index 000000000000..b7ce4da3d742
--- /dev/null
+++ b/arch/arm/boot/dts/bcm63138.dtsi
@@ -0,0 +1,134 @@
+/*
+ * Broadcom BCM63138 DSL SoCs Device Tree
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,bcm63138";
+	model = "Broadcom BCM63138 DSL SoC";
+	interrupt-parent = <&gic>;
+
+	aliases {
+		uart0 = &serial0;
+		uart1 = &serial1;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <1>;
+		};
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		arm_timer_clk: arm_timer_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <500000000>;
+		};
+
+		periph_clk: periph_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+			clock-output-names = "periph";
+		};
+	};
+
+	/* ARM bus */
+	axi@80000000 {
+		compatible = "simple-bus";
+		ranges = <0 0x80000000 0x84000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		L2: cache-controller@1d000 {
+			compatible = "arm,pl310-cache";
+			reg = <0x1d000 0x1000>;
+			cache-unified;
+			cache-level = <2>;
+			cache-sets = <16>;
+			cache-size = <0x80000>;
+			interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		scu: scu@1e000 {
+			compatible = "arm,cortex-a9-scu";
+			reg = <0x1e000 0x100>;
+		};
+
+		gic: interrupt-controller@1e100 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0x1f000 0x1000
+				0x1e100 0x100>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+		};
+
+		global_timer: timer@1e200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x1e200 0x20>;
+			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		local_timer: local-timer@1e600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x1e600 0x20>;
+			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		twd_watchdog: watchdog@1e620 {
+			compatible = "arm,cortex-a9-twd-wdt";
+			reg = <0x1e620 0x20>;
+			interupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+
+	/* Legacy UBUS base */
+	ubus@fffe8000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xfffe8000 0x8100>;
+
+		serial0: uart@600 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x600 0x1b>;
+			interrupts = <GIC_SPI 32 0>;
+			clocks = <&periph_clk>;
+			clock-names = "periph";
+			status = "disabled";
+		};
+
+		serial1: uart@620 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x620 0x1b>;
+			interrupts = <GIC_SPI 33 0>;
+			clocks = <&periph_clk>;
+			clock-names = "periph";
+			status = "disabled";
+		};
+	};
+};
-- 
1.9.1

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[PATCH v2 4/5] ARM: BCM63XX: add BCM963138DVT Reference platform DTS

[Florian Fainelli]

Add a DTS file for the Broadcom BCM963138DVT reference platform board
which leverages the bcm63138.dtsi SoC DTSi file.

Signed-off-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
Changes in v2:
- consistently use the prefix 963138 since this is a reference board
- enable UARTs for that reference board so we get to a prompt

 arch/arm/boot/dts/Makefile         |  1 +
 arch/arm/boot/dts/bcm963138dvt.dts | 25 +++++++++++++++++++++++++
 2 files changed, 26 insertions(+)
 create mode 100644 arch/arm/boot/dts/bcm963138dvt.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b8c5cd3ddeb9..7ffe736abcf8 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -53,6 +53,7 @@ dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
 dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
+dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
 	bcm21664-garnet.dtb
 dtb-$(CONFIG_ARCH_BERLIN) += \
diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/bcm963138dvt.dts
new file mode 100644
index 000000000000..c5f7620881f7
--- /dev/null
+++ b/arch/arm/boot/dts/bcm963138dvt.dts
@@ -0,0 +1,25 @@
+/*
+ * Broadcom BCM63138 Reference Board DTS
+ */
+
+/dts-v1/;
+
+#include "bcm63138.dtsi"
+
+/ {
+	compatible = "brcm,BCM963138DVT", "brcm,bcm63138";
+	model = "Broadcom BCM963138DVT";
+
+	memory {
+		reg = <0x0 0x08000000>;
+	};
+
+};
+
+&serial0 {
+	status = "okay";
+};
+
+&serial1 {
+	status = "okay";
+};
-- 
1.9.1

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[PATCH v2 5/5] MAINTAINERS: add entry for the Broadcom BCM63xx ARM SoCs

[Florian Fainelli]

Add a MAINTAINERS entry covering all the Broadcom BCM63xx ARM DSL SoCs
files along with the relevant git tree and mailing-list.

Signed-off-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
Changes in v2:
- rebased against latest changes

 MAINTAINERS | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 7e2eb4c646e3..2075bb579853 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2013,6 +2013,14 @@ F:	arch/arm/mach-bcm/bcm_5301x.c
 F:	arch/arm/boot/dts/bcm5301x.dtsi
 F:	arch/arm/boot/dts/bcm470*
 
+BROADCOM BCM63XX ARM ARCHITECTURE
+M:	Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+L:	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
+T:	git git://git.github.com/broadcom/arm-bcm63xx
+S:	Maintained
+F:	arch/arm/mach-bcm/bcm63xx.c
+F:	arch/arm/include/debug/bcm63xx.S
+
 BROADCOM BCM7XXX ARM ARCHITECTURE
 M:	Marc Carino <marc.ceeeee-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
 M:	Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
-- 
1.9.1

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Re: [PATCH v2 3/5] ARM: BCM63XX: add BCM63138 minimal Device Tree

[Florian Fainelli]

2014-08-14 17:11 GMT-07:00 Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>:
> Add a very minimalistic BCM63138 Device Tree include file which
> describes the BCM63138 SoC with only the basic set of required
> peripherals:
>
> - Cortex A9 CPUs
> - ARM GIC
> - ARM SCU
> - PL310 Level-2 cache controller
> - ARM TWD & Global timers
> - ARM TWD watchdog
> - legacy MIPS bus (UBUS)
> - BCM6345-style UARTs (disabled by default)
>
> Since the PL310 L2 cache controller does not come out of reset with
> correct default values, we need to override the 'cache-sets' and
> 'cache-size' properties to get its geometry right.
>
> Signed-off-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

[snip]

> +       /* ARM bus */
> +       axi@80000000 {
> +               compatible = "simple-bus";
> +               ranges = <0 0x80000000 0x84000>;

I made a typo here, the range declared here is narrower than it really
is, I will re-submit this after getting some more feedback. Thanks!
--
Florian
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Re: [PATCH v2 1/5] ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC

[Arnd Bergmann]

On Thursday 14 August 2014 17:11:23 Florian Fainelli wrote:
> +static void __init bcm63xx_init(void)
> +{
> +       of_platform_populate(NULL, of_default_bus_match_table, NULL,
> +               &platform_bus);
> +       l2x0_of_init(0, ~0);
> +}
> +
> +static const char * const bcm63xx_dt_compat[] = {
> +       "brcm,bcm63138",
> +       NULL
> +};
> +
> +DT_MACHINE_START(BCM63XXX_DT, "BCM63xx DSL SoC")
> +       .init_machine   = bcm63xx_init,
> +       .dt_compat      = bcm63xx_dt_compat,
> +MACHINE_END
> 

You should be able to remove that bcm63xx_init() function if you add
the l2c_aux_val/l2c_aux_mask settings in the machine descriptor
instead.

	Arnd
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Re: [PATCH v2 4/5] ARM: BCM63XX: add BCM963138DVT Reference platform DTS

[Arnd Bergmann]

On Thursday 14 August 2014 17:11:26 Florian Fainelli wrote:
> +/ {
> +       compatible = "brcm,BCM963138DVT", "brcm,bcm63138";
> +       model = "Broadcom BCM963138DVT";
> +
> +       memory {
> +               reg = <0x0 0x08000000>;
> +       };
> +
> +};
> +
> +&serial0 {
> +       status = "okay";
> +};
> +
> +&serial1 {
> +       status = "okay";
> +};
> 

You should probably add a 'stdout-path' property in the aliases node
to pick the uart that is used for the console. It might require
a change to the driver as well.

	Arnd
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Re: [PATCH v2 3/5] ARM: BCM63XX: add BCM63138 minimal Device Tree

[Arnd Bergmann]

On Thursday 14 August 2014 17:11:25 Florian Fainelli wrote:
> Add a very minimalistic BCM63138 Device Tree include file which
> describes the BCM63138 SoC with only the basic set of required
> peripherals:
> 
> - Cortex A9 CPUs
> - ARM GIC
> - ARM SCU
> - PL310 Level-2 cache controller
> - ARM TWD & Global timers
> - ARM TWD watchdog
> - legacy MIPS bus (UBUS)
> - BCM6345-style UARTs (disabled by default)
> 
> Since the PL310 L2 cache controller does not come out of reset with
> correct default values, we need to override the 'cache-sets' and
> 'cache-size' properties to get its geometry right.
> 
> Signed-off-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Acked-by: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>

Looks all good to me except one tiny detail:

> +	/* Legacy UBUS base */
> +	ubus@fffe8000 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0xfffe8000 0x8100>;
> +
> +		serial0: uart@600 {
> +			compatible = "brcm,bcm6345-uart";
> +			reg = <0x600 0x1b>;
> +			interrupts = <GIC_SPI 32 0>;
> +			clocks = <&periph_clk>;
> +			clock-names = "periph";
> +			status = "disabled";
> +		};

The recommended name for a uart is serial@600, not uart@600.
We are highly inconsistent with the existing dts files, so I'm
not blaming you, I'm just trying to make new files do it the
right way.

	Arnd
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