[PATCH v3 1/5] of: Add NVIDIA Tegra Legacy Interrupt Controller binding

[PATCH v3 1/5] of: Add NVIDIA Tegra Legacy Interrupt Controller binding

[Thierry Reding]

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by
the AVP coprocessor and can also serve as a backup for the ARM Cortex
CPU's local interrupt controller (GIC).

The LIC is subdivided into multiple identical units, each handling 32
possible interrupt sources.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
Changes in v3:
- bracket individual tuples in the "reg" property

 .../interrupt-controller/nvidia,tegra20-ictlr.txt     | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt

diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
new file mode 100644
index 000000000000..1639389b7360
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
@@ -0,0 +1,19 @@
+NVIDIA Tegra Legacy Interrupt Controller
+
+The legacy interrupt controller is divided into units that serve 32 interrupts
+each. Tegra20 implements four units, whereas Tegra30 and later implement five.
+
+Required properties:
+- compatible: "nvidia,tegra<chip>-ictlr"
+- reg: Physical base address and length of the controller's registers. There
+  should be one entry for each unit.
+
+Example:
+
+	interrupt-controller@60004000 {
+		compatible = "nvidia,tegra20-ictlr";
+		reg = <0x60004000 0x40>, /* primary controller */
+		      <0x60004100 0x40>, /* secondary controller */
+		      <0x60004200 0x40>, /* tertiary controller */
+		      <0x60004300 0x40>; /* quaternary controller */
+	};
-- 
2.0.4

Re: [PATCH v3 1/5] of: Add NVIDIA Tegra Legacy Interrupt Controller binding

[Stephen Warren]

On 08/26/2014 12:41 AM, Thierry Reding wrote:
> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by
> the AVP coprocessor and can also serve as a backup for the ARM Cortex
> CPU's local interrupt controller (GIC).
>
> The LIC is subdivided into multiple identical units, each handling 32
> possible interrupt sources.

If I apply this series without patch 2, which is necessary to test the 
support for compatibility with old DTs, then I get the following very 
early on in boot:

Other than that, I would apply this.

> [    0.000000] Preemptible hierarchical RCU implementation.
> [    0.000000] NR_IRQS:16 nr_irqs:16 16
> [    0.000000] ------------[ cut here ]------------
> [    0.000000] WARNING: CPU: 0 PID: 0 at drivers/soc/tegra/fuse/tegra-apbmisc.c:42 tegra_get_chip_id+0x30/0x44()
> [    0.000000] Tegra Chip ID not yet available
> [    0.000000] Modules linked in:
> [    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.17.0-rc2-00016-g6a550998848e #32
> [    0.000000] [<c00157a0>] (unwind_backtrace) from [<c0011344>] (show_stack+0x10/0x14)
> [    0.000000] [<c0011344>] (show_stack) from [<c06045e8>] (dump_stack+0x84/0xd0)
> [    0.000000] [<c06045e8>] (dump_stack) from [<c0024f44>] (warn_slowpath_common+0x64/0x88)
> [    0.000000] [<c0024f44>] (warn_slowpath_common) from [<c0024ffc>] (warn_slowpath_fmt+0x30/0x40)
> [    0.000000] [<c0024ffc>] (warn_slowpath_fmt) from [<c0267acc>] (tegra_get_chip_id+0x30/0x44)
> [    0.000000] [<c0267acc>] (tegra_get_chip_id) from [<c08576a8>] (tegra_init_irq+0xb0/0x2d0)
> [    0.000000] [<c08576a8>] (tegra_init_irq) from [<c0857d60>] (tegra_dt_init_irq+0x8/0x14)
> [    0.000000] [<c0857d60>] (tegra_dt_init_irq) from [<c08525a8>] (init_IRQ+0x28/0x7c)
> [    0.000000] [<c08525a8>] (init_IRQ) from [<c0850a48>] (start_kernel+0x21c/0x3a8)
> [    0.000000] [<c0850a48>] (start_kernel) from [<80008074>] (0x80008074)
> [    0.000000] ---[ end trace cb88537fdc8fa200 ]---
> [    0.000000] ------------[ cut here ]------------
> [    0.000000] WARNING: CPU: 0 PID: 0 at arch/arm/mach-tegra/irq.c:343 tegra_init_irq+0x184/0x2d0()
> [    0.000000] Found 5 interrupt controllers; expected 4.
> [    0.000000] Modules linked in:
> [    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G        W      3.17.0-rc2-00016-g6a550998848e #32
> [    0.000000] [<c00157a0>] (unwind_backtrace) from [<c0011344>] (show_stack+0x10/0x14)
> [    0.000000] [<c0011344>] (show_stack) from [<c06045e8>] (dump_stack+0x84/0xd0)
> [    0.000000] [<c06045e8>] (dump_stack) from [<c0024f44>] (warn_slowpath_common+0x64/0x88)
> [    0.000000] [<c0024f44>] (warn_slowpath_common) from [<c0024ffc>] (warn_slowpath_fmt+0x30/0x40)
> [    0.000000] [<c0024ffc>] (warn_slowpath_fmt) from [<c085777c>] (tegra_init_irq+0x184/0x2d0)
> [    0.000000] [<c085777c>] (tegra_init_irq) from [<c0857d60>] (tegra_dt_init_irq+0x8/0x14)
> [    0.000000] [<c0857d60>] (tegra_dt_init_irq) from [<c08525a8>] (init_IRQ+0x28/0x7c)
> [    0.000000] [<c08525a8>] (init_IRQ) from [<c0850a48>] (start_kernel+0x21c/0x3a8)
> [    0.000000] [<c0850a48>] (start_kernel) from [<80008074>] (0x80008074)
> [    0.000000] ---[ end trace cb88537fdc8fa201 ]---

Re: [PATCH v3 1/5] of: Add NVIDIA Tegra Legacy Interrupt Controller binding

[Thierry Reding]

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On Tue, Aug 26, 2014 at 11:59:13AM -0600, Stephen Warren wrote:
> On 08/26/2014 12:41 AM, Thierry Reding wrote:
> >From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> >
> >The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by
> >the AVP coprocessor and can also serve as a backup for the ARM Cortex
> >CPU's local interrupt controller (GIC).
> >
> >The LIC is subdivided into multiple identical units, each handling 32
> >possible interrupt sources.
> 
> If I apply this series without patch 2, which is necessary to test the
> support for compatibility with old DTs, then I get the following very early
> on in boot:
> 
> Other than that, I would apply this.

Ugh... this is because before patch 3 the code would always initialize
all five controllers, even on Tegra20 where it doesn't exist. Patch 3
adds a check for that based on the chip ID, which due to other patches
merged for v3.17 isn't available at this point. One solution would be
for this to be moved into an initcall to make sure it's called after
initialization of the fuse driver so that tegra_get_chip_id() can read
the chip ID. But since you're not at all a fan of that I guess the best
we can do is to match on the top-level machine compatible instead of
using the chip ID.

Thierry

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