From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Bresticker Subject: [PATCH v2 04/16] MIPS: smp-cps: Enable all hardware interrupts on secondary CPUs Date: Fri, 5 Sep 2014 10:30:06 -0700 Message-ID: <1409938218-9026-5-git-send-email-abrestic@chromium.org> References: <1409938218-9026-1-git-send-email-abrestic@chromium.org> Return-path: In-Reply-To: <1409938218-9026-1-git-send-email-abrestic@chromium.org> Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: Ralf Baechle , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Thomas Gleixner , Jason Cooper Cc: Andrew Bresticker , Jeffrey Deans , Markos Chandras , Paul Burton , Arnd Bergmann , John Crispin , David Daney , linux-mips@linux-mips.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: devicetree@vger.kernel.org Currently interrupt vectors 2 and 5 are left disabled on secondary CPUs. Since systems using CPS must also have a GIC, which is responsible for routing all external interrupts and can map them to any hardware interrupt vector, enable the remaining vectors. The two software interrupt vectors are left disabled since they are not used with CPS. Signed-off-by: Andrew Bresticker --- New for v2. --- arch/mips/kernel/smp-cps.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index e6e16a1..cd20aca 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -273,8 +273,8 @@ static void cps_init_secondary(void) if (cpu_has_mipsmt) dmt(); - change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | - STATUSF_IP6 | STATUSF_IP7); + change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | + STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7); } static void cps_smp_finish(void) -- 2.1.0.rc2.206.gedb03e5