From: Andrew Bresticker <abrestic@chromium.org>
To: Ralf Baechle <ralf@linux-mips.org>,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Bresticker <abrestic@chromium.org>,
Jeffrey Deans <jeffrey.deans@imgtec.com>,
Markos Chandras <markos.chandras@imgtec.com>,
Paul Burton <paul.burton@imgtec.com>,
Arnd Bergmann <arnd@arndb.de>, John Crispin <blogic@openwrt.org>,
David Daney <ddaney.cavm@gmail.com>,
linux-mips@linux-mips.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v2 06/16] MIPS: Move MIPS_GIC_IRQ_BASE into platform irq.h
Date: Fri, 5 Sep 2014 10:30:08 -0700 [thread overview]
Message-ID: <1409938218-9026-7-git-send-email-abrestic@chromium.org> (raw)
In-Reply-To: <1409938218-9026-1-git-send-email-abrestic@chromium.org>
Define a generic MIPS_GIC_IRQ_BASE which is suitable for Malta and
the upcoming Danube board in <mach-generic/irq.h>. Since Sead-3 is
different and uses a MIPS_GIC_IRQ_BASE equal to the CPU IRQ base (0),
define its MIPS_GIC_IRQ_BASE in <mach-sead3/irq.h>.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
---
No changes from v1.
---
arch/mips/include/asm/mach-generic/irq.h | 6 ++++++
arch/mips/include/asm/mach-sead3/irq.h | 1 +
arch/mips/include/asm/mips-boards/maltaint.h | 2 --
arch/mips/include/asm/mips-boards/sead3int.h | 2 --
4 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/mips/include/asm/mach-generic/irq.h b/arch/mips/include/asm/mach-generic/irq.h
index 139cd20..050e18b 100644
--- a/arch/mips/include/asm/mach-generic/irq.h
+++ b/arch/mips/include/asm/mach-generic/irq.h
@@ -36,4 +36,10 @@
#endif /* CONFIG_IRQ_CPU */
+#ifdef CONFIG_MIPS_GIC
+#ifndef MIPS_GIC_IRQ_BASE
+#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
+#endif
+#endif /* CONFIG_MIPS_GIC */
+
#endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-sead3/irq.h b/arch/mips/include/asm/mach-sead3/irq.h
index d8106f7..52c75d5 100644
--- a/arch/mips/include/asm/mach-sead3/irq.h
+++ b/arch/mips/include/asm/mach-sead3/irq.h
@@ -1,6 +1,7 @@
#ifndef __ASM_MACH_MIPS_IRQ_H
#define __ASM_MACH_MIPS_IRQ_H
+#define MIPS_GIC_IRQ_BASE 0
#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
#define NR_IRQS 256
diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h
index e330732..9d23343 100644
--- a/arch/mips/include/asm/mips-boards/maltaint.h
+++ b/arch/mips/include/asm/mips-boards/maltaint.h
@@ -10,8 +10,6 @@
#ifndef _MIPS_MALTAINT_H
#define _MIPS_MALTAINT_H
-#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
-
/*
* Interrupts 0..15 are used for Malta ISA compatible interrupts
*/
diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h
index 6b17aaf..11ebec9 100644
--- a/arch/mips/include/asm/mips-boards/sead3int.h
+++ b/arch/mips/include/asm/mips-boards/sead3int.h
@@ -14,6 +14,4 @@
#define GIC_BASE_ADDR 0x1b1c0000
#define GIC_ADDRSPACE_SZ (128 * 1024)
-#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 0)
-
#endif /* !(_MIPS_SEAD3INT_H) */
--
2.1.0.rc2.206.gedb03e5
next prev parent reply other threads:[~2014-09-05 17:30 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-05 17:30 [PATCH v2 00/16] MIPS: GIC device-tree support Andrew Bresticker
[not found] ` <1409938218-9026-1-git-send-email-abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2014-09-05 17:30 ` [PATCH v2 01/16] MIPS: Provide a generic plat_irq_dispatch Andrew Bresticker
[not found] ` <1409938218-9026-2-git-send-email-abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2014-09-05 18:51 ` Thomas Gleixner
2014-09-05 21:02 ` Andrew Bresticker
2014-09-05 17:30 ` [PATCH v2 09/16] irqchip: mips-gic: Fix gic_set_affinity() return value Andrew Bresticker
2014-09-05 17:30 ` [PATCH v2 13/16] irqchip: mips-gic: Add generic IPI support when using DT Andrew Bresticker
2014-09-05 17:30 ` [PATCH v2 02/16] MIPS: Set vint handler when mapping CPU interrupts Andrew Bresticker
2014-09-05 17:30 ` [PATCH v2 03/16] MIPS: Export CPU IRQ domain Andrew Bresticker
2014-09-05 17:30 ` [PATCH v2 04/16] MIPS: smp-cps: Enable all hardware interrupts on secondary CPUs Andrew Bresticker
2014-09-05 17:30 ` [PATCH v2 05/16] MIPS: Move GIC to drivers/irqchip/ Andrew Bresticker
2014-09-05 17:30 ` Andrew Bresticker [this message]
2014-09-05 17:30 ` [PATCH v2 07/16] irqchip: mips-gic: Implement irq_set_type callback Andrew Bresticker
2014-09-05 17:30 ` [PATCH v2 08/16] irqchip: mips-gic: Implement generic irq_ack/irq_eoi callbacks Andrew Bresticker
2014-09-05 17:30 ` [PATCH v2 10/16] of: Add vendor prefix for MIPS Technologies, Inc Andrew Bresticker
[not found] ` <1409938218-9026-11-git-send-email-abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2014-09-22 14:23 ` Rob Herring
2014-09-22 16:28 ` Andrew Bresticker
2014-09-22 19:01 ` Kumar Gala
2014-09-22 19:30 ` Andrew Bresticker
[not found] ` <CAL1qeaEd2L8NUugh27hkGMa1aqaxviupRJnBd2+aru1wq6KKGg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-09-22 19:36 ` Kumar Gala
[not found] ` <C73B2A63-4396-462B-8172-F9CA32E573F1-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2014-09-22 19:43 ` Andrew Bresticker
2014-09-05 17:30 ` [PATCH v2 11/16] of: Add binding document for MIPS GIC Andrew Bresticker
2014-09-05 17:30 ` [PATCH v2 12/16] irqchip: mips-gic: Add device-tree support Andrew Bresticker
2014-09-05 17:30 ` [PATCH v2 14/16] irqchip: mips-gic: Support local interrupts Andrew Bresticker
2014-09-05 19:05 ` Thomas Gleixner
2014-09-05 21:50 ` Andrew Bresticker
2014-09-05 17:30 ` [PATCH v2 15/16] MIPS: GIC: Use local interrupts for timer Andrew Bresticker
[not found] ` <1409938218-9026-16-git-send-email-abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2014-09-05 19:08 ` Thomas Gleixner
2014-09-05 17:30 ` [PATCH v2 16/16] MIPS: Malta: Map GIC local interrupts Andrew Bresticker
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