From: Kevin Cernekee <cernekee-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
Cc: f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
mbizon-MmRyKUhfbQ9GWvitb5QawA@public.gmane.org,
jogo-p3rKhJxN3npAfugRpC6u6w@public.gmane.org,
jfraser-dY08KVG/lbpWk0Htik3J/w@public.gmane.org,
linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: [PATCH/RFC 02/17] MIPS: BMIPS: Align secondary boot sequence with latest firmware releases
Date: Mon, 20 Oct 2014 21:27:52 -0700 [thread overview]
Message-ID: <1413865687-15255-3-git-send-email-cernekee@gmail.com> (raw)
In-Reply-To: <1413865687-15255-1-git-send-email-cernekee-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On some older BMIPS5200 (dual core / quad thread) platforms, the
PROM code set up CPU2/CPU3 so they would be started through an NMI
instead of through the ACTION register. But this was incompatible with
some power management features that were later added, so the scheme was
changed so that Linux is fully responsible for booting CPU2/CPU3.
Signed-off-by: Kevin Cernekee <cernekee-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/mips/kernel/smp-bmips.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 06bb5ed..4e56911 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -213,17 +213,7 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle)
set_c0_brcm_cmt_ctrl(0x01);
break;
case CPU_BMIPS5000:
- if (cpu & 0x01)
- write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
- else {
- /*
- * core N thread 0 was already booted; just
- * pulse the NMI line
- */
- bmips_write_zscm_reg(0x210, 0xc0000000);
- udelay(10);
- bmips_write_zscm_reg(0x210, 0x00);
- }
+ write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
break;
}
cpumask_set_cpu(cpu, &bmips_booted_mask);
--
2.1.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
next prev parent reply other threads:[~2014-10-21 4:27 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-21 4:27 [PATCH/RFC 00/17] MIPS: BMIPS updates and BCM3384 platform support Kevin Cernekee
[not found] ` <1413865687-15255-1-git-send-email-cernekee-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-10-21 4:27 ` [PATCH/RFC 01/17] MIPS: BMIPS: Fix ".previous without corresponding .section" warnings Kevin Cernekee
2014-10-21 4:27 ` Kevin Cernekee [this message]
2014-10-21 4:27 ` [PATCH/RFC 03/17] MIPS: BMIPS: Introduce helper function to change the reset vector Kevin Cernekee
2014-10-21 4:27 ` [PATCH/RFC 04/17] MIPS: BMIPS: Allow BMIPS3300 to utilize SMP ebase relocation code Kevin Cernekee
2014-10-21 4:27 ` [PATCH/RFC 05/17] MIPS: BMIPS: Mask off timer IRQs when hot-unplugging a CPU Kevin Cernekee
2014-10-21 4:27 ` [PATCH/RFC 06/17] MIPS: BMIPS: Explicitly configure reset vectors prior to secondary boot Kevin Cernekee
2014-10-21 4:27 ` [PATCH/RFC 07/17] MIPS: Allow MIPS_CPU_SCACHE to be used with different line sizes Kevin Cernekee
2014-10-21 4:27 ` [PATCH/RFC 08/17] MIPS: BMIPS: Select the appropriate L1_CACHE_SHIFT for 438x and 5000 CPUs Kevin Cernekee
2014-10-21 4:27 ` [PATCH/RFC 09/17] MIPS: BMIPS: Let each platform customize the CPU1 IRQ mask Kevin Cernekee
2014-10-21 4:28 ` [PATCH/RFC 10/17] MIPS: BMIPS: Add special cache handling in c-r4k.c Kevin Cernekee
2014-10-21 4:28 ` [PATCH/RFC 11/17] MIPS: BMIPS: Add PRId for BMIPS5200 (Whirlwind) Kevin Cernekee
2014-10-21 4:28 ` [PATCH/RFC 12/17] MIPS: Create a helper function for DT setup Kevin Cernekee
2014-10-21 4:28 ` [PATCH/RFC 13/17] Documentation: DT: Add entries for BCM3384 and its peripherals Kevin Cernekee
2014-10-21 4:28 ` [PATCH/RFC 14/17] Documentation: DT: Add "mti" vendor prefix Kevin Cernekee
2014-10-21 4:28 ` [PATCH/RFC 15/17] MIPS: bcm3384: Initial commit of bcm3384 platform support Kevin Cernekee
2014-10-21 4:28 ` [PATCH/RFC 16/17] MAINTAINERS: Add entry for BCM33xx cable chips Kevin Cernekee
2014-10-21 4:28 ` [PATCH/RFC 17/17] MAINTAINERS: Add entry for bcm63xx/bcm33xx UDC gadget driver Kevin Cernekee
2014-10-21 19:31 ` [PATCH/RFC 00/17] MIPS: BMIPS updates and BCM3384 platform support Florian Fainelli
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1413865687-15255-3-git-send-email-cernekee@gmail.com \
--to=cernekee-re5jqeeqqe8avxtiumwx3w@public.gmane.org \
--cc=devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org \
--cc=jfraser-dY08KVG/lbpWk0Htik3J/w@public.gmane.org \
--cc=jogo-p3rKhJxN3npAfugRpC6u6w@public.gmane.org \
--cc=linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org \
--cc=mbizon-MmRyKUhfbQ9GWvitb5QawA@public.gmane.org \
--cc=ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).