From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sebastian Hesselbarth Subject: [PATCH RESEND 02/12] mmc: sdhci-pxav3: Respect MMC_DDR52 timing on uhs signaling Date: Tue, 21 Oct 2014 11:22:34 +0200 Message-ID: <1413883364-681-3-git-send-email-sebastian.hesselbarth@gmail.com> References: <1413883364-681-1-git-send-email-sebastian.hesselbarth@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1413883364-681-1-git-send-email-sebastian.hesselbarth@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Sebastian Hesselbarth Cc: devicetree@vger.kernel.org, Ulf Hansson , =?UTF-8?q?Antoine=20T=C3=A9nart?= , linux-mmc@vger.kernel.org, Chris Ball , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org Y29tbWl0IGJiODE3NWE4YWE0MmQ3MzFhODQwY2Q0NzRlMzQ4YWMzMzY3ZWI1YTAKICAoIm1tYzog c2RoY2k6IGNsYXJpZnkgRERSIHRpbWluZyBtb2RlIGJldHdlZW4gU0QtVUhTIGFuZCBlTU1DIikK YWRkZWQgTU1DX0REUjUyIGFzIGVNTUMncyBERFIgbW9kZSB0byBiZSBkaXN0aW5ndWlzaGVkIGZy b20gU0QtVUhTLgoKV2hpbGUgdGhlIGRpZmZlcmVudGF0aW9uIG1heSBiZSB1c2VmdWwsIHB4YXYz IFNESENJIGNvbnRyb2xsZXIgbGFja3MKYSBjb3JyZXNwb25kaW5nIGNoZWNrIGluIGl0cyBjdXN0 b20gLnNldF91aHNfc2lnbmFsaW5nIGNhbGxiYWNrIGZvcgpNTUNfRERSNTIuIFRoaXMgcGF0Y2gg YWRkcyBhIG5ldyBzd2l0Y2ggY2FzZSBmb3IgTU1DX1RJTUlOR19NTUNfRERSNTIKdG8gTU1DX1RJ TUlOR19VSFNfRERSNTAgY2FzZS4KClNpZ25lZC1vZmYtYnk6IFNlYmFzdGlhbiBIZXNzZWxiYXJ0 aCA8c2ViYXN0aWFuLmhlc3NlbGJhcnRoQGdtYWlsLmNvbT4KLS0tCkNjOiBDaHJpcyBCYWxsIDxj aHJpc0BwcmludGYubmV0PgpDYzogVWxmIEhhbnNzb24gPHVsZi5oYW5zc29uQGxpbmFyby5vcmc+ CkNjOiAiQW50b2luZSBUw6luYXJ0IiA8YW50b2luZS50ZW5hcnRAZnJlZS1lbGVjdHJvbnMuY29t PgpDYzogbGludXgtbW1jQHZnZXIua2VybmVsLm9yZwpDYzogZGV2aWNldHJlZUB2Z2VyLmtlcm5l bC5vcmcKQ2M6IGxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZwpDYzogbGludXgt a2VybmVsQHZnZXIua2VybmVsLm9yZwotLS0KIGRyaXZlcnMvbW1jL2hvc3Qvc2RoY2ktcHhhdjMu YyB8IDEgKwogMSBmaWxlIGNoYW5nZWQsIDEgaW5zZXJ0aW9uKCspCgpkaWZmIC0tZ2l0IGEvZHJp dmVycy9tbWMvaG9zdC9zZGhjaS1weGF2My5jIGIvZHJpdmVycy9tbWMvaG9zdC9zZGhjaS1weGF2 My5jCmluZGV4IDUwMzZkN2QzOTUyOS4uYjU1YzgwNzk4MmZlIDEwMDY0NAotLS0gYS9kcml2ZXJz L21tYy9ob3N0L3NkaGNpLXB4YXYzLmMKKysrIGIvZHJpdmVycy9tbWMvaG9zdC9zZGhjaS1weGF2 My5jCkBAIC0yMTEsNiArMjExLDcgQEAgc3RhdGljIHZvaWQgcHhhdjNfc2V0X3Voc19zaWduYWxp bmcoc3RydWN0IHNkaGNpX2hvc3QgKmhvc3QsIHVuc2lnbmVkIGludCB1aHMpCiAJY2FzZSBNTUNf VElNSU5HX1VIU19TRFIxMDQ6CiAJCWN0cmxfMiB8PSBTREhDSV9DVFJMX1VIU19TRFIxMDQgfCBT REhDSV9DVFJMX1ZERF8xODA7CiAJCWJyZWFrOworCWNhc2UgTU1DX1RJTUlOR19NTUNfRERSNTI6 CiAJY2FzZSBNTUNfVElNSU5HX1VIU19ERFI1MDoKIAkJY3RybF8yIHw9IFNESENJX0NUUkxfVUhT X0REUjUwIHwgU0RIQ0lfQ1RSTF9WRERfMTgwOwogCQlicmVhazsKLS0gCjIuMS4xCgoKX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtlcm5l bCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6 Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo=