From: Yingjoe Chen <yingjoe.chen@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
Jiang Liu <jiang.liu@linux.intel.com>,
Marc Zyngier <marc.zyngier@arm.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
arm@kernel.org
Cc: Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Russell King <linux@arm.linux.org.uk>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Yingjoe Chen <yingjoe.chen@mediatek.com>,
Grant Likely <grant.likely@linaro.org>,
Hans de Goede <hdegoede@redhat.com>,
Boris BREZILLON <boris.brezillon@free-electrons.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Olof Johansson <olof@lixom.net>, Arnd Bergmann <arnd@arndb.de>,
srv_heupstream@mediatek.com, yingjoe.chen@gmail.com,
hc.yen@mediatek.com, eddie.huang@mediatek.com,
nathan.chung@mediatek.com, yh.chen@mediatek.com
Subject: [PATCH v4 6/7] ARM: mediatek: Add sysirq in mt6589/mt8135/mt8127 dtsi
Date: Thu, 23 Oct 2014 23:53:14 +0800 [thread overview]
Message-ID: <1414079595-26129-7-git-send-email-yingjoe.chen@mediatek.com> (raw)
In-Reply-To: <1414079595-26129-1-git-send-email-yingjoe.chen@mediatek.com>
Add sysirq settings for mt6589/mt8135/mt8127
This also correct timer interrupt flag. The old flag setting
works because boot loader already set polarity for timer
interrupt. Without intpol support, the setting was not changed
so gic can get the irq correctly.
Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
---
arch/arm/boot/dts/mt6589.dtsi | 13 +++++++++++--
arch/arm/boot/dts/mt8127.dtsi | 13 +++++++++++--
arch/arm/boot/dts/mt8135.dtsi | 13 +++++++++++--
3 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi
index e3c7600..e7e7ddf 100644
--- a/arch/arm/boot/dts/mt6589.dtsi
+++ b/arch/arm/boot/dts/mt6589.dtsi
@@ -19,7 +19,7 @@
/ {
compatible = "mediatek,mt6589";
- interrupt-parent = <&gic>;
+ interrupt-parent = <&sysirq>;
cpus {
#address-cells = <1>;
@@ -76,15 +76,24 @@
timer: timer@10008000 {
compatible = "mediatek,mt6577-timer";
reg = <0x10008000 0x80>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
clocks = <&system_clk>, <&rtc_clk>;
clock-names = "system-clk", "rtc-clk";
};
+ sysirq: interrupt-controller@10200100 {
+ compatible = "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200100 0 0x1c>;
+ };
+
gic: interrupt-controller@10211000 {
compatible = "arm,cortex-a7-gic";
interrupt-controller;
#interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
reg = <0x10211000 0x1000>,
<0x10212000 0x1000>,
<0x10214000 0x2000>,
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
index 65d279d..adc6f2d 100644
--- a/arch/arm/boot/dts/mt8127.dtsi
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -18,7 +18,7 @@
/ {
compatible = "mediatek,mt8127";
- interrupt-parent = <&gic>;
+ interrupt-parent = <&sysirq>;
cpus {
#address-cells = <1>;
@@ -81,15 +81,24 @@
timer: timer@10008000 {
compatible = "mediatek,mt8127-timer", "mediatek,mt6577-timer";
reg = <0 0x10008000 0 0x80>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
clocks = <&system_clk>, <&rtc_clk>;
clock-names = "system-clk", "rtc-clk";
};
+ sysirq: interrupt-controller@10200100 {
+ compatible = "mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200100 0 0x1c>;
+ };
+
gic: interrupt-controller@10211000 {
compatible = "arm,cortex-a7-gic";
interrupt-controller;
#interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
reg = <0 0x10211000 0 0x1000>,
<0 0x10212000 0 0x1000>,
<0 0x10214000 0 0x2000>,
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index f89a4f5..9627320 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -18,7 +18,7 @@
/ {
compatible = "mediatek,mt8135";
- interrupt-parent = <&gic>;
+ interrupt-parent = <&sysirq>;
cpu-map {
cluster0 {
@@ -103,15 +103,24 @@
timer: timer@10008000 {
compatible = "mediatek,mt8135-timer", "mediatek,mt6577-timer";
reg = <0 0x10008000 0 0x80>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
clocks = <&system_clk>, <&rtc_clk>;
clock-names = "system-clk", "rtc-clk";
};
+ sysirq: interrupt-controller@10200030 {
+ compatible = "mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200030 0 0x1c>;
+ };
+
gic: interrupt-controller@10211000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
reg = <0 0x10211000 0 0x1000>,
<0 0x10212000 0 0x1000>,
<0 0x10214000 0 0x2000>,
--
1.8.1.1.dirty
next prev parent reply other threads:[~2014-10-23 15:53 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-23 15:53 [PATCH v4 0/7] ARM: mediatek: Add support for interrupt polarity Yingjoe Chen
2014-10-23 15:53 ` [PATCH v4 1/7] irqdomain: Fix irq_domain_alloc_irqs return check Yingjoe Chen
2014-10-23 15:53 ` [PATCH v4 2/7] irqdomain: Add back xlate and set_type for hierarchy irq domain Yingjoe Chen
2014-10-23 15:53 ` [PATCH v4 3/7] genirq: Add more helper functions to support stacked irq_chip Yingjoe Chen
2014-10-23 15:53 ` [PATCH v4 4/7] irqchip: gic: Support hierarchy irq domain Yingjoe Chen
[not found] ` <1414079595-26129-5-git-send-email-yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2014-10-24 6:50 ` Yingjoe Chen
2014-10-23 15:53 ` [PATCH v4 5/7] ARM: mediatek: Add sysirq interrupt polarity support Yingjoe Chen
2014-10-23 15:53 ` Yingjoe Chen [this message]
2014-10-23 15:53 ` [PATCH v4 7/7] dt-bindings: add bindings for mediatek sysirq Yingjoe Chen
[not found] ` <1414079595-26129-1-git-send-email-yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2014-10-24 14:59 ` [PATCH v4 0/7] ARM: mediatek: Add support for interrupt polarity Matthias Brugger
[not found] ` <CABuKBeLjFDm2TSqxc=K3rDnYTKRok3sCvEuL+chxxo7p1UbhLQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-10-24 15:06 ` Yingjoe Chen
2014-10-27 7:44 ` Yingjoe Chen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1414079595-26129-7-git-send-email-yingjoe.chen@mediatek.com \
--to=yingjoe.chen@mediatek.com \
--cc=arm@kernel.org \
--cc=arnd@arndb.de \
--cc=benh@kernel.crashing.org \
--cc=boris.brezillon@free-electrons.com \
--cc=devicetree@vger.kernel.org \
--cc=eddie.huang@mediatek.com \
--cc=galak@codeaurora.org \
--cc=grant.likely@linaro.org \
--cc=hc.yen@mediatek.com \
--cc=hdegoede@redhat.com \
--cc=ijc+devicetree@hellion.org.uk \
--cc=jason@lakedaemon.net \
--cc=jiang.liu@linux.intel.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux@arm.linux.org.uk \
--cc=marc.zyngier@arm.com \
--cc=mark.rutland@arm.com \
--cc=matthias.bgg@gmail.com \
--cc=nathan.chung@mediatek.com \
--cc=olof@lixom.net \
--cc=pawel.moll@arm.com \
--cc=robh+dt@kernel.org \
--cc=srv_heupstream@mediatek.com \
--cc=tglx@linutronix.de \
--cc=yh.chen@mediatek.com \
--cc=yingjoe.chen@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).