[PATCH 1/3] powerpc/dts: Factorize the clock control node

[PATCH 1/3] powerpc/dts: Factorize the clock control node

[Emil Medve]

Signed-off-by: Emil Medve <Emilian.Medve-eDlz3WWmN0ll57MIdRCFDg@public.gmane.org>
Change-Id: I25ce24a25862b4ca460164159867abefe00ccdd1
---
 arch/powerpc/boot/dts/b4860emu.dts             |  4 +-
 arch/powerpc/boot/dts/fsl/b4420si-post.dtsi    | 28 +--------
 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi    | 28 +--------
 arch/powerpc/boot/dts/fsl/p2041si-post.dtsi    | 49 +---------------
 arch/powerpc/boot/dts/fsl/p3041si-post.dtsi    | 49 +---------------
 arch/powerpc/boot/dts/fsl/p4080si-post.dtsi    | 55 +-----------------
 arch/powerpc/boot/dts/fsl/p5020si-post.dtsi    | 48 +---------------
 arch/powerpc/boot/dts/fsl/p5040si-post.dtsi    | 49 +---------------
 arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi | 78 ++++++++++++++++++++++++++
 arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi | 61 ++++++++++++++++++++
 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi    | 33 +----------
 arch/powerpc/boot/dts/fsl/t2081si-post.dtsi    | 30 +---------
 arch/powerpc/boot/dts/fsl/t4240si-post.dtsi    | 34 +----------
 arch/powerpc/boot/dts/t4240emu.dts             |  4 +-
 14 files changed, 163 insertions(+), 387 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi

diff --git a/arch/powerpc/boot/dts/b4860emu.dts b/arch/powerpc/boot/dts/b4860emu.dts
index 85646b4..2aa5cd3 100644
--- a/arch/powerpc/boot/dts/b4860emu.dts
+++ b/arch/powerpc/boot/dts/b4860emu.dts
@@ -193,9 +193,9 @@
 		fsl,liodn-bits = <12>;
 	};
 
-	clockgen: global-utilities@e1000 {
+/include/ "fsl/qoriq-clockgen2.dtsi"
+	global-utilities@e1000 {
 		compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
-		reg = <0xe1000 0x1000>;
 	};
 
 /include/ "fsl/qoriq-dma-0.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index b34c62e..aced374 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -80,33 +80,9 @@
 		compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
 	};
 
-	clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen2.dtsi"
+	global-utilities@e1000 {
 		compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
-		ranges = <0x0 0xe1000 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		sysclk: sysclk {
-			#clock-cells = <0>;
-			compatible = "fsl,qoriq-sysclk-2.0";
-			clock-output-names = "sysclk";
-		};
-
-		pll0: pll0@800 {
-			#clock-cells = <1>;
-			reg = <0x800 0x4>;
-			compatible = "fsl,qoriq-core-pll-2.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll0", "pll0-div2", "pll0-div4";
-		};
-
-		pll1: pll1@820 {
-			#clock-cells = <1>;
-			reg = <0x820 0x4>;
-			compatible = "fsl,qoriq-core-pll-2.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll1", "pll1-div2", "pll1-div4";
-		};
 
 		mux0: mux0@0 {
 			#clock-cells = <0>;
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index 256fac8..3b9bb37 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -273,33 +273,9 @@
 		compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";
 	};
 
-	clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen2.dtsi"
+	global-utilities@e1000 {
 		compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";
-		ranges = <0x0 0xe1000 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		sysclk: sysclk {
-			#clock-cells = <0>;
-			compatible = "fsl,qoriq-sysclk-2.0";
-			clock-output-names = "sysclk";
-		};
-
-		pll0: pll0@800 {
-			#clock-cells = <1>;
-			reg = <0x800 0x4>;
-			compatible = "fsl,qoriq-core-pll-2.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll0", "pll0-div2", "pll0-div4";
-		};
-
-		pll1: pll1@820 {
-			#clock-cells = <1>;
-			reg = <0x820 0x4>;
-			compatible = "fsl,qoriq-core-pll-2.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll1", "pll1-div2", "pll1-div4";
-		};
 
 		mux0: mux0@0 {
 			#clock-cells = <0>;
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index f297514..6edacf3 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -313,53 +313,9 @@
 		#sleep-cells = <2>;
 	};
 
-	clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen1.dtsi"
+	global-utilities@e1000 {
 		compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
-		ranges = <0x0 0xe1000 0x1000>;
-		reg = <0xe1000 0x1000>;
-		clock-frequency = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		sysclk: sysclk {
-			#clock-cells = <0>;
-			compatible = "fsl,qoriq-sysclk-1.0";
-			clock-output-names = "sysclk";
-		};
-
-		pll0: pll0@800 {
-			#clock-cells = <1>;
-			reg = <0x800 0x4>;
-			compatible = "fsl,qoriq-core-pll-1.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll0", "pll0-div2";
-		};
-
-		pll1: pll1@820 {
-			#clock-cells = <1>;
-			reg = <0x820 0x4>;
-			compatible = "fsl,qoriq-core-pll-1.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll1", "pll1-div2";
-		};
-
-		mux0: mux0@0 {
-			#clock-cells = <0>;
-			reg = <0x0 0x4>;
-			compatible = "fsl,qoriq-core-mux-1.0";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
-			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
-			clock-output-names = "cmux0";
-		};
-
-		mux1: mux1@20 {
-			#clock-cells = <0>;
-			reg = <0x20 0x4>;
-			compatible = "fsl,qoriq-core-mux-1.0";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
-			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
-			clock-output-names = "cmux1";
-		};
 
 		mux2: mux2@40 {
 			#clock-cells = <0>;
@@ -369,7 +325,6 @@
 			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
 			clock-output-names = "cmux2";
 		};
-
 		mux3: mux3@60 {
 			#clock-cells = <0>;
 			reg = <0x60 0x4>;
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index b3f89ce..cce28f9 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -340,53 +340,9 @@
 		#sleep-cells = <2>;
 	};
 
-	clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen1.dtsi"
+	global-utilities@e1000 {
 		compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
-		ranges = <0x0 0xe1000 0x1000>;
-		reg = <0xe1000 0x1000>;
-		clock-frequency = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		sysclk: sysclk {
-			#clock-cells = <0>;
-			compatible = "fsl,qoriq-sysclk-1.0";
-			clock-output-names = "sysclk";
-		};
-
-		pll0: pll0@800 {
-			#clock-cells = <1>;
-			reg = <0x800 0x4>;
-			compatible = "fsl,qoriq-core-pll-1.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll0", "pll0-div2";
-		};
-
-		pll1: pll1@820 {
-			#clock-cells = <1>;
-			reg = <0x820 0x4>;
-			compatible = "fsl,qoriq-core-pll-1.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll1", "pll1-div2";
-		};
-
-		mux0: mux0@0 {
-			#clock-cells = <0>;
-			reg = <0x0 0x4>;
-			compatible = "fsl,qoriq-core-mux-1.0";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
-			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
-			clock-output-names = "cmux0";
-		};
-
-		mux1: mux1@20 {
-			#clock-cells = <0>;
-			reg = <0x20 0x4>;
-			compatible = "fsl,qoriq-core-mux-1.0";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
-			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
-			clock-output-names = "cmux1";
-		};
 
 		mux2: mux2@40 {
 			#clock-cells = <0>;
@@ -396,7 +352,6 @@
 			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
 			clock-output-names = "cmux2";
 		};
-
 		mux3: mux3@60 {
 			#clock-cells = <0>;
 			reg = <0x60 0x4>;
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index e410b15..9998b99 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -360,35 +360,9 @@
 		#sleep-cells = <2>;
 	};
 
-	clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen1.dtsi"
+	global-utilities@e1000 {
 		compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
-		ranges = <0x0 0xe1000 0x1000>;
-		reg = <0xe1000 0x1000>;
-		clock-frequency = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		sysclk: sysclk {
-			#clock-cells = <0>;
-			compatible = "fsl,qoriq-sysclk-1.0";
-			clock-output-names = "sysclk";
-		};
-
-		pll0: pll0@800 {
-			#clock-cells = <1>;
-			reg = <0x800 0x4>;
-			compatible = "fsl,qoriq-core-pll-1.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll0", "pll0-div2";
-		};
-
-		pll1: pll1@820 {
-			#clock-cells = <1>;
-			reg = <0x820 0x4>;
-			compatible = "fsl,qoriq-core-pll-1.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll1", "pll1-div2";
-		};
 
 		pll2: pll2@840 {
 			#clock-cells = <1>;
@@ -397,7 +371,6 @@
 			clocks = <&sysclk>;
 			clock-output-names = "pll2", "pll2-div2";
 		};
-
 		pll3: pll3@860 {
 			#clock-cells = <1>;
 			reg = <0x860 0x4>;
@@ -405,25 +378,6 @@
 			clocks = <&sysclk>;
 			clock-output-names = "pll3", "pll3-div2";
 		};
-
-		mux0: mux0@0 {
-			#clock-cells = <0>;
-			reg = <0x0 0x4>;
-			compatible = "fsl,qoriq-core-mux-1.0";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
-			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
-			clock-output-names = "cmux0";
-		};
-
-		mux1: mux1@20 {
-			#clock-cells = <0>;
-			reg = <0x20 0x4>;
-			compatible = "fsl,qoriq-core-mux-1.0";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
-			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
-			clock-output-names = "cmux1";
-		};
-
 		mux2: mux2@40 {
 			#clock-cells = <0>;
 			reg = <0x40 0x4>;
@@ -432,7 +386,6 @@
 			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
 			clock-output-names = "cmux2";
 		};
-
 		mux3: mux3@60 {
 			#clock-cells = <0>;
 			reg = <0x60 0x4>;
@@ -441,7 +394,6 @@
 			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
 			clock-output-names = "cmux3";
 		};
-
 		mux4: mux4@80 {
 			#clock-cells = <0>;
 			reg = <0x80 0x4>;
@@ -450,7 +402,6 @@
 			clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
 			clock-output-names = "cmux4";
 		};
-
 		mux5: mux5@a0 {
 			#clock-cells = <0>;
 			reg = <0xa0 0x4>;
@@ -459,7 +410,6 @@
 			clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
 			clock-output-names = "cmux5";
 		};
-
 		mux6: mux6@c0 {
 			#clock-cells = <0>;
 			reg = <0xc0 0x4>;
@@ -468,7 +418,6 @@
 			clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
 			clock-output-names = "cmux6";
 		};
-
 		mux7: mux7@e0 {
 			#clock-cells = <0>;
 			reg = <0xe0 0x4>;
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index d07c771..b70c8c3 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -345,53 +345,9 @@
 		#sleep-cells = <2>;
 	};
 
-	clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen1.dtsi"
+	global-utilities@e1000 {
 		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
-		ranges = <0x0 0xe1000 0x1000>;
-		reg = <0xe1000 0x1000>;
-		clock-frequency = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		sysclk: sysclk {
-			#clock-cells = <0>;
-			compatible = "fsl,qoriq-sysclk-1.0";
-			clock-output-names = "sysclk";
-		};
-
-		pll0: pll0@800 {
-			#clock-cells = <1>;
-			reg = <0x800 0x4>;
-			compatible = "fsl,qoriq-core-pll-1.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll0", "pll0-div2";
-		};
-
-		pll1: pll1@820 {
-			#clock-cells = <1>;
-			reg = <0x820 0x4>;
-			compatible = "fsl,qoriq-core-pll-1.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll1", "pll1-div2";
-		};
-
-		mux0: mux0@0 {
-			#clock-cells = <0>;
-			reg = <0x0 0x4>;
-			compatible = "fsl,qoriq-core-mux-1.0";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
-			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
-			clock-output-names = "cmux0";
-		};
-
-		mux1: mux1@20 {
-			#clock-cells = <0>;
-			reg = <0x20 0x4>;
-			compatible = "fsl,qoriq-core-mux-1.0";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
-			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
-			clock-output-names = "cmux1";
-		};
 	};
 
 	rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index 243574b..663c48b 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -305,53 +305,9 @@
 		#sleep-cells = <2>;
 	};
 
-	clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen1.dtsi"
+	global-utilities@e1000 {
 		compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
-		ranges = <0x0 0xe1000 0x1000>;
-		reg = <0xe1000 0x1000>;
-		clock-frequency = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		sysclk: sysclk {
-			#clock-cells = <0>;
-			compatible = "fsl,qoriq-sysclk-1.0";
-			clock-output-names = "sysclk";
-		};
-
-		pll0: pll0@800 {
-			#clock-cells = <1>;
-			reg = <0x800 0x4>;
-			compatible = "fsl,qoriq-core-pll-1.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll0", "pll0-div2";
-		};
-
-		pll1: pll1@820 {
-			#clock-cells = <1>;
-			reg = <0x820 0x4>;
-			compatible = "fsl,qoriq-core-pll-1.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll1", "pll1-div2";
-		};
-
-		mux0: mux0@0 {
-			#clock-cells = <0>;
-			reg = <0x0 0x4>;
-			compatible = "fsl,qoriq-core-mux-1.0";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
-			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
-			clock-output-names = "cmux0";
-		};
-
-		mux1: mux1@20 {
-			#clock-cells = <0>;
-			reg = <0x20 0x4>;
-			compatible = "fsl,qoriq-core-mux-1.0";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
-			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
-			clock-output-names = "cmux1";
-		};
 
 		mux2: mux2@40 {
 			#clock-cells = <0>;
@@ -361,7 +317,6 @@
 			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
 			clock-output-names = "cmux2";
 		};
-
 		mux3: mux3@60 {
 			#clock-cells = <0>;
 			reg = <0x60 0x4>;
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
new file mode 100644
index 0000000..4871048
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
@@ -0,0 +1,78 @@
+/*
+ * QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *	 notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *	 notice, this list of conditions and the following disclaimer in the
+ *	 documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *	 names of its contributors may be used to endorse or promote products
+ *	 derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+global-utilities@e1000 {
+	compatible = "fsl,qoriq-clockgen-1.0";
+	ranges = <0x0 0xe1000 0x1000>;
+	reg = <0xe1000 0x1000>;
+	clock-frequency = <0>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	sysclk: sysclk {
+		#clock-cells = <0>;
+		compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
+		clock-output-names = "sysclk";
+	};
+	pll0: pll0@800 {
+		#clock-cells = <1>;
+		reg = <0x800 0x4>;
+		compatible = "fsl,qoriq-core-pll-1.0";
+		clocks = <&sysclk>;
+		clock-output-names = "pll0", "pll0-div2";
+	};
+	pll1: pll1@820 {
+		#clock-cells = <1>;
+		reg = <0x820 0x4>;
+		compatible = "fsl,qoriq-core-pll-1.0";
+		clocks = <&sysclk>;
+		clock-output-names = "pll1", "pll1-div2";
+	};
+	mux0: mux0@0 {
+		#clock-cells = <0>;
+		reg = <0x0 0x4>;
+		compatible = "fsl,qoriq-core-mux-1.0";
+		clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+		clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+		clock-output-names = "cmux0";
+	};
+	mux1: mux1@20 {
+		#clock-cells = <0>;
+		reg = <0x20 0x4>;
+		compatible = "fsl,qoriq-core-mux-1.0";
+		clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+		clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+		clock-output-names = "cmux1";
+	};
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
new file mode 100644
index 0000000..5d18d2a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
@@ -0,0 +1,61 @@
+/*
+ * QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *	 notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *	 notice, this list of conditions and the following disclaimer in the
+ *	 documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *	 names of its contributors may be used to endorse or promote products
+ *	 derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+global-utilities@e1000 {
+	compatible = "fsl,qoriq-clockgen-2.0";
+	ranges = <0x0 0xe1000 0x1000>;
+	reg = <0xe1000 0x1000>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	sysclk: sysclk {
+		#clock-cells = <0>;
+		compatible = "fsl,qoriq-sysclk-2.0", "fixed-clock";
+		clock-output-names = "sysclk";
+	};
+	pll0: pll0@800 {
+		#clock-cells = <1>;
+		reg = <0x800 0x4>;
+		compatible = "fsl,qoriq-core-pll-2.0";
+		clocks = <&sysclk>;
+		clock-output-names = "pll0", "pll0-div2", "pll0-div4";
+	};
+	pll1: pll1@820 {
+		#clock-cells = <1>;
+		reg = <0x820 0x4>;
+		compatible = "fsl,qoriq-core-pll-2.0";
+		clocks = <&sysclk>;
+		clock-output-names = "pll1", "pll1-div2", "pll1-div4";
+	};
+};
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index e989b6a..e9a81ac 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -432,35 +432,9 @@
 		fsl,liodn-bits = <12>;
 	};
 
-	clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen2.dtsi"
+	global-utilities@e1000 {
 		compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0";
-		ranges = <0x0 0xe1000 0x1000>;
-		reg = <0xe1000 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		sysclk: sysclk {
-			#clock-cells = <0>;
-			compatible = "fsl,qoriq-sysclk-2.0";
-			clock-output-names = "sysclk", "fixed-clock";
-		};
-
-
-		pll0: pll0@800 {
-			#clock-cells = <1>;
-			reg = <0x800 4>;
-			compatible = "fsl,qoriq-core-pll-2.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll0", "pll0-div2", "pll0-div4";
-		};
-
-		pll1: pll1@820 {
-			#clock-cells = <1>;
-			reg = <0x820 4>;
-			compatible = "fsl,qoriq-core-pll-2.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll1", "pll1-div2", "pll1-div4";
-		};
 
 		mux0: mux0@0 {
 			#clock-cells = <0>;
@@ -472,7 +446,6 @@
 				"pll1", "pll1-div2", "pll1-div4";
 			clock-output-names = "cmux0";
 		};
-
 		mux1: mux1@20 {
 			#clock-cells = <0>;
 			reg = <0x20 4>;
@@ -483,7 +456,6 @@
 				"pll1", "pll1-div2", "pll1-div4";
 			clock-output-names = "cmux1";
 		};
-
 		mux2: mux2@40 {
 			#clock-cells = <0>;
 			reg = <0x40 4>;
@@ -494,7 +466,6 @@
 				"pll1", "pll1-div2", "pll1-div4";
 			clock-output-names = "cmux2";
 		};
-
 		mux3: mux3@60 {
 			#clock-cells = <0>;
 			reg = <0x60 4>;
diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
index dfbe499..72377c5 100644
--- a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
@@ -553,34 +553,9 @@
 		fsl,liodn-bits = <12>;
 	};
 
-	clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen2.dtsi"
+	global-utilities@e1000 {
 		compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0";
-		ranges = <0x0 0xe1000 0x1000>;
-		reg = <0xe1000 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		sysclk: sysclk {
-			#clock-cells = <0>;
-			compatible = "fsl,qoriq-sysclk-2.0";
-			clock-output-names = "sysclk", "fixed-clock";
-		};
-
-		pll0: pll0@800 {
-			#clock-cells = <1>;
-			reg = <0x800 4>;
-			compatible = "fsl,qoriq-core-pll-2.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll0", "pll0-div2", "pll0-div4";
-		};
-
-		pll1: pll1@820 {
-			#clock-cells = <1>;
-			reg = <0x820 4>;
-			compatible = "fsl,qoriq-core-pll-2.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll1", "pll1-div2", "pll1-div4";
-		};
 
 		mux0: mux0@0 {
 			#clock-cells = <0>;
@@ -592,7 +567,6 @@
 				"pll1", "pll1-div2", "pll1-div4";
 			clock-output-names = "cmux0";
 		};
-
 		mux1: mux1@20 {
 			#clock-cells = <0>;
 			reg = <0x20 4>;
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index d2ecd86..ec373b3 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -1032,34 +1032,9 @@
 		fsl,liodn-bits = <12>;
 	};
 
-	clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen2.dtsi"
+	global-utilities@e1000 {
 		compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
-		ranges = <0x0 0xe1000 0x1000>;
-		reg = <0xe1000 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		sysclk: sysclk {
-			#clock-cells = <0>;
-			compatible = "fsl,qoriq-sysclk-2.0";
-			clock-output-names = "sysclk";
-		};
-
-		pll0: pll0@800 {
-			#clock-cells = <1>;
-			reg = <0x800 0x4>;
-			compatible = "fsl,qoriq-core-pll-2.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll0", "pll0-div2", "pll0-div4";
-		};
-
-		pll1: pll1@820 {
-			#clock-cells = <1>;
-			reg = <0x820 0x4>;
-			compatible = "fsl,qoriq-core-pll-2.0";
-			clocks = <&sysclk>;
-			clock-output-names = "pll1", "pll1-div2", "pll1-div4";
-		};
 
 		pll2: pll2@840 {
 			#clock-cells = <1>;
@@ -1068,7 +1043,6 @@
 			clocks = <&sysclk>;
 			clock-output-names = "pll2", "pll2-div2", "pll2-div4";
 		};
-
 		pll3: pll3@860 {
 			#clock-cells = <1>;
 			reg = <0x860 0x4>;
@@ -1076,7 +1050,6 @@
 			clocks = <&sysclk>;
 			clock-output-names = "pll3", "pll3-div2", "pll3-div4";
 		};
-
 		pll4: pll4@880 {
 			#clock-cells = <1>;
 			reg = <0x880 0x4>;
@@ -1084,7 +1057,6 @@
 			clocks = <&sysclk>;
 			clock-output-names = "pll4", "pll4-div2", "pll4-div4";
 		};
-
 		mux0: mux0@0 {
 			#clock-cells = <0>;
 			reg = <0x0 0x4>;
@@ -1097,7 +1069,6 @@
 				"pll2", "pll2-div2", "pll2-div4";
 			clock-output-names = "cmux0";
 		};
-
 		mux1: mux1@20 {
 			#clock-cells = <0>;
 			reg = <0x20 0x4>;
@@ -1110,7 +1081,6 @@
 				"pll2", "pll2-div2", "pll2-div4";
 			clock-output-names = "cmux1";
 		};
-
 		mux2: mux2@40 {
 			#clock-cells = <0>;
 			reg = <0x40 0x4>;
diff --git a/arch/powerpc/boot/dts/t4240emu.dts b/arch/powerpc/boot/dts/t4240emu.dts
index bc12127a..decaf35 100644
--- a/arch/powerpc/boot/dts/t4240emu.dts
+++ b/arch/powerpc/boot/dts/t4240emu.dts
@@ -250,9 +250,9 @@
 		fsl,liodn-bits = <12>;
 	};
 
-	clockgen: global-utilities@e1000 {
+/include/ "fsl/qoriq-clockgen2.dtsi"
+	global-utilities@e1000 {
 		compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
-		reg = <0xe1000 0x1000>;
 	};
 
 /include/ "fsl/qoriq-dma-0.dtsi"
-- 
2.1.2

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[PATCH 2/3] dt/bindings: qoriq-clock: Add binding for the platform PLL

[Emil Medve]

Signed-off-by: Emil Medve <Emilian.Medve-eDlz3WWmN0ll57MIdRCFDg@public.gmane.org>
Change-Id: I7950afa9650d15ec7ce2cca89bb2a1e38586d4a5
---
 Documentation/devicetree/bindings/clock/qoriq-clock.txt | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 5666812..407fb01 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -62,6 +62,8 @@ Required properties:
 		It takes parent's clock-frequency as its clock.
 	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
 		It takes parent's clock-frequency as its clock.
+	* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
+	* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
 - #clock-cells: From common clock binding. The number of cells in a
 	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
 	clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
@@ -94,7 +96,6 @@ Example for clock block and clock provider:
 			compatible = "fsl,qoriq-sysclk-1.0";
 			clock-output-names = "sysclk";
 		};
-
 		pll0: pll0@800 {
 			#clock-cells = <1>;
 			reg = <0x800 0x4>;
@@ -102,7 +103,6 @@ Example for clock block and clock provider:
 			clocks = <&sysclk>;
 			clock-output-names = "pll0", "pll0-div2";
 		};
-
 		pll1: pll1@820 {
 			#clock-cells = <1>;
 			reg = <0x820 0x4>;
@@ -110,7 +110,6 @@ Example for clock block and clock provider:
 			clocks = <&sysclk>;
 			clock-output-names = "pll1", "pll1-div2";
 		};
-
 		mux0: mux0@0 {
 			#clock-cells = <0>;
 			reg = <0x0 0x4>;
@@ -119,7 +118,6 @@ Example for clock block and clock provider:
 			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
 			clock-output-names = "cmux0";
 		};
-
 		mux1: mux1@20 {
 			#clock-cells = <0>;
 			reg = <0x20 0x4>;
@@ -128,8 +126,15 @@ Example for clock block and clock provider:
 			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
 			clock-output-names = "cmux1";
 		};
+		platform-pll: platform-pll@c00 {
+			#clock-cells = <1>;
+			reg = <0xc00 0x4>;
+			compatible = "fsl,qoriq-platform-pll-1.0";
+			clocks = <&sysclk>;
+			clock-output-names = "platform-pll", "platform-pll-div2";
+		};
 	};
-  }
+};
 
 Example for clock consumer:
 
@@ -139,4 +144,4 @@ Example for clock consumer:
 		clocks = <&mux0>;
 		...
 	};
-  }
+};
-- 
2.1.2

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Re: [PATCH 2/3] dt/bindings: qoriq-clock: Add binding for the platform PLL

[Scott Wood]

On Wed, 2014-10-22 at 09:42 -0500, Emil Medve wrote:
> Signed-off-by: Emil Medve <Emilian.Medve-eDlz3WWmN0ll57MIdRCFDg@public.gmane.org>
> Change-Id: I7950afa9650d15ec7ce2cca89bb2a1e38586d4a5
> ---
>  Documentation/devicetree/bindings/clock/qoriq-clock.txt | 17 +++++++++++------
>  1 file changed, 11 insertions(+), 6 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index 5666812..407fb01 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -62,6 +62,8 @@ Required properties:
>  		It takes parent's clock-frequency as its clock.
>  	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
>  		It takes parent's clock-frequency as its clock.
> +	* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
> +	* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
>  - #clock-cells: From common clock binding. The number of cells in a
>  	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
>  	clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
> @@ -94,7 +96,6 @@ Example for clock block and clock provider:
>  			compatible = "fsl,qoriq-sysclk-1.0";
>  			clock-output-names = "sysclk";
>  		};
> -
>  		pll0: pll0@800 {
>  			#clock-cells = <1>;
>  			reg = <0x800 0x4>;
> @@ -102,7 +103,6 @@ Example for clock block and clock provider:
>  			clocks = <&sysclk>;
>  			clock-output-names = "pll0", "pll0-div2";
>  		};
> -
>  		pll1: pll1@820 {
>  			#clock-cells = <1>;
>  			reg = <0x820 0x4>;
> @@ -110,7 +110,6 @@ Example for clock block and clock provider:
>  			clocks = <&sysclk>;
>  			clock-output-names = "pll1", "pll1-div2";
>  		};
> -
>  		mux0: mux0@0 {
>  			#clock-cells = <0>;
>  			reg = <0x0 0x4>;

Please don't make unrelated whitespace changes, especially when they're
changing something that's not obviously broken.

-Scott


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[PATCH 3/3] powerpc/dts: Add node(s) for the platform PLL

[Emil Medve]

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: If76cd705a01813abe53396c1486bc13c4289ee92
---
 arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi | 7 +++++++
 arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi | 7 +++++++
 2 files changed, 14 insertions(+)

diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
index 4871048..4ece1ed 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
@@ -75,4 +75,11 @@ global-utilities@e1000 {
 		clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
 		clock-output-names = "cmux1";
 	};
+	platform_pll: platform-pll@c00 {
+		#clock-cells = <1>;
+		reg = <0xc00 0x4>;
+		compatible = "fsl,qoriq-platform-pll-1.0";
+		clocks = <&sysclk>;
+		clock-output-names = "platform-pll", "platform-pll-div2";
+	};
 };
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
index 5d18d2a..48e0b6e 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
@@ -58,4 +58,11 @@ global-utilities@e1000 {
 		clocks = <&sysclk>;
 		clock-output-names = "pll1", "pll1-div2", "pll1-div4";
 	};
+	platform_pll: platform-pll@c00 {
+		#clock-cells = <1>;
+		reg = <0xc00 0x4>;
+		compatible = "fsl,qoriq-platform-pll-2.0";
+		clocks = <&sysclk>;
+		clock-output-names = "platform-pll", "platform-pll-div2";
+	};
 };
-- 
2.1.2

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Re: [PATCH 1/3] powerpc/dts: Factorize the clock control node

[Scott Wood]

On Wed, 2014-10-22 at 09:42 -0500, Emil Medve wrote:
> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
> Change-Id: I25ce24a25862b4ca460164159867abefe00ccdd1

Please remove gerrit stuff prior to submitting.

> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
> new file mode 100644
> index 0000000..4871048
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
> @@ -0,0 +1,78 @@
> +/*
> + * QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
> + *
> + * Copyright 2014 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions are met:
> + *     * Redistributions of source code must retain the above copyright
> + *	 notice, this list of conditions and the following disclaimer.
> + *     * Redistributions in binary form must reproduce the above copyright
> + *	 notice, this list of conditions and the following disclaimer in the
> + *	 documentation and/or other materials provided with the distribution.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *	 names of its contributors may be used to endorse or promote products
> + *	 derived from this software without specific prior written permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of the
> + * GNU General Public License ("GPL") as published by the Free Software
> + * Foundation, either version 2 of that License or (at your option) any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +global-utilities@e1000 {
> +	compatible = "fsl,qoriq-clockgen-1.0";
> +	ranges = <0x0 0xe1000 0x1000>;
> +	reg = <0xe1000 0x1000>;
> +	clock-frequency = <0>;
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	sysclk: sysclk {
> +		#clock-cells = <0>;
> +		compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
> +		clock-output-names = "sysclk";
> +	};
> +	pll0: pll0@800 {
> +		#clock-cells = <1>;
> +		reg = <0x800 0x4>;
> +		compatible = "fsl,qoriq-core-pll-1.0";
> +		clocks = <&sysclk>;
> +		clock-output-names = "pll0", "pll0-div2";
> +	};
> +	pll1: pll1@820 {
> +		#clock-cells = <1>;
> +		reg = <0x820 0x4>;
> +		compatible = "fsl,qoriq-core-pll-1.0";
> +		clocks = <&sysclk>;
> +		clock-output-names = "pll1", "pll1-div2";
> +	};
> +	mux0: mux0@0 {
> +		#clock-cells = <0>;
> +		reg = <0x0 0x4>;
> +		compatible = "fsl,qoriq-core-mux-1.0";
> +		clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> +		clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
> +		clock-output-names = "cmux0";
> +	};
> +	mux1: mux1@20 {
> +		#clock-cells = <0>;
> +		reg = <0x20 0x4>;
> +		compatible = "fsl,qoriq-core-mux-1.0";
> +		clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> +		clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
> +		clock-output-names = "cmux1";
> +	};
> +};

I don't think the mux stuff belongs here, given that clockgen2.dtsi
doesn't have it, and I saw at least one clockgen1 user needing to
supplement this with more muxes.

> @@ -1068,7 +1043,6 @@
>  			clocks = <&sysclk>;
>  			clock-output-names = "pll2", "pll2-div2", "pll2-div4";
>  		};
> -
>  		pll3: pll3@860 {
>  			#clock-cells = <1>;
>  			reg = <0x860 0x4>;
> @@ -1076,7 +1050,6 @@
>  			clocks = <&sysclk>;
>  			clock-output-names = "pll3", "pll3-div2", "pll3-div4";
>  		};
> -
>  		pll4: pll4@880 {
>  			#clock-cells = <1>;
>  			reg = <0x880 0x4>;

Why?

-Scott


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Re: [PATCH 1/3] powerpc/dts: Factorize the clock control node

[Emil Medve]

Hello Scott,


On 10/28/2014 06:21 PM, Scott Wood wrote:
> On Wed, 2014-10-22 at 09:42 -0500, Emil Medve wrote:
>> Signed-off-by: Emil Medve <Emilian.Medve-eDlz3WWmN0ll57MIdRCFDg@public.gmane.org>
>> Change-Id: I25ce24a25862b4ca460164159867abefe00ccdd1
> 
> Please remove gerrit stuff prior to submitting.

I did remove the bulk of it. I wanted to keep the Change-Id so I can
easily correlate the upstream patches with the sordid internal history.
Seems the upstream history has enough instances of 'Change-Id' for this
not to be an issue

>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
>> new file mode 100644
>> index 0000000..4871048
>> --- /dev/null
>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
>> @@ -0,0 +1,78 @@
>> +/*
>> + * QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
>> + *
>> + * Copyright 2014 Freescale Semiconductor Inc.
>> + *
>> + * Redistribution and use in source and binary forms, with or without
>> + * modification, are permitted provided that the following conditions are met:
>> + *     * Redistributions of source code must retain the above copyright
>> + *	 notice, this list of conditions and the following disclaimer.
>> + *     * Redistributions in binary form must reproduce the above copyright
>> + *	 notice, this list of conditions and the following disclaimer in the
>> + *	 documentation and/or other materials provided with the distribution.
>> + *     * Neither the name of Freescale Semiconductor nor the
>> + *	 names of its contributors may be used to endorse or promote products
>> + *	 derived from this software without specific prior written permission.
>> + *
>> + *
>> + * ALTERNATIVELY, this software may be distributed under the terms of the
>> + * GNU General Public License ("GPL") as published by the Free Software
>> + * Foundation, either version 2 of that License or (at your option) any
>> + * later version.
>> + *
>> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
>> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
>> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
>> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
>> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
>> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
>> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
>> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
>> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
>> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>> + */
>> +
>> +global-utilities@e1000 {
>> +	compatible = "fsl,qoriq-clockgen-1.0";
>> +	ranges = <0x0 0xe1000 0x1000>;
>> +	reg = <0xe1000 0x1000>;
>> +	clock-frequency = <0>;
>> +	#address-cells = <1>;
>> +	#size-cells = <1>;
>> +
>> +	sysclk: sysclk {
>> +		#clock-cells = <0>;
>> +		compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
>> +		clock-output-names = "sysclk";
>> +	};
>> +	pll0: pll0@800 {
>> +		#clock-cells = <1>;
>> +		reg = <0x800 0x4>;
>> +		compatible = "fsl,qoriq-core-pll-1.0";
>> +		clocks = <&sysclk>;
>> +		clock-output-names = "pll0", "pll0-div2";
>> +	};
>> +	pll1: pll1@820 {
>> +		#clock-cells = <1>;
>> +		reg = <0x820 0x4>;
>> +		compatible = "fsl,qoriq-core-pll-1.0";
>> +		clocks = <&sysclk>;
>> +		clock-output-names = "pll1", "pll1-div2";
>> +	};
>> +	mux0: mux0@0 {
>> +		#clock-cells = <0>;
>> +		reg = <0x0 0x4>;
>> +		compatible = "fsl,qoriq-core-mux-1.0";
>> +		clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
>> +		clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
>> +		clock-output-names = "cmux0";
>> +	};
>> +	mux1: mux1@20 {
>> +		#clock-cells = <0>;
>> +		reg = <0x20 0x4>;
>> +		compatible = "fsl,qoriq-core-mux-1.0";
>> +		clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
>> +		clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
>> +		clock-output-names = "cmux1";
>> +	};
>> +};
> 
> I don't think the mux stuff belongs here, given that clockgen2.dtsi
> doesn't have it, and I saw at least one clockgen1 user needing to
> supplement this with more muxes.

The intent was to put here devices/nodes that are common per chassis
from the low to high end. Specific SoC would change/augment this as
appropriate. I could have put each node in its own file as we've done
elsewhere, but I thought it would be too much

Yes, chassis v1 and v2 have differences, but that's not unexpected

>> @@ -1068,7 +1043,6 @@
>>  			clocks = <&sysclk>;
>>  			clock-output-names = "pll2", "pll2-div2", "pll2-div4";
>>  		};
>> -
>>  		pll3: pll3@860 {
>>  			#clock-cells = <1>;
>>  			reg = <0x860 0x4>;
>> @@ -1076,7 +1050,6 @@
>>  			clocks = <&sysclk>;
>>  			clock-output-names = "pll3", "pll3-div2", "pll3-div4";
>>  		};
>> -
>>  		pll4: pll4@880 {
>>  			#clock-cells = <1>;
>>  			reg = <0x880 0x4>;
> 
> Why?

Why what?


Cheers,
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Re: [PATCH 1/3] powerpc/dts: Factorize the clock control node

[Scott Wood]

On Thu, 2014-10-30 at 08:58 -0500, Emil Medve wrote:
> Hello Scott,
> 
> 
> On 10/28/2014 06:21 PM, Scott Wood wrote:
> > On Wed, 2014-10-22 at 09:42 -0500, Emil Medve wrote:
> >> Signed-off-by: Emil Medve <Emilian.Medve-eDlz3WWmN0ll57MIdRCFDg@public.gmane.org>
> >> Change-Id: I25ce24a25862b4ca460164159867abefe00ccdd1
> > 
> > Please remove gerrit stuff prior to submitting.
> 
> I did remove the bulk of it. I wanted to keep the Change-Id so I can
> easily correlate the upstream patches with the sordid internal history.
> Seems the upstream history has enough instances of 'Change-Id' for this
> not to be an issue

OK...

> > I don't think the mux stuff belongs here, given that clockgen2.dtsi
> > doesn't have it, and I saw at least one clockgen1 user needing to
> > supplement this with more muxes.
> 
> The intent was to put here devices/nodes that are common per chassis
> from the low to high end. Specific SoC would change/augment this as
> appropriate. I could have put each node in its own file as we've done
> elsewhere, but I thought it would be too much
> 
> Yes, chassis v1 and v2 have differences, but that's not unexpected

It just strikes me as being an awkward split of where each mux node
goes.  Is it guaranteed by the chassis that all v1 will have at least
the first two muxes?

> >> @@ -1068,7 +1043,6 @@
> >>  			clocks = <&sysclk>;
> >>  			clock-output-names = "pll2", "pll2-div2", "pll2-div4";
> >>  		};
> >> -
> >>  		pll3: pll3@860 {
> >>  			#clock-cells = <1>;
> >>  			reg = <0x860 0x4>;
> >> @@ -1076,7 +1050,6 @@
> >>  			clocks = <&sysclk>;
> >>  			clock-output-names = "pll3", "pll3-div2", "pll3-div4";
> >>  		};
> >> -
> >>  		pll4: pll4@880 {
> >>  			#clock-cells = <1>;
> >>  			reg = <0x880 0x4>;
> > 
> > Why?
> 
> Why what?

Why are you removing all these blank lines?

-Scott


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Re: [PATCH 1/3] powerpc/dts: Factorize the clock control node

[Emil Medve]

Hello Scott,


On 10/30/2014 06:21 PM, Scott Wood wrote:
>>> I don't think the mux stuff belongs here, given that clockgen2.dtsi
>>> doesn't have it, and I saw at least one clockgen1 user needing to
>>> supplement this with more muxes.
>>
>> The intent was to put here devices/nodes that are common per chassis
>> from the low to high end. Specific SoC would change/augment this as
>> appropriate. I could have put each node in its own file as we've done
>> elsewhere, but I thought it would be too much
>>
>> Yes, chassis v1 and v2 have differences, but that's not unexpected
> 
> It just strikes me as being an awkward split of where each mux node
> goes.  Is it guaranteed by the chassis that all v1 will have at least
> the first two muxes?

As far as I'm aware we're not building chassis v1 SoC(s) anymore


Cheers,
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