From: Kevin Cernekee <cernekee@gmail.com>
To: f.fainelli@gmail.com, tglx@linutronix.de, jason@lakedaemon.net,
ralf@linux-mips.org
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
mbizon@freebox.fr, jogo@openwrt.org, linux-mips@linux-mips.org
Subject: [PATCH 05/11] irqchip: bcm7120-l2: Make sure all register accesses use base+offset
Date: Tue, 28 Oct 2014 20:58:52 -0700 [thread overview]
Message-ID: <1414555138-6500-5-git-send-email-cernekee@gmail.com> (raw)
In-Reply-To: <1414555138-6500-1-git-send-email-cernekee@gmail.com>
A couple of accesses to IRQEN (base+0x00) just used "base" directly, so
they would break if IRQEN ever became nonzero. Make sure that all
reads/writes specify the register offset constant.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
drivers/irqchip/irq-bcm7120-l2.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchip/irq-bcm7120-l2.c
index 49d8f3d..6472b71 100644
--- a/drivers/irqchip/irq-bcm7120-l2.c
+++ b/drivers/irqchip/irq-bcm7120-l2.c
@@ -66,10 +66,10 @@ static void bcm7120_l2_intc_suspend(struct irq_data *d)
irq_gc_lock(gc);
/* Save the current mask and the interrupt forward mask */
- b->saved_mask = __raw_readl(b->base) | b->irq_fwd_mask;
+ b->saved_mask = __raw_readl(b->base + IRQEN) | b->irq_fwd_mask;
if (b->can_wake) {
reg = b->saved_mask | gc->wake_active;
- __raw_writel(reg, b->base);
+ __raw_writel(reg, b->base + IRQEN);
}
irq_gc_unlock(gc);
}
@@ -81,7 +81,7 @@ static void bcm7120_l2_intc_resume(struct irq_data *d)
/* Restore the saved mask */
irq_gc_lock(gc);
- __raw_writel(b->saved_mask, b->base);
+ __raw_writel(b->saved_mask, b->base + IRQEN);
irq_gc_unlock(gc);
}
--
2.1.1
next prev parent reply other threads:[~2014-10-29 3:58 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-29 3:58 [PATCH 01/11] irqchip: Allow irq_reg_{readl,writel} to use __raw_{readl_writel} Kevin Cernekee
2014-10-29 3:58 ` [PATCH 02/11] irqchip: brcmstb-l2: Eliminate dependency on ARM code Kevin Cernekee
[not found] ` <1414555138-6500-2-git-send-email-cernekee-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-10-29 7:29 ` Arnd Bergmann
2014-10-29 16:53 ` Florian Fainelli
2014-10-29 3:58 ` [PATCH 03/11] irqchip: bcm7120-l2: Eliminate bad IRQ check Kevin Cernekee
2014-10-29 16:53 ` Florian Fainelli
2014-10-29 3:58 ` [PATCH 04/11] irqchip: Remove ARM dependency for bcm7120-l2 and brcmstb-l2 Kevin Cernekee
2014-10-29 7:44 ` Arnd Bergmann
2014-10-29 16:53 ` Florian Fainelli
2014-10-29 3:58 ` Kevin Cernekee [this message]
2014-10-29 7:46 ` [PATCH 05/11] irqchip: bcm7120-l2: Make sure all register accesses use base+offset Arnd Bergmann
2014-10-29 7:56 ` Arnd Bergmann
2014-10-29 16:53 ` Florian Fainelli
2014-10-29 3:58 ` [PATCH 06/11] irqchip: bcm7120-l2: Use irq_reg_* accessors Kevin Cernekee
2014-10-29 7:46 ` Arnd Bergmann
2014-10-29 16:54 ` Florian Fainelli
2014-10-29 3:58 ` [PATCH 07/11] irqchip: brcmstb-l2: " Kevin Cernekee
[not found] ` <1414555138-6500-7-git-send-email-cernekee-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-10-29 7:46 ` Arnd Bergmann
2014-10-29 16:54 ` Florian Fainelli
2014-10-29 3:58 ` [PATCH 08/11] irqchip: bcm7120-l2: Fix missing nibble in gc->unused mask Kevin Cernekee
2014-10-29 7:47 ` Arnd Bergmann
2014-10-29 16:55 ` Florian Fainelli
2014-10-29 3:58 ` [PATCH 09/11] irqchip: bcm7120-l2: Use gc->mask_cache to simplify suspend/resume functions Kevin Cernekee
[not found] ` <1414555138-6500-9-git-send-email-cernekee-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-10-29 16:55 ` Florian Fainelli
2014-10-29 3:58 ` [PATCH 10/11] irqchip: bcm7120-l2: Extend driver to support 64+ bit controllers Kevin Cernekee
2014-10-29 7:53 ` Arnd Bergmann
2014-10-29 23:22 ` Kevin Cernekee
2014-10-30 9:10 ` Arnd Bergmann
2014-10-29 3:58 ` [PATCH 11/11] irqchip: Decouple bcm7120-l2 from brcmstb-l2 Kevin Cernekee
2014-10-29 7:55 ` Arnd Bergmann
2014-10-29 16:56 ` Florian Fainelli
2014-10-29 7:43 ` [PATCH 01/11] irqchip: Allow irq_reg_{readl,writel} to use __raw_{readl_writel} Arnd Bergmann
2014-10-29 17:36 ` Florian Fainelli
[not found] ` <54512599.4080500-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-10-29 19:14 ` Arnd Bergmann
2014-10-29 18:48 ` Kevin Cernekee
2014-10-29 19:10 ` Thomas Gleixner
2014-10-29 19:14 ` Arnd Bergmann
2014-10-29 20:09 ` Kevin Cernekee
2014-10-29 21:13 ` Arnd Bergmann
2014-10-29 21:31 ` Thomas Gleixner
2014-10-29 21:41 ` Arnd Bergmann
2014-10-29 21:50 ` Thomas Gleixner
2014-10-29 23:05 ` Kevin Cernekee
2014-10-30 9:58 ` Arnd Bergmann
2014-10-30 19:03 ` Kevin Cernekee
2014-10-30 19:52 ` Arnd Bergmann
2014-10-30 20:54 ` Kevin Cernekee
[not found] ` <CAJiQ=7C+r80Jt51NXLCk-0D2nRezBfMN9pGBVT9V8ncefGhBnQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-10-30 21:18 ` Arnd Bergmann
2014-10-29 10:12 ` Thomas Gleixner
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