From: Kevin Cernekee <cernekee@gmail.com>
To: arnd@arndb.de, f.fainelli@gmail.com, tglx@linutronix.de,
jason@lakedaemon.net, ralf@linux-mips.org, lethal@linux-sh.org
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
mbizon@freebox.fr, jogo@openwrt.org, linux-mips@linux-mips.org
Subject: [PATCH V2 15/15] irqchip: bcm7120-l2: Enable big endian register accesses on BE kernels
Date: Wed, 29 Oct 2014 19:18:08 -0700 [thread overview]
Message-ID: <1414635488-14137-16-git-send-email-cernekee@gmail.com> (raw)
In-Reply-To: <1414635488-14137-1-git-send-email-cernekee@gmail.com>
On all supported SoCs, the kernel will be built with CONFIG_CPU_BIG_ENDIAN
iff the CPU is running in BE mode. Leverage this fact to autodetect
the MMIO byte ordering to use in generic-chip.c.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
drivers/irqchip/Kconfig | 2 ++
drivers/irqchip/irq-bcm7120-l2.c | 9 ++++++---
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index afdc1f3..db44694 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -51,11 +51,13 @@ config ATMEL_AIC5_IRQ
config BCM7120_L2_IRQ
bool
select GENERIC_IRQ_CHIP
+ select GENERIC_IRQ_CHIP_BE
select IRQ_DOMAIN
config BRCMSTB_L2_IRQ
bool
select GENERIC_IRQ_CHIP
+ select GENERIC_IRQ_CHIP_BE
select IRQ_DOMAIN
config DW_APB_ICTL
diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchip/irq-bcm7120-l2.c
index e53a3a6..5324249 100644
--- a/drivers/irqchip/irq-bcm7120-l2.c
+++ b/drivers/irqchip/irq-bcm7120-l2.c
@@ -132,7 +132,7 @@ int __init bcm7120_l2_intc_of_init(struct device_node *dn,
const __be32 *map_mask;
int num_parent_irqs;
int ret = 0, len;
- unsigned int idx, irq;
+ unsigned int idx, irq, flags;
data = kzalloc(sizeof(*data), GFP_KERNEL);
if (!data)
@@ -195,9 +195,12 @@ int __init bcm7120_l2_intc_of_init(struct device_node *dn,
goto out_unmap;
}
+ flags = IRQ_GC_INIT_MASK_CACHE;
+ if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
+ flags |= IRQ_GC_BE_IO;
+
ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
- dn->full_name, handle_level_irq, clr, 0,
- IRQ_GC_INIT_MASK_CACHE);
+ dn->full_name, handle_level_irq, clr, 0, flags);
if (ret) {
pr_err("failed to allocate generic irq chip\n");
goto out_free_domain;
--
2.1.1
next prev parent reply other threads:[~2014-10-30 2:18 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-30 2:17 [PATCH V2 00/15] genirq endian fixes; bcm7120/brcmstb IRQ updates Kevin Cernekee
2014-10-30 2:17 ` [PATCH V2 01/15] irqchip: Replace irq_reg_{readl,writel} with {readl,writel} Kevin Cernekee
2014-10-30 2:17 ` [PATCH V2 02/15] sh: Eliminate unused irq_reg_{readl,writel} accessors Kevin Cernekee
2014-10-30 9:00 ` Arnd Bergmann
2014-10-30 10:43 ` Thomas Gleixner
2014-10-30 10:48 ` Arnd Bergmann
2014-10-30 15:25 ` Kevin Cernekee
2014-10-30 2:17 ` [PATCH V2 03/15] genirq: Generic chip: Move irq_reg_{readl,writel} accessors into generic-chip.c Kevin Cernekee
2014-10-30 8:43 ` Thomas Gleixner
2014-10-30 9:06 ` Arnd Bergmann
2014-10-30 10:33 ` Thomas Gleixner
2014-10-30 11:50 ` Thomas Gleixner
2014-10-30 2:17 ` [PATCH V2 04/15] genirq: Generic chip: Change irq_reg_{readl,writel} arguments Kevin Cernekee
2014-10-30 2:17 ` [PATCH V2 05/15] genirq: Generic chip: Add big endian I/O accessors Kevin Cernekee
2014-10-30 9:21 ` Arnd Bergmann
2014-10-30 12:30 ` Thomas Gleixner
2014-10-30 12:40 ` Arnd Bergmann
2014-10-30 2:17 ` [PATCH V2 06/15] genirq: Generic chip: Optimize for fixed-endian systems Kevin Cernekee
2014-10-30 4:16 ` Brian Norris
2014-10-30 9:04 ` Arnd Bergmann
2014-10-30 2:18 ` [PATCH V2 07/15] irqchip: brcmstb-l2: Eliminate dependency on ARM code Kevin Cernekee
2014-10-30 2:18 ` [PATCH V2 08/15] irqchip: bcm7120-l2: Eliminate bad IRQ check Kevin Cernekee
2014-10-30 11:09 ` Sergei Shtylyov
[not found] ` <54521C65.8060603-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
2014-10-30 19:24 ` Kevin Cernekee
2014-10-30 2:18 ` [PATCH V2 09/15] irqchip: Remove ARM dependency for bcm7120-l2 and brcmstb-l2 Kevin Cernekee
2014-10-30 11:10 ` Sergei Shtylyov
2014-10-30 11:24 ` Arnd Bergmann
2014-10-30 11:48 ` Sergei Shtylyov
2014-10-30 2:18 ` [PATCH V2 10/15] irqchip: bcm7120-l2: Make sure all register accesses use base+offset Kevin Cernekee
2014-10-30 9:12 ` Arnd Bergmann
2014-10-30 2:18 ` [PATCH V2 11/15] irqchip: bcm7120-l2: Fix missing nibble in gc->unused mask Kevin Cernekee
2014-10-30 2:18 ` [PATCH V2 12/15] irqchip: bcm7120-l2: Use gc->mask_cache to simplify suspend/resume functions Kevin Cernekee
2014-10-30 2:18 ` [PATCH V2 13/15] irqchip: bcm7120-l2: Extend driver to support 64+ bit controllers Kevin Cernekee
2014-10-30 2:18 ` [PATCH V2 14/15] irqchip: Decouple bcm7120-l2 from brcmstb-l2 Kevin Cernekee
2014-10-30 2:18 ` Kevin Cernekee [this message]
2014-10-30 9:03 ` [PATCH V2 15/15] irqchip: bcm7120-l2: Enable big endian register accesses on BE kernels Arnd Bergmann
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