* [PATCH v3 0/3] Add Reset Controller for MediaTek SoC
@ 2014-11-05 14:21 Flora Fu
2014-11-05 14:21 ` [PATCH v3 1/3] ARM: mediatek: " Flora Fu
[not found] ` <1415197292-10546-1-git-send-email-flora.fu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
0 siblings, 2 replies; 4+ messages in thread
From: Flora Fu @ 2014-11-05 14:21 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring, Matthias Brugger, arm
Cc: Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, devicetree, linux-kernel, linux-arm-kernel,
srv_heupstream, Sascha Hauer, Olof Johansson, Arnd Bergmann,
Flora Fu
Hi,
The patch is based on https://lkml.org/lkml/2014/5/27/422
Changes since v2
================
- Correct #size-cell to be 1.
- Add header file "mt8135-resets.h" for supported resets in MT8135.
Changes since v1
================
(1) Patch 1/3: Update reset controller driver's implementation.
- rename mt_ prefixes to the prefix mtk_
- use module_platform_driver() macro for driver init.
- clean up includes of header files.
- reset controll is a child of syscon. Get regamp through its parent node.
- rename data->size to data->num_regs. It is number of registers in syscon for reset usage.
(2) Patch 2/3: update bindings document according to new dts layout of reset-controller.
(3) Patch 3/3: change reset-controller device node as child of syscon.
This driver is based on 3.18-rc1.
Flora Fu (3):
ARM: mediatek: Add Reset Controller for MediaTek SoC
dt-bindings: Add Reset Controller for MediaTek SoC
ARM: dts: mt8135: Add Reset Controller for MediaTek SoC
.../devicetree/bindings/reset/mediatek,reset.txt | 50 ++++++++
arch/arm/boot/dts/mt8135.dtsi | 27 +++++
drivers/reset/Makefile | 1 +
drivers/reset/reset-mtk.c | 131 +++++++++++++++++++++
.../dt-bindings/reset-controller/mt8135-resets.h | 64 ++++++++++
5 files changed, 273 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/mediatek,reset.txt
create mode 100644 drivers/reset/reset-mtk.c
create mode 100644 include/dt-bindings/reset-controller/mt8135-resets.h
--
1.8.1.1.dirty
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH v3 1/3] ARM: mediatek: Add Reset Controller for MediaTek SoC 2014-11-05 14:21 [PATCH v3 0/3] Add Reset Controller for MediaTek SoC Flora Fu @ 2014-11-05 14:21 ` Flora Fu [not found] ` <1415197292-10546-1-git-send-email-flora.fu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> 1 sibling, 0 replies; 4+ messages in thread From: Flora Fu @ 2014-11-05 14:21 UTC (permalink / raw) To: Philipp Zabel, Rob Herring, Matthias Brugger, arm Cc: Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Grant Likely, devicetree, linux-kernel, linux-arm-kernel, srv_heupstream, Sascha Hauer, Olof Johansson, Arnd Bergmann, Flora Fu Add a driver in reset controller. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- drivers/reset/Makefile | 1 + drivers/reset/reset-mtk.c | 131 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 132 insertions(+) create mode 100644 drivers/reset/reset-mtk.c diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 60fed3d..adcebdf 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_RESET_CONTROLLER) += core.o obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o obj-$(CONFIG_ARCH_STI) += sti/ +obj-$(CONFIG_ARCH_MEDIATEK) += reset-mtk.o diff --git a/drivers/reset/reset-mtk.c b/drivers/reset/reset-mtk.c new file mode 100644 index 0000000..7d792ec --- /dev/null +++ b/drivers/reset/reset-mtk.c @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Flora.Fu <flora.fu@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/reset-controller.h> + +struct mtk_reset_data { + struct regmap *regmap; + u32 resetbase; + u32 num_regs; + struct reset_controller_dev rcdev; +}; + +static int mtk_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct regmap *regmap; + u32 addr; + u32 mask; + struct mtk_reset_data *data = container_of(rcdev, + struct mtk_reset_data, + rcdev); + regmap = data->regmap; + addr = data->resetbase + ((id / 32) << 2); + mask = BIT(id % 32); + + return regmap_update_bits(regmap, addr, mask, mask); +} + +static int mtk_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct regmap *regmap; + u32 addr; + u32 mask; + struct mtk_reset_data *data = container_of(rcdev, + struct mtk_reset_data, + rcdev); + + regmap = data->regmap; + addr = data->resetbase + ((id / 32) << 2); + mask = BIT(id % 32); + + return regmap_update_bits(regmap, addr, mask, ~mask); +} + +static struct reset_control_ops mtk_reset_ops = { + .assert = mtk_reset_assert, + .deassert = mtk_reset_deassert, +}; + +static int mtk_reset_probe(struct platform_device *pdev) +{ + struct mtk_reset_data *data; + struct device_node *np = pdev->dev.of_node; + struct device_node *syscon_np; + u32 reg[2]; + int ret; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + syscon_np = of_get_parent(np); + data->regmap = syscon_node_to_regmap(syscon_np); + of_node_put(syscon_np); + if (IS_ERR(data->regmap)) { + dev_err(&pdev->dev, "couldn't get syscon-reset regmap\n"); + return PTR_ERR(data->regmap); + } + ret = of_property_read_u32_array(np, "reg", reg, 2); + if (ret) { + dev_err(&pdev->dev, "couldn't read reset base from syscon!\n"); + return -EINVAL; + } + + data->resetbase = reg[0]; + data->num_regs = reg[1] >> 2; + data->rcdev.owner = THIS_MODULE; + data->rcdev.nr_resets = data->num_regs * 32; + data->rcdev.ops = &mtk_reset_ops; + data->rcdev.of_node = pdev->dev.of_node; + + return reset_controller_register(&data->rcdev); +} + +static int mtk_reset_remove(struct platform_device *pdev) +{ + struct mtk_reset_data *data = platform_get_drvdata(pdev); + + reset_controller_unregister(&data->rcdev); + + return 0; +} + +static const struct of_device_id mtk_reset_dt_ids[] = { + { .compatible = "mediatek,reset", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mtk_reset_dt_ids); + +static struct platform_driver mtk_reset_driver = { + .probe = mtk_reset_probe, + .remove = mtk_reset_remove, + .driver = { + .name = "mtk-reset", + .owner = THIS_MODULE, + .of_match_table = mtk_reset_dt_ids, + }, +}; + +module_platform_driver(mtk_reset_driver); + +MODULE_AUTHOR("Flora Fu <flora.fu@mediatek.com>"); +MODULE_DESCRIPTION("MediaTek SoC Generic Reset Controller"); +MODULE_LICENSE("GPL"); -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 4+ messages in thread
[parent not found: <1415197292-10546-1-git-send-email-flora.fu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>]
* [PATCH v3 2/3] dt-bindings: Add Reset Controller for MediaTek SoC [not found] ` <1415197292-10546-1-git-send-email-flora.fu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> @ 2014-11-05 14:21 ` Flora Fu 2014-11-05 14:21 ` [PATCH v3 3/3] ARM: dts: mt8135: " Flora Fu 1 sibling, 0 replies; 4+ messages in thread From: Flora Fu @ 2014-11-05 14:21 UTC (permalink / raw) To: Philipp Zabel, Rob Herring, Matthias Brugger, arm-DgEjT+Ai2ygdnm+yROfE0A Cc: Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Grant Likely, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Sascha Hauer, Olof Johansson, Arnd Bergmann, Flora Fu Add device tree bindings. Signed-off-by: Flora Fu <flora.fu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> --- .../devicetree/bindings/reset/mediatek,reset.txt | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/mediatek,reset.txt diff --git a/Documentation/devicetree/bindings/reset/mediatek,reset.txt b/Documentation/devicetree/bindings/reset/mediatek,reset.txt new file mode 100644 index 0000000..a876407 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/mediatek,reset.txt @@ -0,0 +1,50 @@ +MediaTek SoC Reset Controller +====================================== +The reset controller driver accesses registers through the syscon regmap. It +is a child node of syscon. + +Required properties: +- compatible : "mediatek,reset" +- #reset-cells: 1 +- reg: The register region can be accessed from syscon. The first parameter is + reset base address offset. The second parameter is byte width of reset registers. + +example: +infracfg: syscon@10001000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt8135-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + + infrarst: reset-controller@30 { + #reset-cells = <1>; + compatible = "mediatek,mt8135-infracfg-reset", "mediatek,reset"; + reg = <0x30 0x8>; + }; +}; + +Specifying reset lines connected to IP modules +============================================== + +The reset controller(mtk-reset) manages various reset sources. Those device nodes should +specify the reset line on the rstc in their resets property, containing a phandle to the +rstc device node and a RESET_INDEX specifying which module to reset, as described in +reset.txt. + +For MediaTek SoC, RESET_INDEX is reset bit defined in INFRACFG or PERICFG registers. + +example: +pwrap: pwrap@1000f000 { + compatible = "mediatek,mt8135-pwrap"; + reg = <0 0x1000f000 0 0x1000>, + <0 0x11017000 0 0x1000>; + reg-names = "pwrap-base", + "pwrap-bridge-base"; + resets = <&infrarst MT8135_INFRA_PMIC_WRAP_RST>, + <&perirst MT8135_PERI_PWRAP_BRIDGE_SW_RST>; + reset-names = "infrarst", "perirst"; +}; + +Definitions for the supported resets by IC: +MT8135: +include/dt-bindings/reset-controller/mt8135-resets.h -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v3 3/3] ARM: dts: mt8135: Add Reset Controller for MediaTek SoC [not found] ` <1415197292-10546-1-git-send-email-flora.fu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> 2014-11-05 14:21 ` [PATCH v3 2/3] dt-bindings: " Flora Fu @ 2014-11-05 14:21 ` Flora Fu 1 sibling, 0 replies; 4+ messages in thread From: Flora Fu @ 2014-11-05 14:21 UTC (permalink / raw) To: Philipp Zabel, Rob Herring, Matthias Brugger, arm-DgEjT+Ai2ygdnm+yROfE0A Cc: Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Grant Likely, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Sascha Hauer, Olof Johansson, Arnd Bergmann, Flora Fu Add reset controller to MT8135 board dts. Signed-off-by: Flora Fu <flora.fu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> --- arch/arm/boot/dts/mt8135.dtsi | 27 +++++++++ .../dt-bindings/reset-controller/mt8135-resets.h | 64 ++++++++++++++++++++++ 2 files changed, 91 insertions(+) create mode 100644 include/dt-bindings/reset-controller/mt8135-resets.h diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi index 90a56ad..370c8fc 100644 --- a/arch/arm/boot/dts/mt8135.dtsi +++ b/arch/arm/boot/dts/mt8135.dtsi @@ -14,6 +14,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset-controller/mt8135-resets.h> #include "skeleton64.dtsi" / { @@ -102,6 +103,32 @@ clock-names = "system-clk", "rtc-clk"; }; + infracfg: syscon@10001000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt8135-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + + infrarst: reset-controller@30 { + #reset-cells = <1>; + compatible = "mediatek,mt8135-infracfg-reset", "mediatek,reset"; + reg = <0x30 0x8>; + }; + }; + + pericfg: syscon@10003000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt8135-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + + perirst: reset-controller@00 { + #reset-cells = <1>; + compatible = "mediatek,mt8135-pericfg-reset", "mediatek,reset"; + reg = <0x00 0x8>; + }; + }; + gic: interrupt-controller@10211000 { compatible = "arm,cortex-a15-gic"; interrupt-controller; diff --git a/include/dt-bindings/reset-controller/mt8135-resets.h b/include/dt-bindings/reset-controller/mt8135-resets.h new file mode 100644 index 0000000..1bd15fe --- /dev/null +++ b/include/dt-bindings/reset-controller/mt8135-resets.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Flora.Fu <flora.fu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8135 + +/* INFRACFG RESETS */ +#define MT8135_INFRA_EMI_REG_RST 0 +#define MT8135_INFRA_DRAMC0_A0_RST 1 +#define MT8135_INFRA_CCIF0_RST 2 +#define MT8135_INFRA_APCIRQ_EINT_RST 3 +#define MT8135_INFRA_APXGPT_RST 4 +#define MT8135_INFRA_SCPSYS_RST 5 +#define MT8135_INFRA_CCIF1_RST 6 +#define MT8135_INFRA_PMIC_WRAP_RST 7 +#define MT8135_INFRA_KP_RST 8 +#define MT8135_INFRA_EMI_RST 32 +#define MT8135_INFRA_DRAMC0_RST 34 +#define MT8135_INFRA_SMI_RST 35 +#define MT8135_INFRA_M4U_RST 36 + +/* PERICFG RESETS */ +#define MT8135_PERI_UART0_SW_RST 0 +#define MT8135_PERI_UART1_SW_RST 1 +#define MT8135_PERI_UART2_SW_RST 2 +#define MT8135_PERI_UART3_SW_RST 3 +#define MT8135_PERI_IRDA_SW_RST 4 +#define MT8135_PERI_PTP_SW_RST 5 +#define MT8135_PERI_AP_HIF_SW_RST 6 +#define MT8135_PERI_GPCU_SW_RST 7 +#define MT8135_PERI_MD_HIF_SW_RST 8 +#define MT8135_PERI_NLI_SW_RST 9 +#define MT8135_PERI_AUXADC_SW_RST 10 +#define MT8135_PERI_DMA_SW_RST 11 +#define MT8135_PERI_NFI_SW_RST 14 +#define MT8135_PERI_PWM_SW_RST 15 +#define MT8135_PERI_THERM_SW_RST 16 +#define MT8135_PERI_MSDC0_SW_RST 17 +#define MT8135_PERI_MSDC1_SW_RST 18 +#define MT8135_PERI_MSDC2_SW_RST 19 +#define MT8135_PERI_MSDC3_SW_RST 20 +#define MT8135_PERI_I2C0_SW_RST 22 +#define MT8135_PERI_I2C1_SW_RST 23 +#define MT8135_PERI_I2C2_SW_RST 24 +#define MT8135_PERI_I2C3_SW_RST 25 +#define MT8135_PERI_I2C4_SW_RST 26 +#define MT8135_PERI_I2C5_SW_RST 27 +#define MT8135_PERI_I2C6_SW_RST 28 +#define MT8135_PERI_USB_SW_RST 29 +#define MT8135_PERI_SPI1_SW_RST 33 +#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */ \ No newline at end of file -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 4+ messages in thread
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2014-11-05 14:21 [PATCH v3 0/3] Add Reset Controller for MediaTek SoC Flora Fu
2014-11-05 14:21 ` [PATCH v3 1/3] ARM: mediatek: " Flora Fu
[not found] ` <1415197292-10546-1-git-send-email-flora.fu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2014-11-05 14:21 ` [PATCH v3 2/3] dt-bindings: " Flora Fu
2014-11-05 14:21 ` [PATCH v3 3/3] ARM: dts: mt8135: " Flora Fu
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