From mboxrd@z Thu Jan 1 00:00:00 1970 From: Caesar Wang Subject: [PATCH v8 3/3] ARM: dts: add rk3288 power-domain node Date: Thu, 6 Nov 2014 14:22:41 +0800 Message-ID: <1415254961-5746-4-git-send-email-caesar.wang@rock-chips.com> References: <1415254961-5746-1-git-send-email-caesar.wang@rock-chips.com> Return-path: In-Reply-To: <1415254961-5746-1-git-send-email-caesar.wang@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org To: linus.walleij@linaro.org, linux-arm-kernel@lists.infradead.org, Heiko Stuebner , Russell King Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Grant Likely , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Randy Dunlap , linux-doc@vger.kernel.org, dianders@chromium.org, linux-rockchip@lists.infradead.org, Ulf Hansson , Dmitry Torokhov , fzf@rock-chips.com, cf@rock-chips.com, caesar.wang@rock-chips.com, Jack Dai , "jinkun.hong" List-Id: devicetree@vger.kernel.org Signed-off-by: Jack Dai Signed-off-by: jinkun.hong Signed-off-by: Caesar Wang --- Changes in v8: - DTS go back to v2 Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: - Decomposition power-controller, changed to multiple controller (gpu-power-controller, hevc-power-controller) Changes in v2: - make pd_vio clocks all one entry per line and alphabetize. - power: power-controller move back to pinctrl: pinctrl. arch/arm/boot/dts/rk3288.dtsi | 66 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index cb18bb4..9cd269a 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -989,4 +989,70 @@ }; }; }; + + power: power-controller { + compatible = "rockchip,rk3288-power-controller"; + #power-domain-cells = <1>; + rockchip,pmu = <&pmu>; + #address-cells = <1>; + #size-cells = <0>; + + pd_gpu { + reg = ; + clocks = <&cru ACLK_GPU>; + }; + + pd_hevc { + reg = ; + clocks = <&cru ACLK_HEVC>, + <&cru SCLK_HEVC_CABAC>, + <&cru SCLK_HEVC_CORE>, + <&cru HCLK_HEVC>; + }; + + pd_vio { + reg = ; + clocks = <&cru ACLK_IEP>, + <&cru ACLK_ISP>, + <&cru ACLK_RGA_NIU>, + <&cru ACLK_RGA>, + <&cru ACLK_VIO0_NIU>, + <&cru ACLK_VIO1_NIU>, + <&cru ACLK_VIP>, + <&cru ACLK_VOP0>, + <&cru ACLK_VOP1>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru HCLK_IEP>, + <&cru HCLK_ISP>, + <&cru HCLK_RGA>, + <&cru HCLK_VIO_AHB_ARBI>, + <&cru HCLK_VIO_NIU>, + <&cru HCLK_VIO2_H2P>, + <&cru HCLK_VIP>, + <&cru HCLK_VOP0>, + <&cru HCLK_VOP1>, + <&cru PCLK_EDP_CTRL>, + <&cru PCLK_HDMI_CTRL>, + <&cru PCLK_LVDS_PHY>, + <&cru PCLK_MIPI_CSI>, + <&cru PCLK_MIPI_DSI0>, + <&cru PCLK_MIPI_DSI1>, + <&cru PCLK_VIO2_H2P>, + <&cru SCLK_EDP_24M>, + <&cru SCLK_EDP>, + <&cru SCLK_HDMI_CEC>, + <&cru SCLK_HDMI_HDCP>, + <&cru SCLK_ISP_JPE>, + <&cru SCLK_ISP>, + <&cru SCLK_RGA>; + }; + + pd_video { + reg = ; + /* FIXME: add clocks */ + clocks = <&cru ACLK_VCODEC>, + <&cru HCLK_VCODEC>; + }; + }; }; -- 1.9.1