[parent not found: <1416242884-5261-1-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>]
* [PATCH v3 01/11] ARM: STi: DT: STiH416: Add pinctl setup for usb controllers.
[not found] ` <1416242884-5261-1-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
@ 2014-11-17 16:47 ` Peter Griffin
2014-11-17 16:47 ` [PATCH v3 04/11] ARM: multi_v7_defconfig: Enable st ohci and ehci HCD drivers Peter Griffin
` (3 subsequent siblings)
4 siblings, 0 replies; 14+ messages in thread
From: Peter Griffin @ 2014-11-17 16:47 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, maxime.coquelin-qxv4g6HH51o,
srinivas.kandagatla-Re5JQEeQqe8AvxtiuMwx3w,
patrice.chotard-qxv4g6HH51o, arnd-r2nGTMty4D4
Cc: peter.griffin-QSEj5FYQhm4dnm+yROfE0A,
lee.jones-QSEj5FYQhm4dnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA
This patch adds the required pin config for all usb controllers
on the stih416.
Signed-off-by: Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Acked-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
arch/arm/boot/dts/stih416-pinctrl.dtsi | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index c2025bc..9cccf2d 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -147,6 +147,15 @@
};
};
+ usb {
+ pinctrl_usb3: usb3 {
+ st,pins {
+ oc-detect = <&pio40 0 ALT1 IN>;
+ pwr-enable = <&pio40 1 ALT1 OUT>;
+ };
+ };
+ };
+
sbc_i2c1 {
pinctrl_sbc_i2c1_default: sbc_i2c1-default {
st,pins {
@@ -318,6 +327,16 @@
};
};
+ usb {
+ pinctrl_usb0: usb0 {
+ st,pins {
+ oc-detect = <&pio9 4 ALT1 IN>;
+ pwr-enable = <&pio9 5 ALT1 OUT>;
+ };
+ };
+ };
+
+
i2c1 {
pinctrl_i2c1_default: i2c1-default {
st,pins {
@@ -506,6 +525,21 @@
};
};
};
+
+ usb {
+ pinctrl_usb1: usb1 {
+ st,pins {
+ oc-detect = <&pio18 0 ALT1 IN>;
+ pwr-enable = <&pio18 1 ALT1 OUT>;
+ };
+ };
+ pinctrl_usb2: usb2 {
+ st,pins {
+ oc-detect = <&pio18 2 ALT1 IN>;
+ pwr-enable = <&pio18 3 ALT1 OUT>;
+ };
+ };
+ };
};
pin-controller-fvdp-fe {
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 04/11] ARM: multi_v7_defconfig: Enable st ohci and ehci HCD drivers.
[not found] ` <1416242884-5261-1-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2014-11-17 16:47 ` [PATCH v3 01/11] ARM: STi: DT: STiH416: Add pinctl setup for usb controllers Peter Griffin
@ 2014-11-17 16:47 ` Peter Griffin
2014-11-17 16:47 ` [PATCH v3 06/11] ARM: STi: DT: STiH410: Add defines for STiH410 DT clocks Peter Griffin
` (2 subsequent siblings)
4 siblings, 0 replies; 14+ messages in thread
From: Peter Griffin @ 2014-11-17 16:47 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, maxime.coquelin-qxv4g6HH51o,
srinivas.kandagatla-Re5JQEeQqe8AvxtiuMwx3w,
patrice.chotard-qxv4g6HH51o, arnd-r2nGTMty4D4
Cc: peter.griffin-QSEj5FYQhm4dnm+yROfE0A,
lee.jones-QSEj5FYQhm4dnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA
Enable the ehci and ohci drivers in the multi_v7_defconfig so that
the USB controllers on stih41x work by default.
Signed-off-by: Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Acked-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
arch/arm/configs/multi_v7_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 491b7d5..c7a9517 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -318,9 +318,11 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_MVEBU=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_EHCI_HCD_STI=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_ISP1760_HCD=y
CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_STI=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_CHIPIDEA=y
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 06/11] ARM: STi: DT: STiH410: Add defines for STiH410 DT clocks
[not found] ` <1416242884-5261-1-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2014-11-17 16:47 ` [PATCH v3 01/11] ARM: STi: DT: STiH416: Add pinctl setup for usb controllers Peter Griffin
2014-11-17 16:47 ` [PATCH v3 04/11] ARM: multi_v7_defconfig: Enable st ohci and ehci HCD drivers Peter Griffin
@ 2014-11-17 16:47 ` Peter Griffin
2014-11-17 16:48 ` [PATCH v3 11/11] ARM: STi: DT: STiH416: Change miphy356 node name to phy@fe382000 Peter Griffin
2014-11-18 8:47 ` [PATCH v3 00/11] Add stih410 SoC/board and USB2/1.1 support for stih416 Maxime Coquelin
4 siblings, 0 replies; 14+ messages in thread
From: Peter Griffin @ 2014-11-17 16:47 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, maxime.coquelin-qxv4g6HH51o,
srinivas.kandagatla-Re5JQEeQqe8AvxtiuMwx3w,
patrice.chotard-qxv4g6HH51o, arnd-r2nGTMty4D4
Cc: peter.griffin-QSEj5FYQhm4dnm+yROfE0A,
lee.jones-QSEj5FYQhm4dnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA
Although most clock outputs are the same as stih407 SoC, stih410
also has some additional new clock outputs.
Signed-off-by: Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Acked-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
include/dt-bindings/clock/stih410-clks.h | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
create mode 100644 include/dt-bindings/clock/stih410-clks.h
diff --git a/include/dt-bindings/clock/stih410-clks.h b/include/dt-bindings/clock/stih410-clks.h
new file mode 100644
index 0000000..2097a4b
--- /dev/null
+++ b/include/dt-bindings/clock/stih410-clks.h
@@ -0,0 +1,25 @@
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH410 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH410
+#define _DT_BINDINGS_CLK_STIH410
+
+#include "stih407-clks.h"
+
+/* STiH410 introduces new clock outputs compared to STiH407 */
+
+/* CLOCKGEN C0 */
+#define CLK_TX_ICN_HADES 32
+#define CLK_RX_ICN_HADES 33
+#define CLK_ICN_REG_16 34
+#define CLK_PP_HADES 35
+#define CLK_CLUST_HADES 36
+#define CLK_HWPE_HADES 37
+#define CLK_FC_HADES 38
+
+/* CLOCKGEN D0 */
+#define CLK_PCMR10_MASTER 4
+#define CLK_USB2_PHY 5
+
+#endif
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 11/11] ARM: STi: DT: STiH416: Change miphy356 node name to phy@fe382000
[not found] ` <1416242884-5261-1-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
` (2 preceding siblings ...)
2014-11-17 16:47 ` [PATCH v3 06/11] ARM: STi: DT: STiH410: Add defines for STiH410 DT clocks Peter Griffin
@ 2014-11-17 16:48 ` Peter Griffin
2014-11-18 8:47 ` [PATCH v3 00/11] Add stih410 SoC/board and USB2/1.1 support for stih416 Maxime Coquelin
4 siblings, 0 replies; 14+ messages in thread
From: Peter Griffin @ 2014-11-17 16:48 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, maxime.coquelin-qxv4g6HH51o,
srinivas.kandagatla-Re5JQEeQqe8AvxtiuMwx3w,
patrice.chotard-qxv4g6HH51o, arnd-r2nGTMty4D4
Cc: peter.griffin-QSEj5FYQhm4dnm+yROfE0A,
lee.jones-QSEj5FYQhm4dnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA
Following Arnds review comments, update the miphy365 to follow the
common convention of naming the phy node names as phy@addr.
Signed-off-by: Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Suggested-by: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
---
arch/arm/boot/dts/stih416-b2020.dts | 2 +-
arch/arm/boot/dts/stih416-b2020e.dts | 2 +-
arch/arm/boot/dts/stih416.dtsi | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts
index 5d1543b..200a818 100644
--- a/arch/arm/boot/dts/stih416-b2020.dts
+++ b/arch/arm/boot/dts/stih416-b2020.dts
@@ -20,7 +20,7 @@
non-removable;
};
- miphy365x_phy: miphy365x@fe382000 {
+ miphy365x_phy: phy@fe382000 {
phy_port0: port@fe382000 {
st,sata-gen = <3>;
};
diff --git a/arch/arm/boot/dts/stih416-b2020e.dts b/arch/arm/boot/dts/stih416-b2020e.dts
index 956fab8..961799e 100644
--- a/arch/arm/boot/dts/stih416-b2020e.dts
+++ b/arch/arm/boot/dts/stih416-b2020e.dts
@@ -38,7 +38,7 @@
non-removable;
};
- miphy365x_phy: miphy365x@fe382000 {
+ miphy365x_phy: phy@fe382000 {
phy_port0: port@fe382000 {
st,sata-gen = <3>;
};
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 2bdda52..fad9073 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -281,7 +281,7 @@
clocks = <&clk_s_a1_ls 8>;
};
- miphy365x_phy: miphy365x@fe382000 {
+ miphy365x_phy: phy@fe382000 {
compatible = "st,miphy365x-phy";
st,syscfg = <&syscfg_rear>;
#address-cells = <1>;
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v3 00/11] Add stih410 SoC/board and USB2/1.1 support for stih416
[not found] ` <1416242884-5261-1-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
` (3 preceding siblings ...)
2014-11-17 16:48 ` [PATCH v3 11/11] ARM: STi: DT: STiH416: Change miphy356 node name to phy@fe382000 Peter Griffin
@ 2014-11-18 8:47 ` Maxime Coquelin
[not found] ` <546B07BD.4030400-qxv4g6HH51o@public.gmane.org>
4 siblings, 1 reply; 14+ messages in thread
From: Maxime Coquelin @ 2014-11-18 8:47 UTC (permalink / raw)
To: Peter Griffin, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
srinivas.kandagatla-Re5JQEeQqe8AvxtiuMwx3w,
patrice.chotard-qxv4g6HH51o, arnd-r2nGTMty4D4
Cc: lee.jones-QSEj5FYQhm4dnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA
On 11/17/2014 05:47 PM, Peter Griffin wrote:
> Hi folks,
>
> This series adds the required device tree nodes to enable the usb2/1.1 phy
> and usb2/1.1 controllers on the stih416-b2120 board.
>
> It additionally re-works and adds support for the new stih410 SoC which is
> very similar to the stih407 SoC, by abstracting out the common parts
> into common dt files.
>
> After Arnds feedback regarding mixing address spaces in the stih407-picophy
> dt nodes, I've tempoarily removed these patches from the series until the
> underlying driver has been fixed, as ideally I would like to get the rest
> of this series into 3.19
>
> As well as adding dt nodes it also enables the relevant drivers in the
> multi_v7_defconfig.
>
> Finally we update the default bootargs for stih407-b2120 and stih410-b2120
> to boot with the clk_ignore_unused kernel parameter so as not to hang
> the SoC when the (as yet) unreferenced interconnect clocks get disabled
> by CCF (this is a tempoary solution).
>
> This series has been tested on stih416-b2020 and stih410-b2120 SoC/boards.
>
> Changes since v1:
> - Leave bootargs & memory dt nodes in board files (Arnd)
> - Remove '0x' from the unit address in all instances. (Arnd)
> - Remove 'status="okay"' from some nodes (Arnd)
> - Remove some legacy extra nodes which only contain status property (Arnd)
> - Fix stih410 commit description (Maxime)
> - Add a stih410.dtsi and stih410-pinctrl.dtsi files (Maxime)
> - Remove superflous '\n' (Lee)
> - Add a '\n' between the sentries and #include (Lee)
>
> Changes since v2:
> - Remove picophy and ehci/ohci dt nodes for stih407 / stih410 until reg binding is fixed
> - Update miphy365 over to common convention of phy@ (Arnd)
>
> Peter Griffin (11):
> ARM: STi: DT: STiH416: Add pinctl setup for usb controllers.
> ARM: STi: DT: STiH416: Add DT node for the stih415/6 usb2 phy
> ARM: STi: DT: STiH416: Add DT nodes for the ehci and ohci usb
> controllers.
> ARM: multi_v7_defconfig: Enable st ohci and ehci HCD drivers.
> ARM: multi_v7_defconfig: Enable stih415/6 usb2 phy driver.
> ARM: STi: DT: STiH410: Add defines for STiH410 DT clocks
> ARM: STi: DT: STiH410: Add pinctl config for usb controllers.
> ARM: STi: DT: STih407: Abstract common dt nodes into shared files.
> ARM: STi: DT: STiH410: Add STiH410 SoC and b2120 board support.
> ARM: STi: DT: STih407: STih410: Add clk_ignore_unused to kernel
> bootargs
> ARM: STi: DT: STiH416: Change miphy356 node name to phy@fe382000
For the series,
Acked-by: Maxime Coquelin <maxime.coquelin-qxv4g6HH51o@public.gmane.org>
If Arnd is fine with the series, these patches will be part of my
next pull request.
Regards,
Maxime
>
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/stih407-b2120.dts | 55 +----
> arch/arm/boot/dts/stih407-family.dtsi | 278 +++++++++++++++++++++++++
> arch/arm/boot/dts/stih407.dtsi | 279 -------------------------
> arch/arm/boot/dts/stih410-b2120.dts | 29 +++
> arch/arm/boot/dts/stih410-clock.dtsi | 338 +++++++++++++++++++++++++++++++
> arch/arm/boot/dts/stih410-pinctrl.dtsi | 34 ++++
> arch/arm/boot/dts/stih410.dtsi | 14 ++
> arch/arm/boot/dts/stih416-b2020.dts | 2 +-
> arch/arm/boot/dts/stih416-b2020e.dts | 2 +-
> arch/arm/boot/dts/stih416-pinctrl.dtsi | 34 ++++
> arch/arm/boot/dts/stih416.dtsi | 131 +++++++++++-
> arch/arm/boot/dts/stihxxx-b2120.dtsi | 59 ++++++
> arch/arm/configs/multi_v7_defconfig | 3 +
> include/dt-bindings/clock/stih410-clks.h | 25 +++
> 15 files changed, 951 insertions(+), 333 deletions(-)
> create mode 100644 arch/arm/boot/dts/stih407-family.dtsi
> delete mode 100644 arch/arm/boot/dts/stih407.dtsi
> create mode 100644 arch/arm/boot/dts/stih410-b2120.dts
> create mode 100644 arch/arm/boot/dts/stih410-clock.dtsi
> create mode 100644 arch/arm/boot/dts/stih410-pinctrl.dtsi
> create mode 100644 arch/arm/boot/dts/stih410.dtsi
> create mode 100644 arch/arm/boot/dts/stihxxx-b2120.dtsi
> create mode 100644 include/dt-bindings/clock/stih410-clks.h
>
--
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 02/11] ARM: STi: DT: STiH416: Add DT node for the stih415/6 usb2 phy
2014-11-17 16:47 [PATCH v3 00/11] Add stih410 SoC/board and USB2/1.1 support for stih416 Peter Griffin
[not found] ` <1416242884-5261-1-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
@ 2014-11-17 16:47 ` Peter Griffin
2014-11-17 16:47 ` [PATCH v3 03/11] ARM: STi: DT: STiH416: Add DT nodes for the ehci and ohci usb controllers Peter Griffin
` (5 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Peter Griffin @ 2014-11-17 16:47 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, maxime.coquelin,
srinivas.kandagatla, patrice.chotard, arnd
Cc: peter.griffin, devicetree, lee.jones
This usb picophy is found on stih415/6 SoC.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm/boot/dts/stih416.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 1137bdf..ff2ad35 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -316,5 +316,13 @@
status = "disabled";
};
+
+ usb2_phy: phy@0 {
+ compatible = "st,stih416-usb-phy";
+ #phy-cells = <0>;
+ st,syscfg = <&syscfg_rear>;
+ clocks = <&clk_sysin>;
+ clock-names = "osc_phy";
+ };
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 03/11] ARM: STi: DT: STiH416: Add DT nodes for the ehci and ohci usb controllers.
2014-11-17 16:47 [PATCH v3 00/11] Add stih410 SoC/board and USB2/1.1 support for stih416 Peter Griffin
[not found] ` <1416242884-5261-1-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2014-11-17 16:47 ` [PATCH v3 02/11] ARM: STi: DT: STiH416: Add DT node for the stih415/6 usb2 phy Peter Griffin
@ 2014-11-17 16:47 ` Peter Griffin
2014-11-17 16:47 ` [PATCH v3 05/11] ARM: multi_v7_defconfig: Enable stih415/6 usb2 phy driver Peter Griffin
` (4 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Peter Griffin @ 2014-11-17 16:47 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, maxime.coquelin,
srinivas.kandagatla, patrice.chotard, arnd
Cc: peter.griffin, devicetree, lee.jones
This patch adds the DT nodes for the 4 usb ehci and ohci usb controllers
on the stih416 SoC.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm/boot/dts/stih416.dtsi | 121 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index ff2ad35..2bdda52 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -324,5 +324,126 @@
clocks = <&clk_sysin>;
clock-names = "osc_phy";
};
+
+ ehci0: usb@fe1ffe00 {
+ compatible = "st,st-ehci-300x";
+ reg = <0xfe1ffe00 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ clocks = <&clk_s_a1_ls 0>,
+ <&clockgen_b0 0>;
+ clock-names = "ic", "clk48";
+ phys = <&usb2_phy>;
+ phy-names = "usb";
+ resets = <&powerdown STIH416_USB0_POWERDOWN>,
+ <&softreset STIH416_USB0_SOFTRESET>;
+ reset-names = "power", "softreset";
+ };
+
+ ohci0: usb@fe1ffc00 {
+ compatible = "st,st-ohci-300x";
+ reg = <0xfe1ffc00 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
+ clocks = <&clk_s_a1_ls 0>,
+ <&clockgen_b0 0>;
+ clock-names = "ic", "clk48";
+ phys = <&usb2_phy>;
+ phy-names = "usb";
+ status = "okay";
+ resets = <&powerdown STIH416_USB0_POWERDOWN>,
+ <&softreset STIH416_USB0_SOFTRESET>;
+ reset-names = "power", "softreset";
+ };
+
+ ehci1: usb@fe203e00 {
+ compatible = "st,st-ehci-300x";
+ reg = <0xfe203e00 0x100>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ clocks = <&clk_s_a1_ls 0>,
+ <&clockgen_b0 0>;
+ clock-names = "ic", "clk48";
+ phys = <&usb2_phy>;
+ phy-names = "usb";
+ resets = <&powerdown STIH416_USB1_POWERDOWN>,
+ <&softreset STIH416_USB1_SOFTRESET>;
+ reset-names = "power", "softreset";
+ };
+
+ ohci1: usb@fe203c00 {
+ compatible = "st,st-ohci-300x";
+ reg = <0xfe203c00 0x100>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
+ clocks = <&clk_s_a1_ls 0>,
+ <&clockgen_b0 0>;
+ clock-names = "ic", "clk48";
+ phys = <&usb2_phy>;
+ phy-names = "usb";
+ resets = <&powerdown STIH416_USB1_POWERDOWN>,
+ <&softreset STIH416_USB1_SOFTRESET>;
+ reset-names = "power", "softreset";
+ };
+
+ ehci2: usb@fe303e00 {
+ compatible = "st,st-ehci-300x";
+ reg = <0xfe303e00 0x100>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ clocks = <&clk_s_a1_ls 0>,
+ <&clockgen_b0 0>;
+ clock-names = "ic", "clk48";
+ phys = <&usb2_phy>;
+ phy-names = "usb";
+ resets = <&powerdown STIH416_USB2_POWERDOWN>,
+ <&softreset STIH416_USB2_SOFTRESET>;
+ reset-names = "power", "softreset";
+ };
+
+ ohci2: usb@fe303c00 {
+ compatible = "st,st-ohci-300x";
+ reg = <0xfe303c00 0x100>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
+ clocks = <&clk_s_a1_ls 0>,
+ <&clockgen_b0 0>;
+ clock-names = "ic", "clk48";
+ phys = <&usb2_phy>;
+ phy-names = "usb";
+ resets = <&powerdown STIH416_USB2_POWERDOWN>,
+ <&softreset STIH416_USB2_SOFTRESET>;
+ reset-names = "power", "softreset";
+ };
+
+ ehci3: usb@fe343e00 {
+ compatible = "st,st-ehci-300x";
+ reg = <0xfe343e00 0x100>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3>;
+ clocks = <&clk_s_a1_ls 0>,
+ <&clockgen_b0 0>;
+ clock-names = "ic", "clk48";
+ phys = <&usb2_phy>;
+ phy-names = "usb";
+ resets = <&powerdown STIH416_USB3_POWERDOWN>,
+ <&softreset STIH416_USB3_SOFTRESET>;
+ reset-names = "power", "softreset";
+ };
+
+ ohci3: usb@fe343c00 {
+ compatible = "st,st-ohci-300x";
+ reg = <0xfe343c00 0x100>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
+ clocks = <&clk_s_a1_ls 0>,
+ <&clockgen_b0 0>;
+ clock-names = "ic", "clk48";
+ phys = <&usb2_phy>;
+ phy-names = "usb";
+ resets = <&powerdown STIH416_USB3_POWERDOWN>,
+ <&softreset STIH416_USB3_SOFTRESET>;
+ reset-names = "power", "softreset";
+ };
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 05/11] ARM: multi_v7_defconfig: Enable stih415/6 usb2 phy driver.
2014-11-17 16:47 [PATCH v3 00/11] Add stih410 SoC/board and USB2/1.1 support for stih416 Peter Griffin
` (2 preceding siblings ...)
2014-11-17 16:47 ` [PATCH v3 03/11] ARM: STi: DT: STiH416: Add DT nodes for the ehci and ohci usb controllers Peter Griffin
@ 2014-11-17 16:47 ` Peter Griffin
2014-11-17 16:48 ` [PATCH v3 07/11] ARM: STi: DT: STiH410: Add pinctl config for usb controllers Peter Griffin
` (3 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Peter Griffin @ 2014-11-17 16:47 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, maxime.coquelin,
srinivas.kandagatla, patrice.chotard, arnd
Cc: peter.griffin, lee.jones, devicetree
This driver is used by the ehci / ohci usb controllers on stih415/6 SoCs.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index c7a9517..e13ab7e 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -426,6 +426,7 @@ CONFIG_PWM_VT8500=y
CONFIG_OMAP_USB2=y
CONFIG_TI_PIPE3=y
CONFIG_PHY_MIPHY365X=y
+CONFIG_PHY_STIH41X_USB=y
CONFIG_PHY_SUN4I_USB=y
CONFIG_EXT4_FS=y
CONFIG_VFAT_FS=y
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 07/11] ARM: STi: DT: STiH410: Add pinctl config for usb controllers.
2014-11-17 16:47 [PATCH v3 00/11] Add stih410 SoC/board and USB2/1.1 support for stih416 Peter Griffin
` (3 preceding siblings ...)
2014-11-17 16:47 ` [PATCH v3 05/11] ARM: multi_v7_defconfig: Enable stih415/6 usb2 phy driver Peter Griffin
@ 2014-11-17 16:48 ` Peter Griffin
2014-11-17 16:48 ` [PATCH v3 08/11] ARM: STi: DT: STih407: Abstract common dt nodes into shared files Peter Griffin
` (2 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Peter Griffin @ 2014-11-17 16:48 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, maxime.coquelin,
srinivas.kandagatla, patrice.chotard, arnd
Cc: peter.griffin, lee.jones, devicetree
This patch adds the required pin configiguration for the extra usb
controllers found on the stih410 device.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm/boot/dts/stih410-pinctrl.dtsi | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 arch/arm/boot/dts/stih410-pinctrl.dtsi
diff --git a/arch/arm/boot/dts/stih410-pinctrl.dtsi b/arch/arm/boot/dts/stih410-pinctrl.dtsi
new file mode 100644
index 0000000..b3e9dfc
--- /dev/null
+++ b/arch/arm/boot/dts/stih410-pinctrl.dtsi
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics Limited.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "st-pincfg.h"
+/ {
+
+ soc {
+ pin-controller-rear {
+
+ usb0 {
+ pinctrl_usb0: usb2-0 {
+ st,pins {
+ usb-oc-detect = <&pio35 0 ALT1 IN>;
+ usb-pwr-enable = <&pio35 1 ALT1 OUT>;
+ };
+ };
+ };
+
+ usb1 {
+ pinctrl_usb1: usb2-1 {
+ st,pins {
+ usb-oc-detect = <&pio35 2 ALT1 IN>;
+ usb-pwr-enable = <&pio35 3 ALT1 OUT>;
+ };
+ };
+ };
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 08/11] ARM: STi: DT: STih407: Abstract common dt nodes into shared files.
2014-11-17 16:47 [PATCH v3 00/11] Add stih410 SoC/board and USB2/1.1 support for stih416 Peter Griffin
` (4 preceding siblings ...)
2014-11-17 16:48 ` [PATCH v3 07/11] ARM: STi: DT: STiH410: Add pinctl config for usb controllers Peter Griffin
@ 2014-11-17 16:48 ` Peter Griffin
2014-11-17 16:48 ` [PATCH v3 09/11] ARM: STi: DT: STiH410: Add STiH410 SoC and b2120 board support Peter Griffin
2014-11-17 16:48 ` [PATCH v3 10/11] ARM: STi: DT: STih407: STih410: Add clk_ignore_unused to kernel bootargs Peter Griffin
7 siblings, 0 replies; 14+ messages in thread
From: Peter Griffin @ 2014-11-17 16:48 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, maxime.coquelin,
srinivas.kandagatla, patrice.chotard, arnd
Cc: peter.griffin, lee.jones, devicetree
The stih410 soc which will be added in the following commit is very similar to
the stih407, to enable maximum re-use of the dt files this commit abstracts the
common parts into a shared dt file stihxxx-b2120 for the board, and also a shared
file stih407-family.dtsi for the SoC.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm/boot/dts/stih407-b2120.dts | 53 +------
arch/arm/boot/dts/stih407-family.dtsi | 278 +++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stih407.dtsi | 279 ----------------------------------
arch/arm/boot/dts/stihxxx-b2120.dtsi | 59 +++++++
4 files changed, 340 insertions(+), 329 deletions(-)
create mode 100644 arch/arm/boot/dts/stih407-family.dtsi
delete mode 100644 arch/arm/boot/dts/stih407.dtsi
create mode 100644 arch/arm/boot/dts/stihxxx-b2120.dtsi
diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts
index fe69f92..a3ad52b 100644
--- a/arch/arm/boot/dts/stih407-b2120.dts
+++ b/arch/arm/boot/dts/stih407-b2120.dts
@@ -7,7 +7,9 @@
* published by the Free Software Foundation.
*/
/dts-v1/;
-#include "stih407.dtsi"
+#include "stih407-clock.dtsi"
+#include "stih407-family.dtsi"
+#include "stihxxx-b2120.dtsi"
/ {
model = "STiH407 B2120";
compatible = "st,stih407-b2120", "st,stih407";
@@ -26,53 +28,4 @@
ttyAS0 = &sbc_serial0;
};
- soc {
- sbc_serial0: serial@9530000 {
- status = "okay";
- };
-
- leds {
- compatible = "gpio-leds";
- red {
- #gpio-cells = <2>;
- label = "Front Panel LED";
- gpios = <&pio4 1 0>;
- linux,default-trigger = "heartbeat";
- };
- green {
- #gpio-cells = <2>;
- gpios = <&pio1 3 0>;
- default-state = "off";
- };
- };
-
- i2c@9842000 {
- status = "okay";
- };
-
- i2c@9843000 {
- status = "okay";
- };
-
- i2c@9844000 {
- status = "okay";
- };
-
- i2c@9845000 {
- status = "okay";
- };
-
- i2c@9540000 {
- status = "okay";
- };
-
- /* SSC11 to HDMI */
- i2c@9541000 {
- status = "okay";
- /* HDMI V1.3a supports Standard mode only */
- clock-frequency = <100000>;
- st,i2c-min-scl-pulse-width-us = <0>;
- st,i2c-min-sda-pulse-width-us = <5>;
- };
- };
};
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
new file mode 100644
index 0000000..3e31d32
--- /dev/null
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -0,0 +1,278 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics Limited.
+ * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "stih407-pinctrl.dtsi"
+#include <dt-bindings/reset-controller/stih407-resets.h>
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+ };
+
+ intc: interrupt-controller@08761000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x08761000 0x1000>, <0x08760100 0x100>;
+ };
+
+ scu@08760000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x08760000 0x1000>;
+ };
+
+ timer@08760200 {
+ interrupt-parent = <&intc>;
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x08760200 0x100>;
+ interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&arm_periph_clk>;
+ };
+
+ l2: cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0x08762000 0x1000>;
+ arm,data-latency = <3 3 3>;
+ arm,tag-latency = <2 2 2>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+ compatible = "simple-bus";
+
+ powerdown: powerdown-controller {
+ compatible = "st,stih407-powerdown";
+ #reset-cells = <1>;
+ };
+
+ softreset: softreset-controller {
+ compatible = "st,stih407-softreset";
+ #reset-cells = <1>;
+ };
+
+ picophyreset: picophyreset-controller {
+ compatible = "st,stih407-picophyreset";
+ #reset-cells = <1>;
+ };
+
+ syscfg_sbc: sbc-syscfg@9620000 {
+ compatible = "st,stih407-sbc-syscfg", "syscon";
+ reg = <0x9620000 0x1000>;
+ };
+
+ syscfg_front: front-syscfg@9280000 {
+ compatible = "st,stih407-front-syscfg", "syscon";
+ reg = <0x9280000 0x1000>;
+ };
+
+ syscfg_rear: rear-syscfg@9290000 {
+ compatible = "st,stih407-rear-syscfg", "syscon";
+ reg = <0x9290000 0x1000>;
+ };
+
+ syscfg_flash: flash-syscfg@92a0000 {
+ compatible = "st,stih407-flash-syscfg", "syscon";
+ reg = <0x92a0000 0x1000>;
+ };
+
+ syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
+ compatible = "st,stih407-sbc-reg-syscfg", "syscon";
+ reg = <0x9600000 0x1000>;
+ };
+
+ syscfg_core: core-syscfg@92b0000 {
+ compatible = "st,stih407-core-syscfg", "syscon";
+ reg = <0x92b0000 0x1000>;
+ };
+
+ syscfg_lpm: lpm-syscfg@94b5100 {
+ compatible = "st,stih407-lpm-syscfg", "syscon";
+ reg = <0x94b5100 0x1000>;
+ };
+
+ serial@9830000 {
+ compatible = "st,asc";
+ reg = <0x9830000 0x2c>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_serial0>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+
+ status = "disabled";
+ };
+
+ serial@9831000 {
+ compatible = "st,asc";
+ reg = <0x9831000 0x2c>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_serial1>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+
+ status = "disabled";
+ };
+
+ serial@9832000 {
+ compatible = "st,asc";
+ reg = <0x9832000 0x2c>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_serial2>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+
+ status = "disabled";
+ };
+
+ /* SBC_ASC0 - UART10 */
+ sbc_serial0: serial@9530000 {
+ compatible = "st,asc";
+ reg = <0x9530000 0x2c>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sbc_serial0>;
+ clocks = <&clk_sysin>;
+
+ status = "disabled";
+ };
+
+ serial@9531000 {
+ compatible = "st,asc";
+ reg = <0x9531000 0x2c>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sbc_serial1>;
+ clocks = <&clk_sysin>;
+
+ status = "disabled";
+ };
+
+ i2c@9840000 {
+ compatible = "st,comms-ssc4-i2c";
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x9840000 0x110>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+
+ status = "disabled";
+ };
+
+ i2c@9841000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9841000 0x110>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+
+ status = "disabled";
+ };
+
+ i2c@9842000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9842000 0x110>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2_default>;
+
+ status = "disabled";
+ };
+
+ i2c@9843000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9843000 0x110>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3_default>;
+
+ status = "disabled";
+ };
+
+ i2c@9844000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9844000 0x110>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4_default>;
+
+ status = "disabled";
+ };
+
+ i2c@9845000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9845000 0x110>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c5_default>;
+
+ status = "disabled";
+ };
+
+
+ /* SSCs on SBC */
+ i2c@9540000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9540000 0x110>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_sysin>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c10_default>;
+
+ status = "disabled";
+ };
+
+ i2c@9541000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9541000 0x110>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_sysin>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c11_default>;
+
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
deleted file mode 100644
index 50637f5..0000000
--- a/arch/arm/boot/dts/stih407.dtsi
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * Copyright (C) 2014 STMicroelectronics Limited.
- * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
- */
-#include "stih407-clock.dtsi"
-#include "stih407-pinctrl.dtsi"
-#include <dt-bindings/reset-controller/stih407-resets.h>
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- };
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- };
- };
-
- intc: interrupt-controller@08761000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x08761000 0x1000>, <0x08760100 0x100>;
- };
-
- scu@08760000 {
- compatible = "arm,cortex-a9-scu";
- reg = <0x08760000 0x1000>;
- };
-
- timer@08760200 {
- interrupt-parent = <&intc>;
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x08760200 0x100>;
- interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&arm_periph_clk>;
- };
-
- l2: cache-controller {
- compatible = "arm,pl310-cache";
- reg = <0x08762000 0x1000>;
- arm,data-latency = <3 3 3>;
- arm,tag-latency = <2 2 2>;
- cache-unified;
- cache-level = <2>;
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
- ranges;
- compatible = "simple-bus";
-
- powerdown: powerdown-controller {
- compatible = "st,stih407-powerdown";
- #reset-cells = <1>;
- };
-
- softreset: softreset-controller {
- compatible = "st,stih407-softreset";
- #reset-cells = <1>;
- };
-
- picophyreset: picophyreset-controller {
- compatible = "st,stih407-picophyreset";
- #reset-cells = <1>;
- };
-
- syscfg_sbc: sbc-syscfg@9620000 {
- compatible = "st,stih407-sbc-syscfg", "syscon";
- reg = <0x9620000 0x1000>;
- };
-
- syscfg_front: front-syscfg@9280000 {
- compatible = "st,stih407-front-syscfg", "syscon";
- reg = <0x9280000 0x1000>;
- };
-
- syscfg_rear: rear-syscfg@9290000 {
- compatible = "st,stih407-rear-syscfg", "syscon";
- reg = <0x9290000 0x1000>;
- };
-
- syscfg_flash: flash-syscfg@92a0000 {
- compatible = "st,stih407-flash-syscfg", "syscon";
- reg = <0x92a0000 0x1000>;
- };
-
- syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
- compatible = "st,stih407-sbc-reg-syscfg", "syscon";
- reg = <0x9600000 0x1000>;
- };
-
- syscfg_core: core-syscfg@92b0000 {
- compatible = "st,stih407-core-syscfg", "syscon";
- reg = <0x92b0000 0x1000>;
- };
-
- syscfg_lpm: lpm-syscfg@94b5100 {
- compatible = "st,stih407-lpm-syscfg", "syscon";
- reg = <0x94b5100 0x1000>;
- };
-
- serial@9830000 {
- compatible = "st,asc";
- reg = <0x9830000 0x2c>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_serial0>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
-
- status = "disabled";
- };
-
- serial@9831000 {
- compatible = "st,asc";
- reg = <0x9831000 0x2c>;
- interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_serial1>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
-
- status = "disabled";
- };
-
- serial@9832000 {
- compatible = "st,asc";
- reg = <0x9832000 0x2c>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_serial2>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
-
- status = "disabled";
- };
-
- /* SBC_ASC0 - UART10 */
- sbc_serial0: serial@9530000 {
- compatible = "st,asc";
- reg = <0x9530000 0x2c>;
- interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sbc_serial0>;
- clocks = <&clk_sysin>;
-
- status = "disabled";
- };
-
- serial@9531000 {
- compatible = "st,asc";
- reg = <0x9531000 0x2c>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sbc_serial1>;
- clocks = <&clk_sysin>;
-
- status = "disabled";
- };
-
- i2c@9840000 {
- compatible = "st,comms-ssc4-i2c";
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x9840000 0x110>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0_default>;
-
- status = "disabled";
- };
-
- i2c@9841000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9841000 0x110>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1_default>;
-
- status = "disabled";
- };
-
- i2c@9842000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9842000 0x110>;
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2_default>;
-
- status = "disabled";
- };
-
- i2c@9843000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9843000 0x110>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3_default>;
-
- status = "disabled";
- };
-
- i2c@9844000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9844000 0x110>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4_default>;
-
- status = "disabled";
- };
-
- i2c@9845000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9845000 0x110>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c5_default>;
-
- status = "disabled";
- };
-
-
- /* SSCs on SBC */
- i2c@9540000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9540000 0x110>;
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_sysin>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c10_default>;
-
- status = "disabled";
- };
-
- i2c@9541000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9541000 0x110>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_sysin>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c11_default>;
-
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
new file mode 100644
index 0000000..0074bd4
--- /dev/null
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics (R&D) Limited.
+ * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/ {
+ soc {
+ sbc_serial0: serial@9530000 {
+ status = "okay";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ red {
+ #gpio-cells = <2>;
+ label = "Front Panel LED";
+ gpios = <&pio4 1 0>;
+ linux,default-trigger = "heartbeat";
+ };
+ green {
+ #gpio-cells = <2>;
+ gpios = <&pio1 3 0>;
+ default-state = "off";
+ };
+ };
+
+ i2c@9842000 {
+ status = "okay";
+ };
+
+ i2c@9843000 {
+ status = "okay";
+ };
+
+ i2c@9844000 {
+ status = "okay";
+ };
+
+ i2c@9845000 {
+ status = "okay";
+ };
+
+ i2c@9540000 {
+ status = "okay";
+ };
+
+ /* SSC11 to HDMI */
+ i2c@9541000 {
+ status = "okay";
+ /* HDMI V1.3a supports Standard mode only */
+ clock-frequency = <100000>;
+ st,i2c-min-scl-pulse-width-us = <0>;
+ st,i2c-min-sda-pulse-width-us = <5>;
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 09/11] ARM: STi: DT: STiH410: Add STiH410 SoC and b2120 board support.
2014-11-17 16:47 [PATCH v3 00/11] Add stih410 SoC/board and USB2/1.1 support for stih416 Peter Griffin
` (5 preceding siblings ...)
2014-11-17 16:48 ` [PATCH v3 08/11] ARM: STi: DT: STih407: Abstract common dt nodes into shared files Peter Griffin
@ 2014-11-17 16:48 ` Peter Griffin
2014-11-17 16:48 ` [PATCH v3 10/11] ARM: STi: DT: STih407: STih410: Add clk_ignore_unused to kernel bootargs Peter Griffin
7 siblings, 0 replies; 14+ messages in thread
From: Peter Griffin @ 2014-11-17 16:48 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, maxime.coquelin,
srinivas.kandagatla, patrice.chotard, arnd
Cc: peter.griffin, lee.jones, devicetree
The STiH410 is an advanced multi-HD AVC processor with 3D graphics acceleration
and 1.5-GHz ARM Cortex-A9 SMP CPU part of the stih407 family.
It has wide connectivity including USB 3.0, PCI-e, SATA and gigabit ethernet.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/stih410-b2120.dts | 29 +++
arch/arm/boot/dts/stih410-clock.dtsi | 338 +++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stih410.dtsi | 14 ++
4 files changed, 382 insertions(+)
create mode 100644 arch/arm/boot/dts/stih410-b2120.dts
create mode 100644 arch/arm/boot/dts/stih410-clock.dtsi
create mode 100644 arch/arm/boot/dts/stih410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 38c89ca..04cf4a4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -409,6 +409,7 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
spear320-hmi.dtb
dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \
+ stih410-b2120.dtb \
stih415-b2000.dtb \
stih415-b2020.dtb \
stih416-b2000.dtb \
diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts
new file mode 100644
index 0000000..972c17a
--- /dev/null
+++ b/arch/arm/boot/dts/stih410-b2120.dts
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics (R&D) Limited.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stih410.dtsi"
+#include "stihxxx-b2120.dtsi"
+/ {
+ model = "STiH410 B2120";
+ compatible = "st,stih410-b2120", "st,stih410";
+
+ chosen {
+ bootargs = "console=ttyAS0,115200";
+ linux,stdout-path = &sbc_serial0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x40000000 0x80000000>;
+ };
+
+ aliases {
+ ttyAS0 = &sbc_serial0;
+ };
+};
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
new file mode 100644
index 0000000..6b5803a
--- /dev/null
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -0,0 +1,338 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics R&D Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <dt-bindings/clock/stih410-clks.h>
+/ {
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ compatible = "st,stih410-clk", "simple-bus";
+
+ /*
+ * Fixed 30MHz oscillator inputs to SoC
+ */
+ clk_sysin: clk-sysin {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <30000000>;
+ clock-output-names = "CLK_SYSIN";
+ };
+
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: clk-m-a9-periphs {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_m_a9>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ /*
+ * A9 PLL.
+ */
+ clockgen-a9@92b0000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x92b0000 0xffff>;
+
+ clockgen_a9_pll: clockgen-a9-pll {
+ #clock-cells = <1>;
+ compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clockgen-a9-pll-odf";
+ };
+ };
+
+ /*
+ * ARM CPU related clocks.
+ */
+ clk_m_a9: clk-m-a9@92b0000 {
+ #clock-cells = <0>;
+ compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
+ reg = <0x92b0000 0x10000>;
+
+ clocks = <&clockgen_a9_pll 0>,
+ <&clockgen_a9_pll 0>,
+ <&clk_s_c0_flexgen 13>,
+ <&clk_m_a9_ext2f_div2>;
+ };
+
+ /*
+ * ARM Peripheral clock for timers
+ */
+ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+
+ clocks = <&clk_s_c0_flexgen 13>;
+
+ clock-output-names = "clk-m-a9-ext2f-div2";
+
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ /*
+ * Bootloader initialized system infrastructure clock for
+ * serial devices.
+ */
+ clk_ext2f_a9: clockgen-c0@13 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ clock-output-names = "clk-s-icn-reg-0";
+ };
+
+ clockgen-a@090ff000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x90ff000 0x1000>;
+
+ clk_s_a0_pll: clk-s-a0-pll {
+ #clock-cells = <1>;
+ compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-a0-pll-ofd-0";
+ };
+
+ clk_s_a0_flexgen: clk-s-a0-flexgen {
+ compatible = "st,flexgen";
+
+ #clock-cells = <1>;
+
+ clocks = <&clk_s_a0_pll 0>,
+ <&clk_sysin>;
+
+ clock-output-names = "clk-ic-lmi0",
+ "clk-ic-lmi1";
+ };
+ };
+
+ clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
+ #clock-cells = <1>;
+ compatible = "st,stih407-quadfs660-C", "st,quadfs";
+ reg = <0x9103000 0x1000>;
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-c0-fs0-ch0",
+ "clk-s-c0-fs0-ch1",
+ "clk-s-c0-fs0-ch2",
+ "clk-s-c0-fs0-ch3";
+ };
+
+ clk_s_c0: clockgen-c@09103000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x9103000 0x1000>;
+
+ clk_s_c0_pll0: clk-s-c0-pll0 {
+ #clock-cells = <1>;
+ compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-c0-pll0-odf-0";
+ };
+
+ clk_s_c0_pll1: clk-s-c0-pll1 {
+ #clock-cells = <1>;
+ compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-c0-pll1-odf-0";
+ };
+
+ clk_s_c0_flexgen: clk-s-c0-flexgen {
+ #clock-cells = <1>;
+ compatible = "st,flexgen";
+
+ clocks = <&clk_s_c0_pll0 0>,
+ <&clk_s_c0_pll1 0>,
+ <&clk_s_c0_quadfs 0>,
+ <&clk_s_c0_quadfs 1>,
+ <&clk_s_c0_quadfs 2>,
+ <&clk_s_c0_quadfs 3>,
+ <&clk_sysin>;
+
+ clock-output-names = "clk-icn-gpu",
+ "clk-fdma",
+ "clk-nand",
+ "clk-hva",
+ "clk-proc-stfe",
+ "clk-proc-tp",
+ "clk-rx-icn-dmu",
+ "clk-rx-icn-hva",
+ "clk-icn-cpu",
+ "clk-tx-icn-dmu",
+ "clk-mmc-0",
+ "clk-mmc-1",
+ "clk-jpegdec",
+ "clk-ext2fa9",
+ "clk-ic-bdisp-0",
+ "clk-ic-bdisp-1",
+ "clk-pp-dmu",
+ "clk-vid-dmu",
+ "clk-dss-lpc",
+ "clk-st231-aud-0",
+ "clk-st231-gp-1",
+ "clk-st231-dmu",
+ "clk-icn-lmi",
+ "clk-tx-icn-disp-1",
+ "clk-icn-sbc",
+ "clk-stfe-frc2",
+ "clk-eth-phy",
+ "clk-eth-ref-phyclk",
+ "clk-flash-promip",
+ "clk-main-disp",
+ "clk-aux-disp",
+ "clk-compo-dvp",
+ "clk-tx-icn-hades",
+ "clk-rx-icn-hades",
+ "clk-icn-reg-16",
+ "clk-pp-hades",
+ "clk-clust-hades",
+ "clk-hwpe-hades",
+ "clk-fc-hades";
+ };
+ };
+
+ clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
+ #clock-cells = <1>;
+ compatible = "st,stih407-quadfs660-D", "st,quadfs";
+ reg = <0x9104000 0x1000>;
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-d0-fs0-ch0",
+ "clk-s-d0-fs0-ch1",
+ "clk-s-d0-fs0-ch2",
+ "clk-s-d0-fs0-ch3";
+ };
+
+ clockgen-d0@09104000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x9104000 0x1000>;
+
+ clk_s_d0_flexgen: clk-s-d0-flexgen {
+ #clock-cells = <1>;
+ compatible = "st,flexgen";
+
+ clocks = <&clk_s_d0_quadfs 0>,
+ <&clk_s_d0_quadfs 1>,
+ <&clk_s_d0_quadfs 2>,
+ <&clk_s_d0_quadfs 3>,
+ <&clk_sysin>;
+
+ clock-output-names = "clk-pcm-0",
+ "clk-pcm-1",
+ "clk-pcm-2",
+ "clk-spdiff",
+ "clk-pcmr10-master",
+ "clk-usb2-phy";
+ };
+ };
+
+ clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
+ #clock-cells = <1>;
+ compatible = "st,stih407-quadfs660-D", "st,quadfs";
+ reg = <0x9106000 0x1000>;
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-d2-fs0-ch0",
+ "clk-s-d2-fs0-ch1",
+ "clk-s-d2-fs0-ch2",
+ "clk-s-d2-fs0-ch3";
+ };
+
+ clk_tmdsout_hdmi: clk-tmdsout-hdmi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clockgen-d2@x9106000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x9106000 0x1000>;
+
+ clk_s_d2_flexgen: clk-s-d2-flexgen {
+ #clock-cells = <1>;
+ compatible = "st,flexgen";
+
+ clocks = <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>,
+ <&clk_s_d2_quadfs 2>,
+ <&clk_s_d2_quadfs 3>,
+ <&clk_sysin>,
+ <&clk_sysin>,
+ <&clk_tmdsout_hdmi>;
+
+ clock-output-names = "clk-pix-main-disp",
+ "clk-pix-pip",
+ "clk-pix-gdp1",
+ "clk-pix-gdp2",
+ "clk-pix-gdp3",
+ "clk-pix-gdp4",
+ "clk-pix-aux-disp",
+ "clk-denc",
+ "clk-pix-hddac",
+ "clk-hddac",
+ "clk-sddac",
+ "clk-pix-dvo",
+ "clk-dvo",
+ "clk-pix-hdmi",
+ "clk-tmds-hdmi",
+ "clk-ref-hdmiphy";
+ };
+ };
+
+ clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
+ #clock-cells = <1>;
+ compatible = "st,stih407-quadfs660-D", "st,quadfs";
+ reg = <0x9107000 0x1000>;
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-d3-fs0-ch0",
+ "clk-s-d3-fs0-ch1",
+ "clk-s-d3-fs0-ch2",
+ "clk-s-d3-fs0-ch3";
+ };
+
+ clockgen-d3@9107000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x9107000 0x1000>;
+
+ clk_s_d3_flexgen: clk-s-d3-flexgen {
+ #clock-cells = <1>;
+ compatible = "st,flexgen";
+
+ clocks = <&clk_s_d3_quadfs 0>,
+ <&clk_s_d3_quadfs 1>,
+ <&clk_s_d3_quadfs 2>,
+ <&clk_s_d3_quadfs 3>,
+ <&clk_sysin>;
+
+ clock-output-names = "clk-stfe-frc1",
+ "clk-tsout-0",
+ "clk-tsout-1",
+ "clk-mchi",
+ "clk-vsens-compo",
+ "clk-frc1-remote",
+ "clk-lpc-0",
+ "clk-lpc-1";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
new file mode 100644
index 0000000..c05627e
--- /dev/null
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics Limited.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "stih410-clock.dtsi"
+#include "stih407-family.dtsi"
+#include "stih410-pinctrl.dtsi"
+/ {
+
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 10/11] ARM: STi: DT: STih407: STih410: Add clk_ignore_unused to kernel bootargs
2014-11-17 16:47 [PATCH v3 00/11] Add stih410 SoC/board and USB2/1.1 support for stih416 Peter Griffin
` (6 preceding siblings ...)
2014-11-17 16:48 ` [PATCH v3 09/11] ARM: STi: DT: STiH410: Add STiH410 SoC and b2120 board support Peter Griffin
@ 2014-11-17 16:48 ` Peter Griffin
7 siblings, 0 replies; 14+ messages in thread
From: Peter Griffin @ 2014-11-17 16:48 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, maxime.coquelin,
srinivas.kandagatla, patrice.chotard, arnd
Cc: peter.griffin, lee.jones, devicetree
At the moment we don't take a reference on some core interconnect
clocks which means when CCF turns off unused clocks the SoC will
hang. As a temp soltuion we will boot with clk_ignore_unused
parameter for all b2120 boards.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
---
arch/arm/boot/dts/stih407-b2120.dts | 2 +-
arch/arm/boot/dts/stih410-b2120.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts
index a3ad52b..261d5e2 100644
--- a/arch/arm/boot/dts/stih407-b2120.dts
+++ b/arch/arm/boot/dts/stih407-b2120.dts
@@ -15,7 +15,7 @@
compatible = "st,stih407-b2120", "st,stih407";
chosen {
- bootargs = "console=ttyAS0,115200";
+ bootargs = "console=ttyAS0,115200 clk_ignore_unused";
linux,stdout-path = &sbc_serial0;
};
diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts
index 972c17a..2f61a99 100644
--- a/arch/arm/boot/dts/stih410-b2120.dts
+++ b/arch/arm/boot/dts/stih410-b2120.dts
@@ -14,7 +14,7 @@
compatible = "st,stih410-b2120", "st,stih410";
chosen {
- bootargs = "console=ttyAS0,115200";
+ bootargs = "console=ttyAS0,115200 clk_ignore_unused";
linux,stdout-path = &sbc_serial0;
};
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread