[PATCH/RFC 0/4] ARM: shmobile: Correct masks for GIC PPI interrupts

[PATCH/RFC 0/4] ARM: shmobile: Correct masks for GIC PPI interrupts

[Geert Uytterhoeven]

	Hi all,

This patch series corrects the masks in the second interrupt cells for
Private Peripheral Interrupts in dtsi files for the shmobile family of
SoCs.

It's my understanding this mask should reflect the actual number of CPU
cores the interrupt is wired too.
Is that correct?

  - Hence it should be "GIC_CPU_MASK_SIMPLE(2)" on dual-core CPUs, like
    r8a7791 and r8a7794 (the first two patches),
  - Should it be "GIC_CPU_MASK_SIMPLE(8)" on big.LITTLE configurations
    with four Cortex-A15 cores and four Cortex-A7 cores?
    Or should the interrupts be delivered to the four Cortex-A15 cores
    only by default?
    The last two RFC-patches implement the former for r8a7790 and
    r8a73a4.

Note that incorrect masks for GIC PPI interrupts are not limited to
shmobile. Presumably the interrupt specifiers got copied around a lot,
cfr. the proliferation of "GIC_CPU_MASK_SIMPLE(4)" (and the older
hardcoded "0xf0x" variant) in various dtsi files, not always limited to
quad-core CPUs.

This was tested on r8a7791/koelsch, which uses the arch timer interrupt.

Thanks for your feedback!

Geert Uytterhoeven (4):
  ARM: shmobile: r8a7791: Correct mask for GIC PPI interrupts
  ARM: shmobile: r8a7794: Correct mask for GIC PPI interrupts
  [RFC] ARM: shmobile: r8a7790: Correct mask for GIC PPI interrupts
  [RFC] ARM: shmobile: r8a73a4: Correct mask for GIC PPI interrupts

 arch/arm/boot/dts/r8a73a4.dtsi | 10 +++++-----
 arch/arm/boot/dts/r8a7790.dtsi | 10 +++++-----
 arch/arm/boot/dts/r8a7791.dtsi | 10 +++++-----
 arch/arm/boot/dts/r8a7794.dtsi | 10 +++++-----
 4 files changed, 20 insertions(+), 20 deletions(-)

-- 
1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH 1/4] ARM: shmobile: r8a7791: Correct mask for GIC PPI interrupts

[Geert Uytterhoeven]

R-Car M2-W (r8a7791) contains two Cortex-A15 cores, hence the second
interrupt specifier cell for Private Peripheral Interrupts should use
"GIC_CPU_MASK_SIMPLE(2)".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Tested on koelsch
---
 arch/arm/boot/dts/r8a7791.dtsi | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 77c0beeb8d7c984c..6293d3aaf23822bc 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -78,7 +78,7 @@
 			<0 0xf1002000 0 0x1000>,
 			<0 0xf1004000 0 0x2000>,
 			<0 0xf1006000 0 0x2000>;
-		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
 	gpio0: gpio@e6050000 {
@@ -186,10 +186,10 @@
 
 	timer {
 		compatible = "arm,armv7-timer";
-		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
 	cmt0: timer@ffca0000 {
-- 
1.9.1

[PATCH 2/4] ARM: shmobile: r8a7794: Correct mask for GIC PPI interrupts

[Geert Uytterhoeven]

R-Car E2 (r8a7794) contains two Cortex-A7 cores, hence the second
interrupt specifier cell for Private Peripheral Interrupts should use
"GIC_CPU_MASK_SIMPLE(2)".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Untested
---
 arch/arm/boot/dts/r8a7794.dtsi | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 19c9de3f2a5ade33..0a6caa99e3afb07e 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -47,7 +47,7 @@
 			<0 0xf1002000 0 0x1000>,
 			<0 0xf1004000 0 0x2000>,
 			<0 0xf1006000 0 0x2000>;
-		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
 	cmt0: timer@ffca0000 {
@@ -84,10 +84,10 @@
 
 	timer {
 		compatible = "arm,armv7-timer";
-		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
 	irqc0: interrupt-controller@e61c0000 {
-- 
1.9.1

[PATCH/RFC 3/4] ARM: shmobile: r8a7790: Correct mask for GIC PPI interrupts

[Geert Uytterhoeven]

R-Car H2 (r8a7790) contains four Cortex-A15 and four Cortex-A7 cores,
hence the second interrupt specifier cell for Private Peripheral
Interrupts should use "GIC_CPU_MASK_SIMPLE(8)".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Untested.
Is this correct? Or should the interrupts be delivered to the four
Cortex-A15 cores only by default?
---
 arch/arm/boot/dts/r8a7790.dtsi | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index af7e255f629e3273..8774181c4169b035 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -120,7 +120,7 @@
 			<0 0xf1002000 0 0x1000>,
 			<0 0xf1004000 0 0x2000>,
 			<0 0xf1006000 0 0x2000>;
-		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
 	gpio0: gpio@e6050000 {
@@ -204,10 +204,10 @@
 
 	timer {
 		compatible = "arm,armv7-timer";
-		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <1 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <1 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <1 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
 	cmt0: timer@ffca0000 {
-- 
1.9.1

[PATCH/RFC 4/4] ARM: shmobile: r8a73a4: Correct mask for GIC PPI interrupts

[Geert Uytterhoeven]

R-Mobile APE6 (r8a73a4) contains four Cortex-A15 and four Cortex-A7
cores, hence the second interrupt specifier cell for Private Peripheral
Interrupts should use "GIC_CPU_MASK_SIMPLE(8)".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Untested.
Is this correct? Or should the interrupts be delivered to the four
Cortex-A15 cores only by default?
---
 arch/arm/boot/dts/r8a73a4.dtsi | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 5ac57babc3b95c99..6291a57fe8bf440f 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -32,10 +32,10 @@
 
 	timer {
 		compatible = "arm,armv7-timer";
-		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <1 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <1 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <1 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
 	dmac: dma-multiplexer {
@@ -365,6 +365,6 @@
 			<0 0xf1002000 0 0x1000>,
 			<0 0xf1004000 0 0x2000>,
 			<0 0xf1006000 0 0x2000>;
-		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 };
-- 
1.9.1

Re: [PATCH/RFC 0/4] ARM: shmobile: Correct masks for GIC PPI interrupts

[Simon Horman]

On Thu, Nov 27, 2014 at 11:57:15AM +0100, Geert Uytterhoeven wrote:
> 	Hi all,
> 
> This patch series corrects the masks in the second interrupt cells for
> Private Peripheral Interrupts in dtsi files for the shmobile family of
> SoCs.
> 
> It's my understanding this mask should reflect the actual number of CPU
> cores the interrupt is wired too.
> Is that correct?
> 
>   - Hence it should be "GIC_CPU_MASK_SIMPLE(2)" on dual-core CPUs, like
>     r8a7791 and r8a7794 (the first two patches),
>   - Should it be "GIC_CPU_MASK_SIMPLE(8)" on big.LITTLE configurations
>     with four Cortex-A15 cores and four Cortex-A7 cores?
>     Or should the interrupts be delivered to the four Cortex-A15 cores
>     only by default?
>     The last two RFC-patches implement the former for r8a7790 and
>     r8a73a4.
> 
> Note that incorrect masks for GIC PPI interrupts are not limited to
> shmobile. Presumably the interrupt specifiers got copied around a lot,
> cfr. the proliferation of "GIC_CPU_MASK_SIMPLE(4)" (and the older
> hardcoded "0xf0x" variant) in various dtsi files, not always limited to
> quad-core CPUs.
> 
> This was tested on r8a7791/koelsch, which uses the arch timer interrupt.
> 
> Thanks for your feedback!
> 
> Geert Uytterhoeven (4):
>   ARM: shmobile: r8a7791: Correct mask for GIC PPI interrupts
>   ARM: shmobile: r8a7794: Correct mask for GIC PPI interrupts

Hi Geert,

the above two patches seem like they could be queued up.
Shall I do so?

>   [RFC] ARM: shmobile: r8a7790: Correct mask for GIC PPI interrupts
>   [RFC] ARM: shmobile: r8a73a4: Correct mask for GIC PPI interrupts
> 
>  arch/arm/boot/dts/r8a73a4.dtsi | 10 +++++-----
>  arch/arm/boot/dts/r8a7790.dtsi | 10 +++++-----
>  arch/arm/boot/dts/r8a7791.dtsi | 10 +++++-----
>  arch/arm/boot/dts/r8a7794.dtsi | 10 +++++-----
>  4 files changed, 20 insertions(+), 20 deletions(-)
> 
> -- 
> 1.9.1
> 
> Gr{oetje,eeting}s,
> 
> 						Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> 							    -- Linus Torvalds
> 

Re: [PATCH/RFC 0/4] ARM: shmobile: Correct masks for GIC PPI interrupts

[Geert Uytterhoeven]

Hi Simon,

On Mon, Dec 8, 2014 at 1:13 AM, Simon Horman <horms@verge.net.au> wrote:
> On Thu, Nov 27, 2014 at 11:57:15AM +0100, Geert Uytterhoeven wrote:
>> This patch series corrects the masks in the second interrupt cells for
>> Private Peripheral Interrupts in dtsi files for the shmobile family of
>> SoCs.
>>
>> It's my understanding this mask should reflect the actual number of CPU
>> cores the interrupt is wired too.
>> Is that correct?
>>
>>   - Hence it should be "GIC_CPU_MASK_SIMPLE(2)" on dual-core CPUs, like
>>     r8a7791 and r8a7794 (the first two patches),
>>   - Should it be "GIC_CPU_MASK_SIMPLE(8)" on big.LITTLE configurations
>>     with four Cortex-A15 cores and four Cortex-A7 cores?
>>     Or should the interrupts be delivered to the four Cortex-A15 cores
>>     only by default?
>>     The last two RFC-patches implement the former for r8a7790 and
>>     r8a73a4.
>>
>> Note that incorrect masks for GIC PPI interrupts are not limited to
>> shmobile. Presumably the interrupt specifiers got copied around a lot,
>> cfr. the proliferation of "GIC_CPU_MASK_SIMPLE(4)" (and the older
>> hardcoded "0xf0x" variant) in various dtsi files, not always limited to
>> quad-core CPUs.
>>
>> This was tested on r8a7791/koelsch, which uses the arch timer interrupt.
>>
>> Thanks for your feedback!
>>
>> Geert Uytterhoeven (4):
>>   ARM: shmobile: r8a7791: Correct mask for GIC PPI interrupts
>>   ARM: shmobile: r8a7794: Correct mask for GIC PPI interrupts
>
> Hi Geert,
>
> the above two patches seem like they could be queued up.
> Shall I do so?

I think it's safe. Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH/RFC 0/4] ARM: shmobile: Correct masks for GIC PPI interrupts

[Simon Horman]

On Mon, Dec 08, 2014 at 09:04:16AM +0100, Geert Uytterhoeven wrote:
> Hi Simon,
> 
> On Mon, Dec 8, 2014 at 1:13 AM, Simon Horman <horms@verge.net.au> wrote:
> > On Thu, Nov 27, 2014 at 11:57:15AM +0100, Geert Uytterhoeven wrote:
> >> This patch series corrects the masks in the second interrupt cells for
> >> Private Peripheral Interrupts in dtsi files for the shmobile family of
> >> SoCs.
> >>
> >> It's my understanding this mask should reflect the actual number of CPU
> >> cores the interrupt is wired too.
> >> Is that correct?
> >>
> >>   - Hence it should be "GIC_CPU_MASK_SIMPLE(2)" on dual-core CPUs, like
> >>     r8a7791 and r8a7794 (the first two patches),
> >>   - Should it be "GIC_CPU_MASK_SIMPLE(8)" on big.LITTLE configurations
> >>     with four Cortex-A15 cores and four Cortex-A7 cores?
> >>     Or should the interrupts be delivered to the four Cortex-A15 cores
> >>     only by default?
> >>     The last two RFC-patches implement the former for r8a7790 and
> >>     r8a73a4.
> >>
> >> Note that incorrect masks for GIC PPI interrupts are not limited to
> >> shmobile. Presumably the interrupt specifiers got copied around a lot,
> >> cfr. the proliferation of "GIC_CPU_MASK_SIMPLE(4)" (and the older
> >> hardcoded "0xf0x" variant) in various dtsi files, not always limited to
> >> quad-core CPUs.
> >>
> >> This was tested on r8a7791/koelsch, which uses the arch timer interrupt.
> >>
> >> Thanks for your feedback!
> >>
> >> Geert Uytterhoeven (4):
> >>   ARM: shmobile: r8a7791: Correct mask for GIC PPI interrupts
> >>   ARM: shmobile: r8a7794: Correct mask for GIC PPI interrupts
> >
> > Hi Geert,
> >
> > the above two patches seem like they could be queued up.
> > Shall I do so?
> 
> I think it's safe. Thanks!

Thanks, I have done so.