From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ray Jui Subject: [PATCH v2 1/4] pci: iProc: define Broadcom iProc PCIe binding Date: Thu, 11 Dec 2014 18:36:54 -0800 Message-ID: <1418351817-14898-2-git-send-email-rjui@broadcom.com> References: <1418351817-14898-1-git-send-email-rjui@broadcom.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1418351817-14898-1-git-send-email-rjui@broadcom.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Bjorn Helgaas , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Grant Likely , Christian Daudt , Matt Porter , Florian Fainelli , Russell King , Hauke Mehrtens Cc: devicetree@vger.kernel.org, Scott Branden , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, Ray Jui , linux-arm-kernel@lists.infradead.org, Lucas Stach List-Id: devicetree@vger.kernel.org Document the PCIe device tree binding for Broadcom iProc family of SoCs Signed-off-by: Ray Jui Reviewed-by: Scott Branden --- .../devicetree/bindings/pci/brcm,iproc-pcie.txt | 74 ++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt new file mode 100644 index 0000000..040bc0f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt @@ -0,0 +1,74 @@ +* Broadcom iProc PCIe controller + +Required properties: +- compatible: Must be "brcm,iproc-pcie" +- reg: base address and length of the PCIe controller and the MDIO interface + that controls the PCIe PHY +- #interrupt-cells: set to <1> +- interrupts: interrupt IDs +- interrupt-map-mask and interrupt-map, standard PCI properties to define the + mapping of the PCIe interface to interrupt numbers +- bus-range: PCI bus numbers covered +- #address-cells: set to <3> +- #size-cells: set to <2> +- device_type: set to "pci" +- ranges: ranges for the PCI memory and I/O regions +- phy-addr: MDC/MDIO adddress of the PCIe PHY +- have-msi-inten-reg: Required for legacy iProc PCIe controllers that need the + MSI interrupt enable register to be set explicitly + +The Broadcom iProc PCie driver adapts the multi-domain structure, i.e., each +interface has its own domain and therefore has its own device node +Example: + +SoC specific DT Entry: + + pcie0: pcie@18012000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18012000 0x1000>, + <0x18002000 0x1000>; + + #interrupt-cells = <1>; + interrupts = , + , + , + , + , + ; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; + + bus-range = <0x00 0xFF>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x28000000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; /* non-prefetchable memory */ + phy-addr = <5>; + }; + + pcie1: pcie@18013000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18013000 0x1000>, + <0x18002000 0x1000>; + + #interrupt-cells = <1>; + interrupts = , + , + , + , + , + ; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; + + bus-range = <0x00 0xFF>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x48000000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; /* non-prefetchable memory */ + phy-addr = <6>; + }; -- 1.7.9.5