[PATCH 0/4] pinctrl: qcom: Add multiple copy support

[PATCH 0/4] pinctrl: qcom: Add multiple copy support

[Andy Gross]

These patches add multiple copy support for functions which require additional
mux configurations on specific Qualcomm processor pincontrol blocks.  Functions
which may have multiple copies are slimbus, mi2s, pdm, pcie, and GSBI.

Andy Gross (4):
  pinctrl: qcom: Add multiple copy base support
  pinctrl: qcom: ipq8064: Add multi copy support
  pinctrl: qcom: apq8064: Add multi copy support
  pinctrl: qcom: msm8960: Add multi copy support

 .../bindings/pinctrl/qcom,apq8064-pinctrl.txt      |    3 +-
 .../bindings/pinctrl/qcom,ipq8064-pinctrl.txt      |   16 +-
 .../bindings/pinctrl/qcom,msm8960-pinctrl.txt      |   19 +-
 drivers/pinctrl/qcom/pinctrl-apq8064.c             |   29 ++-
 drivers/pinctrl/qcom/pinctrl-ipq8064.c             |  244 ++++++++++++++------
 drivers/pinctrl/qcom/pinctrl-msm.c                 |   10 +
 drivers/pinctrl/qcom/pinctrl-msm.h                 |    4 +
 drivers/pinctrl/qcom/pinctrl-msm8960.c             |   32 ++-
 8 files changed, 257 insertions(+), 100 deletions(-)

-- 
Qualcomm Innovation Center, Inc
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 1/4] pinctrl: qcom: Add multiple copy base support

[Andy Gross]

Qualcomm pinctrl devices support functions that can be routed to multiple pins.
In some cases, there are additional mux registers that must be set for the pins
to work correctly.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-msm.c |   10 ++++++++++
 drivers/pinctrl/qcom/pinctrl-msm.h |    4 ++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index e730935..17e2867 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -141,11 +141,13 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
 {
 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 	const struct msm_pingroup *g;
+	const struct msm_function *f;
 	unsigned long flags;
 	u32 val;
 	int i;
 
 	g = &pctrl->soc->groups[group];
+	f = &pctrl->soc->functions[function];
 
 	for (i = 0; i < g->nfuncs; i++) {
 		if (g->funcs[i] == function)
@@ -162,6 +164,14 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
 	val |= i << g->mux_bit;
 	writel(val, pctrl->regs + g->ctl_reg);
 
+	/*
+	 * if an alternate copy configuration is required, configure the pins to
+	 * steer the function to the correct set of pins.  This is used in cases
+	 * where we have more than one copy of the pins for a function
+	 */
+	if (f->requires_copy_select)
+		writel(f->copy_select_value, pctrl->regs + f->copy_select_reg);
+
 	spin_unlock_irqrestore(&pctrl->lock, flags);
 
 	return 0;
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
index b952c4b..7180587 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -25,6 +25,10 @@ struct msm_function {
 	const char *name;
 	const char * const *groups;
 	unsigned ngroups;
+
+	unsigned requires_copy_select;
+	unsigned copy_select_reg;
+	unsigned copy_select_value;
 };
 
 /**
-- 
Qualcomm Innovation Center, Inc
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 2/4] pinctrl: qcom: ipq8064: Add multi copy support

[Andy Gross]

This patch adds multiple copy support for functions that can be mapped to more
than one pin and that also require an additional mux configuration setting to
work properly.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 .../bindings/pinctrl/qcom,ipq8064-pinctrl.txt      |   16 +-
 drivers/pinctrl/qcom/pinctrl-ipq8064.c             |  244 ++++++++++++++------
 2 files changed, 185 insertions(+), 75 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt
index 6e88e91..593b86b 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt
@@ -51,13 +51,15 @@ Valid values for qcom,pins are:
 
 
 Valid values for function are:
-  mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5,
-  gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1,
-  spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata,
-  pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt,
-  pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie2_pwren,
-  pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3_pwren_n,
-  pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold
+  mdio, mi2s_a, mi2s_b, mi2s, pdm0_a, pdm0_b, pdm1_a, pdm1_b, pdm2_a, pdm2_b,
+  ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5, gsbi5_spi_cs1,
+  gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6_a, gsbi6_b, gsbi7, nss_spi, sdc1, spdif,
+  nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata, pcie1_rst,
+  pcie1_prsnt_a, pcie1_prsnt_b, pcie1_pwren_n_a, pcie1_pwren_n_b, pcie1_pwren_a,
+  pcie1_pwren_b, pcie1_pwrflt_a, pcie1_pwrflt_b, pcie1_clk_req, pcie2_rst,
+  pcie2_prsnt_a, pcie2_prsnt_b, pcie2_pwren_n_a, pcie2_pwren_n_b, pcie2_pwren_a,
+  pcie2_pwren_b, pcie2_pwrflt_a, pcie2_pwrflt_b, pcie2_clk_req, pcie3_rst,
+  pcie3_prsnt, pcie3_pwren_n, pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold
 
 Example:
 
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8064.c b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
index bcb29c0..312968d 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
@@ -177,6 +177,16 @@ static const unsigned int sdc3_data_pins[] = { 71 };
 		.ngroups = ARRAY_SIZE(fname##_groups),	\
 	}
 
+#define FUNCTION_MULTI_COPY(fname, reg, value)		\
+	[IPQ_MUX_##fname] = {				\
+		.name = #fname,				\
+		.groups = fname##_groups,		\
+		.ngroups = ARRAY_SIZE(fname##_groups),	\
+		.requires_copy_select = 1,		\
+		.copy_select_reg = reg,			\
+		.copy_select_value = value,		\
+	}
+
 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
 	{						\
 		.name = "gpio" #id,			\
@@ -247,7 +257,15 @@ static const unsigned int sdc3_data_pins[] = { 71 };
 enum ipq8064_functions {
 	IPQ_MUX_gpio,
 	IPQ_MUX_mdio,
+	IPQ_MUX_mi2s_a,
+	IPQ_MUX_mi2s_b,
 	IPQ_MUX_mi2s,
+	IPQ_MUX_pdm0_a,
+	IPQ_MUX_pdm0_b,
+	IPQ_MUX_pdm1_a,
+	IPQ_MUX_pdm1_b,
+	IPQ_MUX_pdm2_a,
+	IPQ_MUX_pdm2_b,
 	IPQ_MUX_pdm,
 	IPQ_MUX_ssbi,
 	IPQ_MUX_spmi,
@@ -259,7 +277,8 @@ enum ipq8064_functions {
 	IPQ_MUX_gsbi5_spi_cs1,
 	IPQ_MUX_gsbi5_spi_cs2,
 	IPQ_MUX_gsbi5_spi_cs3,
-	IPQ_MUX_gsbi6,
+	IPQ_MUX_gsbi6_a,
+	IPQ_MUX_gsbi6_b,
 	IPQ_MUX_gsbi7,
 	IPQ_MUX_nss_spi,
 	IPQ_MUX_sdc1,
@@ -273,16 +292,24 @@ enum ipq8064_functions {
 	IPQ_MUX_rgmii2,
 	IPQ_MUX_sata,
 	IPQ_MUX_pcie1_rst,
-	IPQ_MUX_pcie1_prsnt,
-	IPQ_MUX_pcie1_pwrflt,
-	IPQ_MUX_pcie1_pwren_n,
-	IPQ_MUX_pcie1_pwren,
+	IPQ_MUX_pcie1_prsnt_a,
+	IPQ_MUX_pcie1_prsnt_b,
+	IPQ_MUX_pcie1_pwrflt_a,
+	IPQ_MUX_pcie1_pwrflt_b,
+	IPQ_MUX_pcie1_pwren_n_a,
+	IPQ_MUX_pcie1_pwren_n_b,
+	IPQ_MUX_pcie1_pwren_a,
+	IPQ_MUX_pcie1_pwren_b,
 	IPQ_MUX_pcie1_clk_req,
 	IPQ_MUX_pcie2_rst,
-	IPQ_MUX_pcie2_prsnt,
-	IPQ_MUX_pcie2_pwrflt,
-	IPQ_MUX_pcie2_pwren_n,
-	IPQ_MUX_pcie2_pwren,
+	IPQ_MUX_pcie2_prsnt_a,
+	IPQ_MUX_pcie2_prsnt_b,
+	IPQ_MUX_pcie2_pwrflt_a,
+	IPQ_MUX_pcie2_pwrflt_b,
+	IPQ_MUX_pcie2_pwren_n_a,
+	IPQ_MUX_pcie2_pwren_n_b,
+	IPQ_MUX_pcie2_pwren_a,
+	IPQ_MUX_pcie2_pwren_b,
 	IPQ_MUX_pcie2_clk_req,
 	IPQ_MUX_pcie3_rst,
 	IPQ_MUX_pcie3_prsnt,
@@ -311,15 +338,44 @@ static const char * const mdio_groups[] = {
 	"gpio0", "gpio1", "gpio10", "gpio11",
 };
 
+static const char * const mi2s_a_groups[] = {
+	"gpio27", "gpio28", "gpio29", "gpio32",
+};
+
+static const char * const mi2s_b_groups[] = {
+	"gpio55", "gpio56", "gpio57", "gpio58",
+};
+
 static const char * const mi2s_groups[] = {
-	"gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
-	"gpio33", "gpio55", "gpio56", "gpio57", "gpio58",
+	"gpio30", "gpio31", "gpio33",
+};
+
+static const char * const pdm0_a_groups[] = {
+	"gpio51", "gpio52",
+};
+
+static const char * const pdm0_b_groups[] = {
+	"gpio2", "gpio59",
+};
+
+static const char * const pdm1_a_groups[] = {
+	"gpio30", "gpio31",
+};
+
+static const char * const pdm1_b_groups[] = {
+	"gpio16", "gpio17",
+};
+
+static const char * const pdm2_a_groups[] = {
+	"gpio55", "gpio56",
+};
+
+static const char * const pdm2_b_groups[] = {
+	"gpio34", "gpio35",
 };
 
 static const char * const pdm_groups[] = {
-	"gpio3", "gpio16", "gpio17", "gpio22", "gpio30", "gpio31",
-	"gpio34", "gpio35", "gpio52", "gpio55", "gpio56", "gpio58",
-	"gpio59",
+	"gpio22",
 };
 
 static const char * const ssbi_groups[] = {
@@ -362,9 +418,12 @@ static const char * const gsbi5_spi_cs3_groups[] = {
 	"gpio2",
 };
 
-static const char * const gsbi6_groups[] = {
-	"gpio27", "gpio28", "gpio29", "gpio30", "gpio55", "gpio56",
-	"gpio57", "gpio58",
+static const char * const gsbi6_a_groups[] = {
+	"gpio27", "gpio28", "gpio29", "gpio30",
+};
+
+static const char *const gsbi6_b_groups[] = {
+	"gpio55", "gpio56", "gpio57", "gpio58",
 };
 
 static const char * const gsbi7_groups[] = {
@@ -424,20 +483,36 @@ static const char * const pcie1_rst_groups[] = {
 	"gpio3",
 };
 
-static const char * const pcie1_prsnt_groups[] = {
-	"gpio3", "gpio11",
+static const char * const pcie1_prsnt_a_groups[] = {
+	"gpio11",
+};
+
+static const char * const pcie1_prsnt_b_groups[] = {
+	"gpio3",
+};
+
+static const char * const pcie1_pwren_n_a_groups[] = {
+	"gpio12",
 };
 
-static const char * const pcie1_pwren_n_groups[] = {
-	"gpio4", "gpio12",
+static const char * const pcie1_pwren_n_b_groups[] = {
+	"gpio4",
 };
 
-static const char * const pcie1_pwren_groups[] = {
-	"gpio4", "gpio12",
+static const char * const pcie1_pwren_a_groups[] = {
+	"gpio12",
 };
 
-static const char * const pcie1_pwrflt_groups[] = {
-	"gpio5", "gpio13",
+static const char * const pcie1_pwren_b_groups[] = {
+	"gpio4",
+};
+
+static const char * const pcie1_pwrflt_a_groups[] = {
+	"gpio13",
+};
+
+static const char * const pcie1_pwrflt_b_groups[] = {
+	"gpio5",
 };
 
 static const char * const pcie1_clk_req_groups[] = {
@@ -448,20 +523,36 @@ static const char * const pcie2_rst_groups[] = {
 	"gpio48",
 };
 
-static const char * const pcie2_prsnt_groups[] = {
-	"gpio11", "gpio48",
+static const char * const pcie2_prsnt_a_groups[] = {
+	"gpio11",
+};
+
+static const char * const pcie2_prsnt_b_groups[] = {
+	"gpio48",
+};
+
+static const char * const pcie2_pwren_n_a_groups[] = {
+	"gpio12",
+};
+
+static const char * const pcie2_pwren_n_b_groups[] = {
+	"gpio49",
 };
 
-static const char * const pcie2_pwren_n_groups[] = {
-	"gpio12", "gpio49",
+static const char * const pcie2_pwren_a_groups[] = {
+	"gpio12",
 };
 
-static const char * const pcie2_pwren_groups[] = {
-	"gpio12", "gpio49",
+static const char * const pcie2_pwren_b_groups[] = {
+	"gpio49",
 };
 
-static const char * const pcie2_pwrflt_groups[] = {
-	"gpio13", "gpio50",
+static const char * const pcie2_pwrflt_a_groups[] = {
+	"gpio13",
+};
+
+static const char * const pcie2_pwrflt_b_groups[] = {
+	"gpio50",
 };
 
 static const char * const pcie2_clk_req_groups[] = {
@@ -499,10 +590,18 @@ static const char * const ps_hold_groups[] = {
 static const struct msm_function ipq8064_functions[] = {
 	FUNCTION(gpio),
 	FUNCTION(mdio),
-	FUNCTION(ssbi),
-	FUNCTION(spmi),
+	FUNCTION_MULTI_COPY(mi2s_a, 0x2074, 0x0),
+	FUNCTION_MULTI_COPY(mi2s_b, 0x2074, 0x1),
 	FUNCTION(mi2s),
+	FUNCTION_MULTI_COPY(pdm0_a, 0x2068, 0x0),
+	FUNCTION_MULTI_COPY(pdm0_b, 0x2068, 0x1),
+	FUNCTION_MULTI_COPY(pdm1_a, 0x206c, 0x0),
+	FUNCTION_MULTI_COPY(pdm1_b, 0x206c, 0x1),
+	FUNCTION_MULTI_COPY(pdm2_a, 0x2070, 0x0),
+	FUNCTION_MULTI_COPY(pdm2_b, 0x2070, 0x1),
 	FUNCTION(pdm),
+	FUNCTION(ssbi),
+	FUNCTION(spmi),
 	FUNCTION(audio_pcm),
 	FUNCTION(gsbi1),
 	FUNCTION(gsbi2),
@@ -511,7 +610,8 @@ static const struct msm_function ipq8064_functions[] = {
 	FUNCTION(gsbi5_spi_cs1),
 	FUNCTION(gsbi5_spi_cs2),
 	FUNCTION(gsbi5_spi_cs3),
-	FUNCTION(gsbi6),
+	FUNCTION_MULTI_COPY(gsbi6_a, 0x2088, 0x0),
+	FUNCTION_MULTI_COPY(gsbi6_b, 0x2088, 0x1),
 	FUNCTION(gsbi7),
 	FUNCTION(nss_spi),
 	FUNCTION(sdc1),
@@ -525,16 +625,24 @@ static const struct msm_function ipq8064_functions[] = {
 	FUNCTION(rgmii2),
 	FUNCTION(sata),
 	FUNCTION(pcie1_rst),
-	FUNCTION(pcie1_prsnt),
-	FUNCTION(pcie1_pwren_n),
-	FUNCTION(pcie1_pwren),
-	FUNCTION(pcie1_pwrflt),
+	FUNCTION_MULTI_COPY(pcie1_prsnt_a, 0x207c, 0),
+	FUNCTION_MULTI_COPY(pcie1_prsnt_b, 0x207c, 1),
+	FUNCTION_MULTI_COPY(pcie1_pwren_n_a, 0x207c, 0),
+	FUNCTION_MULTI_COPY(pcie1_pwren_n_b, 0x207c, 1),
+	FUNCTION_MULTI_COPY(pcie1_pwren_a, 0x207c, 0),
+	FUNCTION_MULTI_COPY(pcie1_pwren_b, 0x207c, 1),
+	FUNCTION_MULTI_COPY(pcie1_pwrflt_a, 0x207c, 0),
+	FUNCTION_MULTI_COPY(pcie1_pwrflt_b, 0x207c, 1),
 	FUNCTION(pcie1_clk_req),
 	FUNCTION(pcie2_rst),
-	FUNCTION(pcie2_prsnt),
-	FUNCTION(pcie2_pwren_n),
-	FUNCTION(pcie2_pwren),
-	FUNCTION(pcie2_pwrflt),
+	FUNCTION_MULTI_COPY(pcie2_prsnt_a, 0x2080, 0),
+	FUNCTION_MULTI_COPY(pcie2_prsnt_b, 0x2080, 1),
+	FUNCTION_MULTI_COPY(pcie2_pwren_n_a, 0x2080, 0),
+	FUNCTION_MULTI_COPY(pcie2_pwren_n_b, 0x2080, 1),
+	FUNCTION_MULTI_COPY(pcie2_pwren_a, 0x2080, 0),
+	FUNCTION_MULTI_COPY(pcie2_pwren_b, 0x2080, 1),
+	FUNCTION_MULTI_COPY(pcie2_pwrflt_a, 0x2080, 0),
+	FUNCTION_MULTI_COPY(pcie2_pwrflt_b, 0x2080, 1),
 	FUNCTION(pcie2_clk_req),
 	FUNCTION(pcie3_rst),
 	FUNCTION(pcie3_prsnt),
@@ -549,21 +657,21 @@ static const struct msm_pingroup ipq8064_groups[] = {
 	PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(3, pcie1_rst, pcie1_prsnt_b, pdm0_b, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(4, pcie1_pwren_n_b, pcie1_pwren_b, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(5, pcie1_clk_req, pcie1_pwrflt_b, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(6, gsbi7, usb_fs, gsbi5_spi_cs1, usb_fs_n, NA, NA, NA, NA, NA, NA),
 	PINGROUP(7, gsbi7, usb_fs, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(8, gsbi7, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(9, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(10, gsbi4, spdif, sata, ssbi, mdio, spmi, NA, NA, NA, NA),
-	PINGROUP(11, gsbi4, pcie2_prsnt, pcie1_prsnt, pcie3_prsnt, ssbi, mdio, spmi, NA, NA, NA),
-	PINGROUP(12, gsbi4, pcie2_pwren_n, pcie1_pwren_n, pcie3_pwren_n, pcie2_pwren, pcie1_pwren, pcie3_pwren, NA, NA, NA),
-	PINGROUP(13, gsbi4, pcie2_pwrflt, pcie1_pwrflt, pcie3_pwrflt, NA, NA, NA, NA, NA, NA),
+	PINGROUP(11, gsbi4, pcie2_prsnt_a, pcie1_prsnt_a, pcie3_prsnt, ssbi, mdio, spmi, NA, NA, NA),
+	PINGROUP(12, gsbi4, pcie2_pwren_n_a, pcie1_pwren_n_a, pcie3_pwren_n, pcie2_pwren_a, pcie1_pwren_a, pcie3_pwren, NA, NA, NA),
+	PINGROUP(13, gsbi4, pcie2_pwrflt_a, pcie1_pwrflt_a, pcie3_pwrflt, NA, NA, NA, NA, NA, NA),
 	PINGROUP(14, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(15, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(16, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(17, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(16, audio_pcm, nss_spi, pdm1_b, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(17, audio_pcm, nss_spi, pdm1_b, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(18, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(19, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(20, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
@@ -573,15 +681,15 @@ static const struct msm_pingroup ipq8064_groups[] = {
 	PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(26, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(27, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(28, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(29, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(30, mi2s, rgmii2, gsbi6, pdm, NA, NA, NA, NA, NA, NA),
-	PINGROUP(31, mi2s, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(32, mi2s, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(27, mi2s_a, rgmii2, gsbi6_a, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(28, mi2s_a, rgmii2, gsbi6_a, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(29, mi2s_a, rgmii2, gsbi6_a, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(30, mi2s, rgmii2, gsbi6_a, pdm1_a, NA, NA, NA, NA, NA, NA),
+	PINGROUP(31, mi2s, rgmii2, pdm1_a, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(32, mi2s_a, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(34, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(35, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(34, nand, pdm2_b, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(35, nand, pdm2_b, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(36, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(37, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(38, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
@@ -595,17 +703,17 @@ static const struct msm_pingroup ipq8064_groups[] = {
 	PINGROUP(46, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(47, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(48, pcie2_rst, spdif, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(49, pcie2_pwren_n, pcie2_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(50, pcie2_clk_req, pcie2_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(49, pcie2_pwren_n_b, pcie2_pwren_b, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(50, pcie2_clk_req, pcie2_pwrflt_b, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(51, gsbi1, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(52, gsbi1, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(52, gsbi1, rgmii2, pdm0_a, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(53, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(54, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(55, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
-	PINGROUP(56, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
-	PINGROUP(57, tsif1, mi2s, gsbi6, nss_spi, NA, NA, NA, NA, NA, NA),
-	PINGROUP(58, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
-	PINGROUP(59, tsif2, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(55, tsif1, mi2s_b, gsbi6_b, pdm2_a, nss_spi, NA, NA, NA, NA, NA),
+	PINGROUP(56, tsif1, mi2s_b, gsbi6_b, pdm2_a, nss_spi, NA, NA, NA, NA, NA),
+	PINGROUP(57, tsif1, mi2s_b, gsbi6_b, nss_spi, NA, NA, NA, NA, NA, NA),
+	PINGROUP(58, tsif1, mi2s_b, gsbi6_b, pdm0_a, nss_spi, NA, NA, NA, NA, NA),
+	PINGROUP(59, tsif2, rgmii2, pdm0_b, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(60, tsif2, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(61, tsif2, rgmii2, gsbi5_spi_cs1, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(62, tsif2, rgmii2, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
-- 
Qualcomm Innovation Center, Inc
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 3/4] pinctrl: qcom: apq8064: Add multi copy support

[Andy Gross]

This patch adds multiple copy support for functions that can be mapped to more
than one pin and that also require an additional mux configuration setting to
work properly.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 .../bindings/pinctrl/qcom,apq8064-pinctrl.txt      |    3 +-
 drivers/pinctrl/qcom/pinctrl-apq8064.c             |   29 +++++++++++++++-----
 2 files changed, 24 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
index a7bde64..37ffe9b 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
@@ -50,7 +50,8 @@ Valid values for function are:
   gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6,
   gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1,
   gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm,
-  riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, ps_hold
+  riva_wlan, sdc2, sdc4, slimbus_a, slimbus_b, spkr_i2s, tsif1, tsif2,
+  usb2_hsic, ps_hold
 
 Example:
 
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c
index cd96699..e2d1dc1 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c
@@ -224,6 +224,16 @@ static const unsigned int sdc3_data_pins[] = { 95 };
 		.ngroups = ARRAY_SIZE(fname##_groups),	\
 	}
 
+#define FUNCTION_MULTI_COPY(fname, reg, value)		\
+	[APQ_MUX_##fname] = {				\
+		.name = #fname,				\
+		.groups = fname##_groups,		\
+		.ngroups = ARRAY_SIZE(fname##_groups),	\
+		.requires_copy_select = 1,		\
+		.copy_select_reg = reg,			\
+		.copy_select_value = value,		\
+	}
+
 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
 	{						\
 		.name = "gpio" #id,			\
@@ -321,7 +331,8 @@ enum apq8064_functions {
 	APQ_MUX_riva_wlan,
 	APQ_MUX_sdc2,
 	APQ_MUX_sdc4,
-	APQ_MUX_slimbus,
+	APQ_MUX_slimbus_a,
+	APQ_MUX_slimbus_b,
 	APQ_MUX_spkr_i2s,
 	APQ_MUX_tsif1,
 	APQ_MUX_tsif2,
@@ -432,9 +443,12 @@ static const char * const sdc2_groups[] = {
 static const char * const sdc4_groups[] = {
 	"gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"
 };
-static const char * const slimbus_groups[] = {
+static const char * const slimbus_a_groups[] = {
 	"gpio40", "gpio41"
 };
+static const char * const slimbus_b_groups[] = {
+	"gpio30", "gpio31"
+};
 static const char * const spkr_i2s_groups[] = {
 	"gpio47", "gpio48", "gpio49", "gpio50"
 };
@@ -478,7 +492,8 @@ static const struct msm_function apq8064_functions[] = {
 	FUNCTION(riva_wlan),
 	FUNCTION(sdc2),
 	FUNCTION(sdc4),
-	FUNCTION(slimbus),
+	FUNCTION_MULTI_COPY(slimbus_a, 0x2074, 0),
+	FUNCTION_MULTI_COPY(slimbus_b, 0x2074, 1),
 	FUNCTION(spkr_i2s),
 	FUNCTION(tsif1),
 	FUNCTION(tsif2),
@@ -517,8 +532,8 @@ static const struct msm_pingroup apq8064_groups[] = {
 	PINGROUP(27, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(28, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(29, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(30, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(31, mi2s, NA, gsbi5_spi_cs2, gsbi6_spi_cs2, gsbi7_spi_cs2, NA, NA, NA, NA, NA),
+	PINGROUP(30, mi2s, slimbus_b, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(31, mi2s, slimbus_b, gsbi5_spi_cs2, gsbi6_spi_cs2, gsbi7_spi_cs2, NA, NA, NA, NA, NA),
 	PINGROUP(32, mi2s, NA, NA, NA, NA, gsbi5_spi_cs3, gsbi6_spi_cs3, gsbi7_spi_cs3, NA, NA),
 	PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(34, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
@@ -527,8 +542,8 @@ static const struct msm_pingroup apq8064_groups[] = {
 	PINGROUP(37, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(38, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(39, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(40, slimbus, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(41, slimbus, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(40, slimbus_a, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(41, slimbus_a, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(42, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(44, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-- 
Qualcomm Innovation Center, Inc
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 4/4] pinctrl: qcom: msm8960: Add multi copy support

[Andy Gross]

This patch adds multiple copy support for functions that can be mapped to more
than one pin and that also require an additional mux configuration setting to
work properly.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 .../bindings/pinctrl/qcom,msm8960-pinctrl.txt      |   19 ++++++------
 drivers/pinctrl/qcom/pinctrl-msm8960.c             |   32 +++++++++++++++-----
 2 files changed, 34 insertions(+), 17 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt
index eb8d8aa..c73ed5c 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt
@@ -103,15 +103,16 @@ to specify in a pin configuration subnode:
 		    gsbi12, hdmi_cec, hdmi_ddc_clock, hdmi_ddc_data,
 		    hdmi_hot_plug_detect, hsic, mdp_vsync, mi2s, mic_i2s,
 		    pmb_clk, pmb_ext_ctrl, ps_hold, rpm_wdog, sdc2, sdc4, sdc5,
-		    slimbus1, slimbus2, spkr_i2s, ssbi1, ssbi2, ssbi_ext_gps,
-		    ssbi_pmic2, ssbi_qpa1, ssbi_ts, tsif1, tsif2, ts_eoc,
-		    usb_fs1, usb_fs1_oe, usb_fs1_oe_n, usb_fs2, usb_fs2_oe,
-		    usb_fs2_oe_n, vfe_camif_timer1_a, vfe_camif_timer1_b,
-		    vfe_camif_timer2, vfe_camif_timer3_a, vfe_camif_timer3_b,
-		    vfe_camif_timer4_a, vfe_camif_timer4_b, vfe_camif_timer4_c,
-		    vfe_camif_timer5_a, vfe_camif_timer5_b, vfe_camif_timer6_a,
-		    vfe_camif_timer6_b, vfe_camif_timer6_c, vfe_camif_timer7_a,
-		    vfe_camif_timer7_b, vfe_camif_timer7_c, wlan
+		    slimbus1_a, slimbus1_b, slimbus2, spkr_i2s, ssbi1, ssbi2,
+		    ssbi_ext_gps, ssbi_pmic2, ssbi_qpa1, ssbi_ts, tsif1, tsif2,
+		    ts_eoc, usb_fs1, usb_fs1_oe, usb_fs1_oe_n, usb_fs2,
+		    usb_fs2_oe, usb_fs2_oe_n, vfe_camif_timer1_a,
+		    vfe_camif_timer1_b, vfe_camif_timer2, vfe_camif_timer3_a,
+		    vfe_camif_timer3_b, vfe_camif_timer4_a, vfe_camif_timer4_b,
+		    vfe_camif_timer4_c, vfe_camif_timer5_a, vfe_camif_timer5_b,
+		    vfe_camif_timer6_a, vfe_camif_timer6_b, vfe_camif_timer6_c,
+		    vfe_camif_timer7_a, vfe_camif_timer7_b, vfe_camif_timer7_c,
+		    wlan
 
 - bias-disable:
 	Usage: optional
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8960.c b/drivers/pinctrl/qcom/pinctrl-msm8960.c
index ed23e36..39e76b9 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8960.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c
@@ -349,6 +349,16 @@ static const unsigned int sdc3_data_pins[] = { 157 };
 		.ngroups = ARRAY_SIZE(fname##_groups),	\
 	}
 
+#define FUNCTION_MULTI_COPY(fname, reg, value)		\
+	[MSM_MUX_##fname] = {				\
+		.name = #fname,				\
+		.groups = fname##_groups,		\
+		.ngroups = ARRAY_SIZE(fname##_groups),	\
+		.requires_copy_select = 1,		\
+		.copy_select_reg = reg,			\
+		.copy_select_value = value,		\
+	}
+
 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
 	{						\
 		.name = "gpio" #id,			\
@@ -487,7 +497,8 @@ enum msm8960_functions {
 	MSM_MUX_sdc2,
 	MSM_MUX_sdc4,
 	MSM_MUX_sdc5,
-	MSM_MUX_slimbus1,
+	MSM_MUX_slimbus1_a,
+	MSM_MUX_slimbus1_b,
 	MSM_MUX_slimbus2,
 	MSM_MUX_spkr_i2s,
 	MSM_MUX_ssbi1,
@@ -824,8 +835,12 @@ static const char * const sdc5_groups[] = {
 	"gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82"
 };
 
-static const char * const slimbus1_groups[] = {
-	"gpio50", "gpio51", "gpio60", "gpio61"
+static const char * const slimbus1_a_groups[] = {
+	"gpio60", "gpio61"
+};
+
+static const char * const slimbus1_b_groups[] = {
+	"gpio50", "gpio51",
 };
 
 static const char * const slimbus2_groups[] = {
@@ -1034,7 +1049,8 @@ static const struct msm_function msm8960_functions[] = {
 	FUNCTION(sdc2),
 	FUNCTION(sdc4),
 	FUNCTION(sdc5),
-	FUNCTION(slimbus1),
+	FUNCTION_MULTI_COPY(slimbus1_a, 0x2074, 0),
+	FUNCTION_MULTI_COPY(slimbus1_b, 0x2074, 1),
 	FUNCTION(slimbus2),
 	FUNCTION(spkr_i2s),
 	FUNCTION(ssbi1),
@@ -1122,8 +1138,8 @@ static const struct msm_pingroup msm8960_groups[] = {
 	PINGROUP(47, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(48, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(49, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(50, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(51, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(50, mi2s, slimbus1_b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(51, mi2s, slimbus1_b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(52, mi2s, gp_clk_2a, gsbi2_spi_cs1_n, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(53, mi2s, gp_pdm_2b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(54, codec_mic_i2s, gp_clk_0b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
@@ -1132,8 +1148,8 @@ static const struct msm_pingroup msm8960_groups[] = {
 	PINGROUP(57, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(58, codec_mic_i2s, gp_pdm_0a, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(59, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(60, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(61, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(60, slimbus1_a, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(61, slimbus1_a, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(62, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(63, audio_pcm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 	PINGROUP(64, audio_pcm, gp_pdm_1b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-- 
Qualcomm Innovation Center, Inc
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 0/4] pinctrl: qcom: Add multiple copy support

[Linus Walleij]

On Thu, Dec 18, 2014 at 9:59 PM, Andy Gross <agross-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> wrote:

> These patches add multiple copy support for functions which require additional
> mux configurations on specific Qualcomm processor pincontrol blocks.  Functions
> which may have multiple copies are slimbus, mi2s, pdm, pcie, and GSBI.

Björn, can you look at this?

Yours,
Linus Walleij
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Re: [PATCH 1/4] pinctrl: qcom: Add multiple copy base support

[Bjorn]

On Thu 18 Dec 12:59 PST 2014, Andy Gross wrote:

> Qualcomm pinctrl devices support functions that can be routed to multiple pins.
> In some cases, there are additional mux registers that must be set for the pins
> to work correctly.
> 

I've described it as "second level muxing", but your description works too...

[..]

> +	/*
> +	 * if an alternate copy configuration is required, configure the pins to
> +	 * steer the function to the correct set of pins.  This is used in cases
> +	 * where we have more than one copy of the pins for a function
> +	 */
> +	if (f->requires_copy_select)
> +		writel(f->copy_select_value, pctrl->regs + f->copy_select_reg);

I'm not sure if this is sufficient.

In the APQ8064 case (patch 3) you use this to write 0 or 1 to $2074, but if I
read the documentation correctly you should also write to $207c and $2080 to
enable/disable slew rate control of the individual paths.

On 8974 we don't have the muxing, but the documentation states that we should
set bit 0 of $2030 depending on slimbus being muxed or not. (not sure what to
do about bit 1 though)


I looked at assigning an optional function pointer to the function, that way we
could easily express the platform specific tweaks in the individual drivers.

However, as the muxing is deselected we need to make sure the slew rate is
disabled and the only sane way I can think of then would be to tie this to the
pingroup, as selecting any other entry from the pingroup should trigger the
reset.

Regards,
Bjorn