[PATCH 0/4] ARM: shmobile: Add DT support for memory controllers

[PATCH 0/4] ARM: shmobile: Add DT support for memory controllers

[Geert Uytterhoeven]

	Hi Simon, Magnus,

This patch series adds DT binding documentation and devices nodes to
describe memory-controllers in R-Mobile and SH-Mobile SoCs.

Currently memory controller device nodes are used only to reference PM
domains, and prevent these PM domains from being powered down, which
would crash the system.

As such this series is a prerequisite for adding DT PM domain support to
sh73a0 (SH-Mobile AG5) and r7a73a4 (R-Mobile APE6).
For r8a7740 (R-Mobile A1), this wasn't a hard prerequisite for PM
domain support, as the A4S PM domain is never turned off anyway
because its child PM domain A3SM contains the CPU core.

The patches for sh73a0 and r8a7740 have been sent before as part of
(patches in) the series "[PATCH RFC 0/7] ARM: shmobile: sh73a0: DT PM
domain support" (https://lkml.org/lkml/2014/11/19/404).

"ARM: shmobile: r8a7740 dtsi: Add memory-controller node" depends on
the DT R-Mobile PM Domain support for r8a7740 that's queued up in
Simon's tree under tag renesas-dt-pm-for-v3.20, as the
memory-controller node already contains a power-domains property.

The two other dtsi patches do not add power-domains properties yet.
These will be added when adding PM domain support for sh73a0 resp.
r8a73a4.

Thanks!

Geert Uytterhoeven (4):
  ARM: shmobile: Add DT bindings for Renesas memory controllers
  ARM: shmobile: r8a73a4 dtsi: Add memory-controller nodes
  ARM: shmobile: r8a7740 dtsi: Add memory-controller node
  ARM: shmobile: sh73a0 dtsi: Add memory-controller nodes

 .../renesas-memory-controllers.txt                 | 44 ++++++++++++++++++++++
 arch/arm/boot/dts/r8a73a4.dtsi                     | 10 +++++
 arch/arm/boot/dts/r8a7740.dtsi                     |  6 +++
 arch/arm/boot/dts/sh73a0.dtsi                      | 16 ++++++++
 4 files changed, 76 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt

-- 
1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH 1/4] ARM: shmobile: Add DT bindings for Renesas memory controllers

[Geert Uytterhoeven]

Add DT bindings for Renesas R-Mobile and SH-Mobile memory controllers.
Currently memory controller device nodes are used only to reference PM
domains, and prevent these PM domains from being powered down, which
would crash the system.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 .../renesas-memory-controllers.txt                 | 44 ++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt

diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt b/Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt
new file mode 100644
index 0000000000000000..c64b7925cd0924e8
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt
@@ -0,0 +1,44 @@
+DT bindings for Renesas R-Mobile and SH-Mobile memory controllers
+=================================================================
+
+Renesas R-Mobile and SH-Mobile SoCs contain one or more memory controllers.
+These memory controllers differ from one SoC variant to another, and are called
+by different names ("DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
+(DBSC3)", "SDRAM Bus State Controller (SBSC)").
+
+Currently memory controller device nodes are used only to reference PM
+domains, and prevent these PM domains from being powered down, which would
+crash the system.
+
+As there exist no actual drivers for these controllers yet, these bindings
+should be considered EXPERIMENTAL for now.
+
+Required properties:
+  - compatible: Must be one of the following SoC-specific values:
+		  - "renesas,dbsc-r8a73a4" (R-Mobile APE6)
+		  - "renesas,dbsc3-r8a7740" (R-Mobile A1)
+		  - "renesas,sbsc-sh73a0" (SH-Mobile AG5)
+  - reg: Must contain the base address and length of the memory controller's
+	 registers.
+
+Optional properties:
+  - interrupts: Must contain a list of interrupt specifiers for memory
+		controller interrupts, if available.
+  - interrupts-names: Must contain a list of interrupt names corresponding to
+		      the interrupts in the interrupts property, if available.
+		      Valid interrupt names are:
+			- "sec" (secure interrupt)
+			- "temp" (normal (temperature) interrupt)
+  - power-domains: Must contain a reference to the PM domain that the memory
+		   controller belongs to, if available.
+
+Example:
+
+	sbsc1: memory-controller@fe400000 {
+		compatible = "renesas,sbsc-sh73a0";
+		reg = <0xfe400000 0x400>;
+		interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 36 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "sec", "temp";
+		power-domains = <&pd_a4bc0>;
+	};
-- 
1.9.1

[PATCH 2/4] ARM: shmobile: r8a73a4 dtsi: Add memory-controller nodes

[Geert Uytterhoeven]

Add device nodes for the two DDR Bus State Controllers (DBSC).
The DBSCs are located in the A3BC PM domain, which must not be powered
down, else the system will crash.

A reference to the A3BC PM domain will be added later.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/boot/dts/r8a73a4.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 6291a57fe8bf440f..424c189640812c91 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -38,6 +38,16 @@
 			     <1 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
+	dbsc1: memory-controller@e6790000 {
+		compatible = "renesas,dbsc-r8a73a4";
+		reg = <0 0xe6790000 0 0x10000>;
+	};
+
+	dbsc2: memory-controller@e67a0000 {
+		compatible = "renesas,dbsc-r8a73a4";
+		reg = <0 0xe67a0000 0 0x10000>;
+	};
+
 	dmac: dma-multiplexer {
 		compatible = "renesas,shdma-mux";
 		#dma-cells = <1>;
-- 
1.9.1

[PATCH 3/4] ARM: shmobile: r8a7740 dtsi: Add memory-controller node

[Geert Uytterhoeven]

Add a device node for the DDR3 Bus State Controller (DBSC3).
The DBSC3 is located in the A4S PM domain, which must not be powered
down, else the system will crash.

This has no visible effect for now, as A4S was never turned off anyway
because its child PM domain A3SM contains the CPU core.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/boot/dts/r8a7740.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 52f2cf4b84d3ccb4..8a092605d641f7d4 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -37,6 +37,12 @@
 		      <0xc2000000 0x1000>;
 	};
 
+	dbsc3: memory-controller@fe400000 {
+		compatible = "renesas,dbsc3-r8a7740";
+		reg = <0xfe400000 0x400>;
+		power-domains = <&pd_a4s>;
+	};
+
 	pmu {
 		compatible = "arm,cortex-a9-pmu";
 		interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
-- 
1.9.1

[PATCH 4/4] ARM: shmobile: sh73a0 dtsi: Add memory-controller nodes

[Geert Uytterhoeven]

Add device nodes for the two SDRAM Bus State Controllers.
The SBSCs are located in the A4BC0 resp. A4BC1 PM domains, which must
not be powered down, else the system will crash.

References to the A4BC0 and A4BC1 PM domains will be added later.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/boot/dts/sh73a0.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 46954ac26dd9fb41..8d9c2ce593745b1f 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -43,6 +43,22 @@
 		      <0xf0000100 0x100>;
 	};
 
+	sbsc2: memory-controller@fb400000 {
+		compatible = "renesas,sbsc-sh73a0";
+		reg = <0xfb400000 0x400>;
+		interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 38 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "sec", "temp";
+	};
+
+	sbsc1: memory-controller@fe400000 {
+		compatible = "renesas,sbsc-sh73a0";
+		reg = <0xfe400000 0x400>;
+		interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 36 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "sec", "temp";
+	};
+
 	pmu {
 		compatible = "arm,cortex-a9-pmu";
 		interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>,
-- 
1.9.1

Re: [PATCH 0/4] ARM: shmobile: Add DT support for memory controllers

[Simon Horman]

On Wed, Jan 14, 2015 at 12:12:58PM +0100, Geert Uytterhoeven wrote:
> 	Hi Simon, Magnus,
> 
> This patch series adds DT binding documentation and devices nodes to
> describe memory-controllers in R-Mobile and SH-Mobile SoCs.
> 
> Currently memory controller device nodes are used only to reference PM
> domains, and prevent these PM domains from being powered down, which
> would crash the system.
> 
> As such this series is a prerequisite for adding DT PM domain support to
> sh73a0 (SH-Mobile AG5) and r7a73a4 (R-Mobile APE6).
> For r8a7740 (R-Mobile A1), this wasn't a hard prerequisite for PM
> domain support, as the A4S PM domain is never turned off anyway
> because its child PM domain A3SM contains the CPU core.
> 
> The patches for sh73a0 and r8a7740 have been sent before as part of
> (patches in) the series "[PATCH RFC 0/7] ARM: shmobile: sh73a0: DT PM
> domain support" (https://lkml.org/lkml/2014/11/19/404).
> 
> "ARM: shmobile: r8a7740 dtsi: Add memory-controller node" depends on
> the DT R-Mobile PM Domain support for r8a7740 that's queued up in
> Simon's tree under tag renesas-dt-pm-for-v3.20, as the
> memory-controller node already contains a power-domains property.
> 
> The two other dtsi patches do not add power-domains properties yet.
> These will be added when adding PM domain support for sh73a0 resp.
> r8a73a4.
> 
> Thanks!

Thanks Geert, I have queued these up.