From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tomi Valkeinen Subject: [PATCH 1/9] arm/dts: dra7xx: add 'ti,set-rate-parent' for dss_dss_clk Date: Fri, 13 Feb 2015 17:11:18 +0200 Message-ID: <1423840286-18377-2-git-send-email-tomi.valkeinen@ti.com> References: <1423840286-18377-1-git-send-email-tomi.valkeinen@ti.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1423840286-18377-1-git-send-email-tomi.valkeinen@ti.com> Sender: linux-omap-owner@vger.kernel.org To: Tony Lindgren , Paul Walmsley , =?UTF-8?q?Beno=C3=AEt=20Cousson?= , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Nishanth Menon , Felipe Balbi , Tero Kristo , Tomi Valkeinen , devicetree@vger.kernel.org List-Id: devicetree@vger.kernel.org We need set-rate-parent flags for the display's clock path so that the DSS driver can change the clock rate of the PLL. This patchs adds the ti,set-rate-parent flag to 'dss_dss_clk' clock node, which is only a gate clock, allowing the setting of the clock rate to propagate to the PLL. Signed-off-by: Tomi Valkeinen Cc: devicetree@vger.kernel.org --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 4bdcbd61ce47..0d76233840e6 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1451,6 +1451,7 @@ clocks = <&dpll_per_h12x2_ck>; ti,bit-shift = <8>; reg = <0x1120>; + ti,set-rate-parent; }; dss_hdmi_clk: dss_hdmi_clk { -- 2.3.0