* [Patch V6 01/10] MAINTAINERS: Add QCOM audio ASoC maintainer
2015-02-25 6:39 [Patch V6 00/10] ASoC: QCOM: Add support for ipq806x SOC Kenneth Westfield
@ 2015-02-25 6:39 ` Kenneth Westfield
2015-02-25 6:39 ` [Patch V6 02/10] ASoC: qcom: Document LPASS CPU bindings Kenneth Westfield
` (8 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Kenneth Westfield @ 2015-02-25 6:39 UTC (permalink / raw)
To: Mark Brown, Takashi Iwai, Liam Girdwood, Banajit Goswami,
Patrick Lai, David Brown, Bryan Huntsman, Greg KH
Cc: MSM Mailing List, Kenneth Westfield, ALSA Mailing List,
Kernel Mailing List, Device Tree Mailing List
From: Kenneth Westfield <kwestfie@codeaurora.org>
Add maintainers for the Qualcomm Technologies
sound drivers.
Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org>
Acked-by: Banajit Goswami <bgoswami@codeaurora.org>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index ddc5a8cf9a8ac0078f8ca1bc99d9c48f8197214a..9514b794b74d7fb93072bbdbaefaaa79df38c5fd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5254,6 +5254,13 @@ F: drivers/char/ipmi/
F: include/linux/ipmi*
F: include/uapi/linux/ipmi*
+QCOM AUDIO (ASoC) DRIVERS
+M: Patrick Lai <plai@codeaurora.org>
+M: Banajit Goswami <bgoswami@codeaurora.org>
+L: alsa-devel@alsa-project.org (moderated for non-subscribers)
+S: Supported
+F: sound/soc/qcom/
+
IPS SCSI RAID DRIVER
M: Adaptec OEM Raid Solutions <aacraid@adaptec.com>
L: linux-scsi@vger.kernel.org
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Patch V6 02/10] ASoC: qcom: Document LPASS CPU bindings
2015-02-25 6:39 [Patch V6 00/10] ASoC: QCOM: Add support for ipq806x SOC Kenneth Westfield
2015-02-25 6:39 ` [Patch V6 01/10] MAINTAINERS: Add QCOM audio ASoC maintainer Kenneth Westfield
@ 2015-02-25 6:39 ` Kenneth Westfield
2015-02-25 6:39 ` [Patch V6 03/10] ASoC: qcom: Document Storm bindings Kenneth Westfield
` (7 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Kenneth Westfield @ 2015-02-25 6:39 UTC (permalink / raw)
To: Mark Brown, Takashi Iwai, Liam Girdwood, Banajit Goswami,
Patrick Lai, David Brown, Bryan Huntsman, Greg KH
Cc: Kenneth Westfield, ALSA Mailing List, MSM Mailing List,
Device Tree Mailing List, Kernel Mailing List
From: Kenneth Westfield <kwestfie@codeaurora.org>
Add documentation to the sound directory of the
device-tree bindings for the QTi LPASS CPU DAI
device.
Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org>
Acked-by: Banajit Goswami <bgoswami@codeaurora.org>
---
.../devicetree/bindings/sound/qcom,lpass-cpu.txt | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt
diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt b/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt
new file mode 100644
index 0000000000000000000000000000000000000000..e7c6e9321863f022ebf0d51b75d7bb83c10b9062
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt
@@ -0,0 +1,49 @@
+* Qualcomm Technologies LPASS CPU DAI
+
+This node models the Qualcomm Technologies Low-Power Audio SubSystem (LPASS).
+
+Required properties:
+
+- compatible : "qcom,lpass-cpu"
+- clocks : Must contain an entry for each entry in clock-names.
+- clock-names : A list which must include the following entries:
+ * "ahbix-clk"
+ * "mi2s-osr-clk"
+ * "mi2s-bit-clk"
+- interrupts : Must contain an entry for each entry in
+ interrupt-names.
+- interrupt-names : A list which must include the following entries:
+ * "lpass-irq-lpaif"
+- pinctrl-N : One property must exist for each entry in
+ pinctrl-names. See ../pinctrl/pinctrl-bindings.txt
+ for details of the property values.
+- pinctrl-names : Must contain a "default" entry.
+- reg : Must contain an address for each entry in reg-names.
+- reg-names : A list which must include the following entries:
+ * "lpass-lpaif"
+
+Required subnodes:
+
+- qcom,adsp : Audio DSP sub-node
+
+Optional Audio DSP subnode properties:
+
+- status : "disabled" indicates the adsp is not available.
+
+Example:
+
+lpass@28100000 {
+ compatible = "qcom,lpass-cpu";
+ clocks = <&lcc AHBIX_CLK>, <&lcc MI2S_OSR_CLK>, <&lcc MI2S_BIT_CLK>;
+ clock-names = "ahbix-clk", "mi2s-osr-clk", "mi2s-bit-clk";
+ interrupts = <0 85 1>;
+ interrupt-names = "lpass-irq-lpaif";
+ pinctrl-names = "default", "idle";
+ pinctrl-0 = <&mi2s_default>;
+ pinctrl-1 = <&mi2s_idle>;
+ reg = <0x28100000 0x10000>;
+ reg-names = "lpass-lpaif";
+ qcom,adsp {
+ status = "disabled";
+ };
+};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Patch V6 03/10] ASoC: qcom: Document Storm bindings
2015-02-25 6:39 [Patch V6 00/10] ASoC: QCOM: Add support for ipq806x SOC Kenneth Westfield
2015-02-25 6:39 ` [Patch V6 01/10] MAINTAINERS: Add QCOM audio ASoC maintainer Kenneth Westfield
2015-02-25 6:39 ` [Patch V6 02/10] ASoC: qcom: Document LPASS CPU bindings Kenneth Westfield
@ 2015-02-25 6:39 ` Kenneth Westfield
2015-02-25 6:39 ` [Patch V6 04/10] ASoC: qcom: add LPASS header files Kenneth Westfield
` (6 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Kenneth Westfield @ 2015-02-25 6:39 UTC (permalink / raw)
To: Mark Brown, Takashi Iwai, Liam Girdwood, Banajit Goswami,
Patrick Lai, David Brown, Bryan Huntsman, Greg KH
Cc: Kenneth Westfield, ALSA Mailing List, MSM Mailing List,
Device Tree Mailing List, Kernel Mailing List
From: Kenneth Westfield <kwestfie@codeaurora.org>
Add documentation to the sound directory of the
device-tree bindings for the soundcard of the
Storm board.
Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org>
Acked-by: Banajit Goswami <bgoswami@codeaurora.org>
---
Documentation/devicetree/bindings/sound/storm.txt | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/storm.txt
diff --git a/Documentation/devicetree/bindings/sound/storm.txt b/Documentation/devicetree/bindings/sound/storm.txt
new file mode 100644
index 0000000000000000000000000000000000000000..2a308e9c4cd3f9550c0b7078200a14a787f02858
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/storm.txt
@@ -0,0 +1,23 @@
+* Sound complex for Storm boards
+
+Models a soundcard for Storm boards with the Qualcomm Technologies IPQ806x SOC
+connected to a MAX98357A DAC via I2S.
+
+Required properties:
+
+- compatible : "google,storm"
+- cpu : Phandle of the CPU DAI
+- codec : Phandle of the codec DAI
+
+Optional properties:
+
+- qcom,model : The user-visible name of this sound card.
+
+Example:
+
+sound {
+ compatible = "google,storm";
+ qcom,model = "ipq806x-storm";
+ cpu = <&lpass_cpu>;
+ codec = <&max98357a>;
+};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Patch V6 04/10] ASoC: qcom: add LPASS header files
2015-02-25 6:39 [Patch V6 00/10] ASoC: QCOM: Add support for ipq806x SOC Kenneth Westfield
` (2 preceding siblings ...)
2015-02-25 6:39 ` [Patch V6 03/10] ASoC: qcom: Document Storm bindings Kenneth Westfield
@ 2015-02-25 6:39 ` Kenneth Westfield
2015-02-25 6:39 ` [Patch V6 05/10] ASoC: qcom: Add LPASS CPU DAI driver Kenneth Westfield
` (5 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Kenneth Westfield @ 2015-02-25 6:39 UTC (permalink / raw)
To: Mark Brown, Takashi Iwai, Liam Girdwood, Banajit Goswami,
Patrick Lai, David Brown, Bryan Huntsman, Greg KH
Cc: Kenneth Westfield, ALSA Mailing List, MSM Mailing List,
Device Tree Mailing List, Kernel Mailing List
From: Kenneth Westfield <kwestfie@codeaurora.org>
Add the LPASS header files for ipq806x SOC. This
includes the register definitions for the ipq806x
LPAIF, and the structure definition for the driver
data.
Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org>
Acked-by: Banajit Goswami <bgoswami@codeaurora.org>
---
sound/soc/qcom/lpass-lpaif-ipq806x.h | 172 +++++++++++++++++++++++++++++++++++
sound/soc/qcom/lpass.h | 51 +++++++++++
2 files changed, 223 insertions(+)
create mode 100644 sound/soc/qcom/lpass-lpaif-ipq806x.h
create mode 100644 sound/soc/qcom/lpass.h
diff --git a/sound/soc/qcom/lpass-lpaif-ipq806x.h b/sound/soc/qcom/lpass-lpaif-ipq806x.h
new file mode 100644
index 0000000000000000000000000000000000000000..dc423b8888425e60ebb11cd0ce78da2574ed27c2
--- /dev/null
+++ b/sound/soc/qcom/lpass-lpaif-ipq806x.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * lpass-lpaif-ipq806x.h -- Definitions for the QTi LPAIF in the ipq806x LPASS
+ */
+
+#ifndef __LPASS_LPAIF_H__
+#define __LPASS_LPAIF_H__
+
+#define LPAIF_BANK_OFFSET 0x1000
+
+/* LPAIF I2S */
+
+#define LPAIF_I2SCTL_REG_BASE 0x0010
+#define LPAIF_I2SCTL_REG_STRIDE 0x4
+#define LPAIF_I2SCTL_REG_ADDR(addr, port) \
+ (LPAIF_I2SCTL_REG_BASE + (addr) + (LPAIF_I2SCTL_REG_STRIDE * (port)))
+
+enum lpaif_i2s_ports {
+ LPAIF_I2S_PORT_MIN = 0,
+
+ LPAIF_I2S_PORT_CODEC_SPK = 0,
+ LPAIF_I2S_PORT_CODEC_MIC = 1,
+ LPAIF_I2S_PORT_SEC_SPK = 2,
+ LPAIF_I2S_PORT_SEC_MIC = 3,
+ LPAIF_I2S_PORT_MI2S = 4,
+
+ LPAIF_I2S_PORT_MAX = 4,
+ LPAIF_I2S_PORT_NUM = 5,
+};
+
+#define LPAIF_I2SCTL_REG(port) LPAIF_I2SCTL_REG_ADDR(0x0, (port))
+
+#define LPAIF_I2SCTL_LOOPBACK_MASK 0x8000
+#define LPAIF_I2SCTL_LOOPBACK_SHIFT 15
+#define LPAIF_I2SCTL_LOOPBACK_DISABLE (0 << LPAIF_I2SCTL_LOOPBACK_SHIFT)
+#define LPAIF_I2SCTL_LOOPBACK_ENABLE (1 << LPAIF_I2SCTL_LOOPBACK_SHIFT)
+
+#define LPAIF_I2SCTL_SPKEN_MASK 0x4000
+#define LPAIF_I2SCTL_SPKEN_SHIFT 14
+#define LPAIF_I2SCTL_SPKEN_DISABLE (0 << LPAIF_I2SCTL_SPKEN_SHIFT)
+#define LPAIF_I2SCTL_SPKEN_ENABLE (1 << LPAIF_I2SCTL_SPKEN_SHIFT)
+
+#define LPAIF_I2SCTL_SPKMODE_MASK 0x3C00
+#define LPAIF_I2SCTL_SPKMODE_SHIFT 10
+#define LPAIF_I2SCTL_SPKMODE_NONE (0 << LPAIF_I2SCTL_SPKMODE_SHIFT)
+#define LPAIF_I2SCTL_SPKMODE_SD0 (1 << LPAIF_I2SCTL_SPKMODE_SHIFT)
+#define LPAIF_I2SCTL_SPKMODE_SD1 (2 << LPAIF_I2SCTL_SPKMODE_SHIFT)
+#define LPAIF_I2SCTL_SPKMODE_SD2 (3 << LPAIF_I2SCTL_SPKMODE_SHIFT)
+#define LPAIF_I2SCTL_SPKMODE_SD3 (4 << LPAIF_I2SCTL_SPKMODE_SHIFT)
+#define LPAIF_I2SCTL_SPKMODE_QUAD01 (5 << LPAIF_I2SCTL_SPKMODE_SHIFT)
+#define LPAIF_I2SCTL_SPKMODE_QUAD23 (6 << LPAIF_I2SCTL_SPKMODE_SHIFT)
+#define LPAIF_I2SCTL_SPKMODE_6CH (7 << LPAIF_I2SCTL_SPKMODE_SHIFT)
+#define LPAIF_I2SCTL_SPKMODE_8CH (8 << LPAIF_I2SCTL_SPKMODE_SHIFT)
+
+#define LPAIF_I2SCTL_SPKMONO_MASK 0x0200
+#define LPAIF_I2SCTL_SPKMONO_SHIFT 9
+#define LPAIF_I2SCTL_SPKMONO_STEREO (0 << LPAIF_I2SCTL_SPKMONO_SHIFT)
+#define LPAIF_I2SCTL_SPKMONO_MONO (1 << LPAIF_I2SCTL_SPKMONO_SHIFT)
+
+#define LPAIF_I2SCTL_WSSRC_MASK 0x0004
+#define LPAIF_I2SCTL_WSSRC_SHIFT 2
+#define LPAIF_I2SCTL_WSSRC_INTERNAL (0 << LPAIF_I2SCTL_WSSRC_SHIFT)
+#define LPAIF_I2SCTL_WSSRC_EXTERNAL (1 << LPAIF_I2SCTL_WSSRC_SHIFT)
+
+#define LPAIF_I2SCTL_BITWIDTH_MASK 0x0003
+#define LPAIF_I2SCTL_BITWIDTH_SHIFT 0
+#define LPAIF_I2SCTL_BITWIDTH_16 (0 << LPAIF_I2SCTL_BITWIDTH_SHIFT)
+#define LPAIF_I2SCTL_BITWIDTH_24 (1 << LPAIF_I2SCTL_BITWIDTH_SHIFT)
+#define LPAIF_I2SCTL_BITWIDTH_32 (2 << LPAIF_I2SCTL_BITWIDTH_SHIFT)
+
+/* LPAIF IRQ */
+
+#define LPAIF_IRQ_REG_BASE 0x3000
+#define LPAIF_IRQ_REG_STRIDE 0x1000
+#define LPAIF_IRQ_REG_ADDR(addr, port) \
+ (LPAIF_IRQ_REG_BASE + (addr) + (LPAIF_IRQ_REG_STRIDE * (port)))
+
+enum lpaif_irq_ports {
+ LPAIF_IRQ_PORT_MIN = 0,
+
+ LPAIF_IRQ_PORT_HOST = 0,
+ LPAIF_IRQ_PORT_ADSP = 1,
+
+ LPAIF_IRQ_PORT_MAX = 2,
+ LPAIF_IRQ_PORT_NUM = 3,
+};
+
+#define LPAIF_IRQEN_REG(port) LPAIF_IRQ_REG_ADDR(0x0, (port))
+#define LPAIF_IRQSTAT_REG(port) LPAIF_IRQ_REG_ADDR(0x4, (port))
+#define LPAIF_IRQCLEAR_REG(port) LPAIF_IRQ_REG_ADDR(0xC, (port))
+
+#define LPAIF_IRQ_BITSTRIDE 3
+#define LPAIF_IRQ_PER(chan) (1 << (LPAIF_IRQ_BITSTRIDE * (chan)))
+#define LPAIF_IRQ_XRUN(chan) (2 << (LPAIF_IRQ_BITSTRIDE * (chan)))
+#define LPAIF_IRQ_ERR(chan) (4 << (LPAIF_IRQ_BITSTRIDE * (chan)))
+#define LPAIF_IRQ_ALL(chan) (7 << (LPAIF_IRQ_BITSTRIDE * (chan)))
+
+/* LPAIF DMA */
+
+#define LPAIF_RDMA_REG_BASE 0x6000
+#define LPAIF_RDMA_REG_STRIDE 0x1000
+#define LPAIF_RDMA_REG_ADDR(addr, chan) \
+ (LPAIF_RDMA_REG_BASE + (addr) + (LPAIF_RDMA_REG_STRIDE * (chan)))
+
+enum lpaif_dma_channels {
+ LPAIF_RDMA_CHAN_MIN = 0,
+
+ LPAIF_RDMA_CHAN_MI2S = 0,
+ LPAIF_RDMA_CHAN_PCM0 = 1,
+ LPAIF_RDMA_CHAN_PCM1 = 2,
+
+ LPAIF_RDMA_CHAN_MAX = 4,
+ LPAIF_RDMA_CHAN_NUM = 5,
+};
+
+#define LPAIF_RDMACTL_REG(chan) LPAIF_RDMA_REG_ADDR(0x00, (chan))
+#define LPAIF_RDMABASE_REG(chan) LPAIF_RDMA_REG_ADDR(0x04, (chan))
+#define LPAIF_RDMABUFF_REG(chan) LPAIF_RDMA_REG_ADDR(0x08, (chan))
+#define LPAIF_RDMACURR_REG(chan) LPAIF_RDMA_REG_ADDR(0x0C, (chan))
+#define LPAIF_RDMAPER_REG(chan) LPAIF_RDMA_REG_ADDR(0x10, (chan))
+
+#define LPAIF_RDMACTL_BURSTEN_MASK 0x800
+#define LPAIF_RDMACTL_BURSTEN_SHIFT 11
+#define LPAIF_RDMACTL_BURSTEN_SINGLE (0 << LPAIF_RDMACTL_BURSTEN_SHIFT)
+#define LPAIF_RDMACTL_BURSTEN_INCR4 (1 << LPAIF_RDMACTL_BURSTEN_SHIFT)
+
+#define LPAIF_RDMACTL_WPSCNT_MASK 0x700
+#define LPAIF_RDMACTL_WPSCNT_SHIFT 8
+#define LPAIF_RDMACTL_WPSCNT_ONE (0 << LPAIF_RDMACTL_WPSCNT_SHIFT)
+#define LPAIF_RDMACTL_WPSCNT_TWO (1 << LPAIF_RDMACTL_WPSCNT_SHIFT)
+#define LPAIF_RDMACTL_WPSCNT_THREE (2 << LPAIF_RDMACTL_WPSCNT_SHIFT)
+#define LPAIF_RDMACTL_WPSCNT_FOUR (3 << LPAIF_RDMACTL_WPSCNT_SHIFT)
+#define LPAIF_RDMACTL_WPSCNT_SIX (5 << LPAIF_RDMACTL_WPSCNT_SHIFT)
+#define LPAIF_RDMACTL_WPSCNT_EIGHT (7 << LPAIF_RDMACTL_WPSCNT_SHIFT)
+
+#define LPAIF_RDMACTL_AUDINTF_MASK 0x0F0
+#define LPAIF_RDMACTL_AUDINTF_SHIFT 4
+#define LPAIF_RDMACTL_AUDINTF_NONE (0 << LPAIF_RDMACTL_AUDINTF_SHIFT)
+#define LPAIF_RDMACTL_AUDINTF_CODEC (1 << LPAIF_RDMACTL_AUDINTF_SHIFT)
+#define LPAIF_RDMACTL_AUDINTF_PCM (2 << LPAIF_RDMACTL_AUDINTF_SHIFT)
+#define LPAIF_RDMACTL_AUDINTF_SEC_I2S (3 << LPAIF_RDMACTL_AUDINTF_SHIFT)
+#define LPAIF_RDMACTL_AUDINTF_MI2S (4 << LPAIF_RDMACTL_AUDINTF_SHIFT)
+#define LPAIF_RDMACTL_AUDINTF_HDMI (5 << LPAIF_RDMACTL_AUDINTF_SHIFT)
+#define LPAIF_RDMACTL_AUDINTF_SEC_PCM (7 << LPAIF_RDMACTL_AUDINTF_SHIFT)
+
+#define LPAIF_RDMACTL_FIFOWM_MASK 0x00E
+#define LPAIF_RDMACTL_FIFOWM_SHIFT 1
+#define LPAIF_RDMACTL_FIFOWM_1 (0 << LPAIF_RDMACTL_FIFOWM_SHIFT)
+#define LPAIF_RDMACTL_FIFOWM_2 (1 << LPAIF_RDMACTL_FIFOWM_SHIFT)
+#define LPAIF_RDMACTL_FIFOWM_3 (2 << LPAIF_RDMACTL_FIFOWM_SHIFT)
+#define LPAIF_RDMACTL_FIFOWM_4 (3 << LPAIF_RDMACTL_FIFOWM_SHIFT)
+#define LPAIF_RDMACTL_FIFOWM_5 (4 << LPAIF_RDMACTL_FIFOWM_SHIFT)
+#define LPAIF_RDMACTL_FIFOWM_6 (5 << LPAIF_RDMACTL_FIFOWM_SHIFT)
+#define LPAIF_RDMACTL_FIFOWM_7 (6 << LPAIF_RDMACTL_FIFOWM_SHIFT)
+#define LPAIF_RDMACTL_FIFOWM_8 (7 << LPAIF_RDMACTL_FIFOWM_SHIFT)
+
+#define LPAIF_RDMACTL_ENABLE_MASK 0x1
+#define LPAIF_RDMACTL_ENABLE_SHIFT 0
+#define LPAIF_RDMACTL_ENABLE_OFF (0 << LPAIF_RDMACTL_ENABLE_SHIFT)
+#define LPAIF_RDMACTL_ENABLE_ON (1 << LPAIF_RDMACTL_ENABLE_SHIFT)
+
+#endif /* __LPASS_LPAIF_H__ */
diff --git a/sound/soc/qcom/lpass.h b/sound/soc/qcom/lpass.h
new file mode 100644
index 0000000000000000000000000000000000000000..315b981ef89dbe5ab060a58b2cce79c7704c32ed
--- /dev/null
+++ b/sound/soc/qcom/lpass.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * lpass.h - Definitions for the QTi LPASS
+ */
+
+#ifndef __LPASS_H__
+#define __LPASS_H__
+
+#include <linux/clk.h>
+#include <linux/compiler.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#define LPASS_AHBIX_CLOCK_FREQUENCY 131072
+
+/* Both the CPU DAI and platform drivers will access this data */
+struct lpass_data {
+
+ /* AHB-I/X bus clocks inside the low-power audio subsystem (LPASS) */
+ struct clk *ahbix_clk;
+
+ /* MI2S system clock */
+ struct clk *mi2s_osr_clk;
+
+ /* MI2S bit clock (derived from system clock by a divider */
+ struct clk *mi2s_bit_clk;
+
+ /* low-power audio interface (LPAIF) registers */
+ void __iomem *lpaif;
+
+ /* regmap backed by the low-power audio interface (LPAIF) registers */
+ struct regmap *lpaif_map;
+
+ /* interrupts from the low-power audio interface (LPAIF) */
+ int lpaif_irq;
+};
+
+/* register the platform driver from the CPU DAI driver */
+int asoc_qcom_lpass_platform_register(struct platform_device *);
+
+#endif /* __LPASS_H__ */
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Patch V6 05/10] ASoC: qcom: Add LPASS CPU DAI driver
2015-02-25 6:39 [Patch V6 00/10] ASoC: QCOM: Add support for ipq806x SOC Kenneth Westfield
` (3 preceding siblings ...)
2015-02-25 6:39 ` [Patch V6 04/10] ASoC: qcom: add LPASS header files Kenneth Westfield
@ 2015-02-25 6:39 ` Kenneth Westfield
2015-02-25 6:39 ` [Patch V6 06/10] ASoC: qcom: Add LPASS platform driver Kenneth Westfield
` (4 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Kenneth Westfield @ 2015-02-25 6:39 UTC (permalink / raw)
To: Mark Brown, Takashi Iwai, Liam Girdwood, Banajit Goswami,
Patrick Lai, David Brown, Bryan Huntsman, Greg KH
Cc: Kenneth Westfield, ALSA Mailing List, MSM Mailing List,
Device Tree Mailing List, Kernel Mailing List
From: Kenneth Westfield <kwestfie@codeaurora.org>
Add the CPU DAI driver for the Qualcomm
Technologies low-power audio subsystem (LPASS).
Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org>
Acked-by: Banajit Goswami <bgoswami@codeaurora.org>
---
sound/soc/qcom/lpass-cpu.c | 508 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 508 insertions(+)
create mode 100644 sound/soc/qcom/lpass-cpu.c
diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c
new file mode 100644
index 0000000000000000000000000000000000000000..44ba7e34915e2cac91c51fecbcb8516805e99f56
--- /dev/null
+++ b/sound/soc/qcom/lpass-cpu.c
@@ -0,0 +1,508 @@
+/*
+ * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS
+ */
+
+#include <linux/clk.h>
+#include <linux/compiler.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/ioport.h>
+#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <linux/regmap.h>
+#include <sound/soc.h>
+#include <sound/soc-dai.h>
+#include "lpass-lpaif-ipq806x.h"
+#include "lpass.h"
+
+static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id,
+ unsigned int freq, int dir)
+{
+ struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
+ int ret;
+
+ ret = clk_set_rate(drvdata->mi2s_osr_clk, freq);
+ if (ret)
+ dev_err(dai->dev, "%s() error setting mi2s osrclk to %u: %d\n",
+ __func__, freq, ret);
+
+ return ret;
+}
+
+static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
+ int ret;
+
+ ret = clk_prepare_enable(drvdata->mi2s_osr_clk);
+ if (ret) {
+ dev_err(dai->dev, "%s() error in enabling mi2s osr clk: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(drvdata->mi2s_bit_clk);
+ if (ret) {
+ dev_err(dai->dev, "%s() error in enabling mi2s bit clk: %d\n",
+ __func__, ret);
+ clk_disable_unprepare(drvdata->mi2s_osr_clk);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
+
+ clk_disable_unprepare(drvdata->mi2s_bit_clk);
+ clk_disable_unprepare(drvdata->mi2s_osr_clk);
+}
+
+static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
+{
+ struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
+ snd_pcm_format_t format = params_format(params);
+ unsigned int channels = params_channels(params);
+ unsigned int rate = params_rate(params);
+ unsigned int regval;
+ int bitwidth, ret;
+
+ bitwidth = snd_pcm_format_width(format);
+ if (bitwidth < 0) {
+ dev_err(dai->dev, "%s() invalid bit width given: %d\n",
+ __func__, bitwidth);
+ return bitwidth;
+ }
+
+ regval = LPAIF_I2SCTL_LOOPBACK_DISABLE |
+ LPAIF_I2SCTL_WSSRC_INTERNAL;
+
+ switch (bitwidth) {
+ case 16:
+ regval |= LPAIF_I2SCTL_BITWIDTH_16;
+ break;
+ case 24:
+ regval |= LPAIF_I2SCTL_BITWIDTH_24;
+ break;
+ case 32:
+ regval |= LPAIF_I2SCTL_BITWIDTH_32;
+ break;
+ default:
+ dev_err(dai->dev, "%s() invalid bitwidth given: %d\n",
+ __func__, bitwidth);
+ return -EINVAL;
+ }
+
+ switch (channels) {
+ case 1:
+ regval |= LPAIF_I2SCTL_SPKMODE_SD0;
+ regval |= LPAIF_I2SCTL_SPKMONO_MONO;
+ break;
+ case 2:
+ regval |= LPAIF_I2SCTL_SPKMODE_SD0;
+ regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
+ break;
+ case 4:
+ regval |= LPAIF_I2SCTL_SPKMODE_QUAD01;
+ regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
+ break;
+ case 6:
+ regval |= LPAIF_I2SCTL_SPKMODE_6CH;
+ regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
+ break;
+ case 8:
+ regval |= LPAIF_I2SCTL_SPKMODE_8CH;
+ regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
+ break;
+ default:
+ dev_err(dai->dev, "%s() invalid channels given: %u\n",
+ __func__, channels);
+ return -EINVAL;
+ }
+
+ ret = regmap_write(drvdata->lpaif_map,
+ LPAIF_I2SCTL_REG(LPAIF_I2S_PORT_MI2S), regval);
+ if (ret) {
+ dev_err(dai->dev, "%s() error writing to i2sctl reg: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = clk_set_rate(drvdata->mi2s_bit_clk, rate * bitwidth * 2);
+ if (ret) {
+ dev_err(dai->dev, "%s() error setting mi2s bitclk to %u: %d\n",
+ __func__, rate * bitwidth * 2, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int lpass_cpu_daiops_hw_free(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
+ int ret;
+
+ ret = regmap_write(drvdata->lpaif_map,
+ LPAIF_I2SCTL_REG(LPAIF_I2S_PORT_MI2S), 0);
+ if (ret)
+ dev_err(dai->dev, "%s() error writing to i2sctl reg: %d\n",
+ __func__, ret);
+
+ return ret;
+}
+
+static int lpass_cpu_daiops_prepare(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
+ int ret;
+
+ ret = regmap_update_bits(drvdata->lpaif_map,
+ LPAIF_I2SCTL_REG(LPAIF_I2S_PORT_MI2S),
+ LPAIF_I2SCTL_SPKEN_MASK, LPAIF_I2SCTL_SPKEN_ENABLE);
+ if (ret)
+ dev_err(dai->dev, "%s() error writing to i2sctl reg: %d\n",
+ __func__, ret);
+
+ return ret;
+}
+
+static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream,
+ int cmd, struct snd_soc_dai *dai)
+{
+ struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
+ int ret;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ ret = regmap_update_bits(drvdata->lpaif_map,
+ LPAIF_I2SCTL_REG(LPAIF_I2S_PORT_MI2S),
+ LPAIF_I2SCTL_SPKEN_MASK,
+ LPAIF_I2SCTL_SPKEN_ENABLE);
+ if (ret)
+ dev_err(dai->dev, "%s() error writing to i2sctl reg: %d\n",
+ __func__, ret);
+ break;
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ ret = regmap_update_bits(drvdata->lpaif_map,
+ LPAIF_I2SCTL_REG(LPAIF_I2S_PORT_MI2S),
+ LPAIF_I2SCTL_SPKEN_MASK,
+ LPAIF_I2SCTL_SPKEN_DISABLE);
+ if (ret)
+ dev_err(dai->dev, "%s() error writing to i2sctl reg: %d\n",
+ __func__, ret);
+ break;
+ }
+
+ return ret;
+}
+
+static struct snd_soc_dai_ops lpass_cpu_dai_ops = {
+ .set_sysclk = lpass_cpu_daiops_set_sysclk,
+ .startup = lpass_cpu_daiops_startup,
+ .shutdown = lpass_cpu_daiops_shutdown,
+ .hw_params = lpass_cpu_daiops_hw_params,
+ .hw_free = lpass_cpu_daiops_hw_free,
+ .prepare = lpass_cpu_daiops_prepare,
+ .trigger = lpass_cpu_daiops_trigger,
+};
+
+static int lpass_cpu_dai_probe(struct snd_soc_dai *dai)
+{
+ struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
+ int ret;
+
+ /* ensure audio hardware is disabled */
+ ret = regmap_write(drvdata->lpaif_map,
+ LPAIF_I2SCTL_REG(LPAIF_I2S_PORT_MI2S), 0);
+ if (ret)
+ dev_err(dai->dev, "%s() error writing to i2sctl reg: %d\n",
+ __func__, ret);
+
+ return ret;
+}
+
+static struct snd_soc_dai_driver lpass_cpu_dai_driver = {
+ .playback = {
+ .stream_name = "lpass-cpu-playback",
+ .formats = SNDRV_PCM_FMTBIT_S16 |
+ SNDRV_PCM_FMTBIT_S24 |
+ SNDRV_PCM_FMTBIT_S32,
+ .rates = SNDRV_PCM_RATE_8000 |
+ SNDRV_PCM_RATE_16000 |
+ SNDRV_PCM_RATE_32000 |
+ SNDRV_PCM_RATE_48000 |
+ SNDRV_PCM_RATE_96000,
+ .rate_min = 8000,
+ .rate_max = 96000,
+ .channels_min = 1,
+ .channels_max = 8,
+ },
+ .probe = &lpass_cpu_dai_probe,
+ .ops = &lpass_cpu_dai_ops,
+};
+
+static const struct snd_soc_component_driver lpass_cpu_comp_driver = {
+ .name = "lpass-cpu",
+};
+
+static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg)
+{
+ int i;
+
+ for (i = 0; i < LPAIF_I2S_PORT_NUM; ++i)
+ if (reg == LPAIF_I2SCTL_REG(i))
+ return true;
+
+ for (i = 0; i < LPAIF_IRQ_PORT_NUM; ++i) {
+ if (reg == LPAIF_IRQEN_REG(i))
+ return true;
+ if (reg == LPAIF_IRQCLEAR_REG(i))
+ return true;
+ }
+
+ for (i = 0; i < LPAIF_RDMA_CHAN_NUM; ++i) {
+ if (reg == LPAIF_RDMACTL_REG(i))
+ return true;
+ if (reg == LPAIF_RDMABASE_REG(i))
+ return true;
+ if (reg == LPAIF_RDMABUFF_REG(i))
+ return true;
+ if (reg == LPAIF_RDMAPER_REG(i))
+ return true;
+ }
+
+ return false;
+}
+
+static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg)
+{
+ int i;
+
+ for (i = 0; i < LPAIF_I2S_PORT_NUM; ++i)
+ if (reg == LPAIF_I2SCTL_REG(i))
+ return true;
+
+ for (i = 0; i < LPAIF_IRQ_PORT_NUM; ++i) {
+ if (reg == LPAIF_IRQEN_REG(i))
+ return true;
+ if (reg == LPAIF_IRQSTAT_REG(i))
+ return true;
+ }
+
+ for (i = 0; i < LPAIF_RDMA_CHAN_NUM; ++i) {
+ if (reg == LPAIF_RDMACTL_REG(i))
+ return true;
+ if (reg == LPAIF_RDMABASE_REG(i))
+ return true;
+ if (reg == LPAIF_RDMABUFF_REG(i))
+ return true;
+ if (reg == LPAIF_RDMACURR_REG(i))
+ return true;
+ if (reg == LPAIF_RDMAPER_REG(i))
+ return true;
+ }
+
+ return false;
+}
+
+static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg)
+{
+ int i;
+
+ for (i = 0; i < LPAIF_IRQ_PORT_NUM; ++i)
+ if (reg == LPAIF_IRQSTAT_REG(i))
+ return true;
+
+ for (i = 0; i < LPAIF_RDMA_CHAN_NUM; ++i)
+ if (reg == LPAIF_RDMACURR_REG(i))
+ return true;
+
+ return false;
+}
+
+static const struct regmap_config lpass_cpu_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = LPAIF_RDMAPER_REG(LPAIF_RDMA_CHAN_MAX),
+ .writeable_reg = lpass_cpu_regmap_writeable,
+ .readable_reg = lpass_cpu_regmap_readable,
+ .volatile_reg = lpass_cpu_regmap_volatile,
+ .cache_type = REGCACHE_FLAT,
+};
+
+static int lpass_cpu_parse_of(struct device *dev)
+{
+ struct device_node *dsp_of_node;
+
+ dsp_of_node = of_get_child_by_name(dev->of_node, "qcom,adsp");
+ if (!dsp_of_node) {
+ dev_err(dev, "%s() error getting qcom,adsp sub-node\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ if (of_device_is_available(dsp_of_node)) {
+ dev_err(dev, "%s() DSP exists and holds audio resources\n",
+ __func__);
+ return -EBUSY;
+ }
+
+ return 0;
+}
+
+static int lpass_cpu_platform_probe(struct platform_device *pdev)
+{
+ struct lpass_data *drvdata;
+ struct resource *res;
+ int ret;
+
+ drvdata = devm_kzalloc(&pdev->dev, sizeof(struct lpass_data),
+ GFP_KERNEL);
+ if (!drvdata)
+ return -ENOMEM;
+ platform_set_drvdata(pdev, drvdata);
+
+ ret = lpass_cpu_parse_of(&pdev->dev);
+ if (ret) {
+ dev_err(&pdev->dev, "%s() error getting DT node info: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-lpaif");
+ if (!res) {
+ dev_err(&pdev->dev, "%s() error getting resource\n", __func__);
+ return -ENODEV;
+ }
+
+ drvdata->lpaif = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR((void const __force *)drvdata->lpaif)) {
+ dev_err(&pdev->dev, "%s() error mapping reg resource: %ld\n",
+ __func__,
+ PTR_ERR((void const __force *)drvdata->lpaif));
+ return PTR_ERR((void const __force *)drvdata->lpaif);
+ }
+
+ drvdata->lpaif_map = devm_regmap_init_mmio(&pdev->dev, drvdata->lpaif,
+ &lpass_cpu_regmap_config);
+ if (IS_ERR(drvdata->lpaif_map)) {
+ dev_err(&pdev->dev, "%s() error initializing regmap: %ld\n",
+ __func__, PTR_ERR(drvdata->lpaif_map));
+ return PTR_ERR(drvdata->lpaif_map);
+ }
+
+ drvdata->mi2s_osr_clk = devm_clk_get(&pdev->dev, "mi2s-osr-clk");
+ if (IS_ERR(drvdata->mi2s_osr_clk)) {
+ dev_err(&pdev->dev, "%s() error getting mi2s-osr-clk: %ld\n",
+ __func__, PTR_ERR(drvdata->mi2s_osr_clk));
+ return PTR_ERR(drvdata->mi2s_osr_clk);
+ }
+
+ drvdata->mi2s_bit_clk = devm_clk_get(&pdev->dev, "mi2s-bit-clk");
+ if (IS_ERR(drvdata->mi2s_bit_clk)) {
+ dev_err(&pdev->dev, "%s() error getting mi2s-bit-clk: %ld\n",
+ __func__, PTR_ERR(drvdata->mi2s_bit_clk));
+ return PTR_ERR(drvdata->mi2s_bit_clk);
+ }
+
+ drvdata->ahbix_clk = devm_clk_get(&pdev->dev, "ahbix-clk");
+ if (IS_ERR(drvdata->ahbix_clk)) {
+ dev_err(&pdev->dev, "%s() error getting ahbix-clk: %ld\n",
+ __func__, PTR_ERR(drvdata->ahbix_clk));
+ return PTR_ERR(drvdata->ahbix_clk);
+ }
+
+ ret = clk_set_rate(drvdata->ahbix_clk, LPASS_AHBIX_CLOCK_FREQUENCY);
+ if (ret) {
+ dev_err(&pdev->dev, "%s() error setting rate on ahbix_clk: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(drvdata->ahbix_clk);
+ if (ret) {
+ dev_err(&pdev->dev, "%s() Error enabling ahbix_clk: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = devm_snd_soc_register_component(&pdev->dev,
+ &lpass_cpu_comp_driver, &lpass_cpu_dai_driver, 1);
+ if (ret) {
+ dev_err(&pdev->dev, "%s() error registering cpu driver: %d\n",
+ __func__, ret);
+ goto err_clk;
+ }
+
+ ret = asoc_qcom_lpass_platform_register(pdev);
+ if (ret) {
+ dev_err(&pdev->dev, "%s() error registering platform driver: %d\n",
+ __func__, ret);
+ goto err_clk;
+ }
+
+ return 0;
+
+err_clk:
+ clk_disable_unprepare(drvdata->ahbix_clk);
+ return ret;
+}
+
+static int lpass_cpu_platform_remove(struct platform_device *pdev)
+{
+ struct lpass_data *drvdata = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(drvdata->ahbix_clk);
+
+ return 0;
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id lpass_cpu_device_id[] = {
+ { .compatible = "qcom,lpass-cpu" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, lpass_cpu_device_id);
+#endif
+
+static struct platform_driver lpass_cpu_platform_driver = {
+ .driver = {
+ .name = "lpass-cpu",
+ .of_match_table = of_match_ptr(lpass_cpu_device_id),
+ },
+ .probe = lpass_cpu_platform_probe,
+ .remove = lpass_cpu_platform_remove,
+};
+module_platform_driver(lpass_cpu_platform_driver);
+
+MODULE_DESCRIPTION("QTi LPASS CPU Driver");
+MODULE_LICENSE("GPL v2");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Patch V6 06/10] ASoC: qcom: Add LPASS platform driver
2015-02-25 6:39 [Patch V6 00/10] ASoC: QCOM: Add support for ipq806x SOC Kenneth Westfield
` (4 preceding siblings ...)
2015-02-25 6:39 ` [Patch V6 05/10] ASoC: qcom: Add LPASS CPU DAI driver Kenneth Westfield
@ 2015-02-25 6:39 ` Kenneth Westfield
2015-02-25 6:39 ` [Patch V6 07/10] ASoC: qcom: Add Storm machine driver Kenneth Westfield
` (3 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Kenneth Westfield @ 2015-02-25 6:39 UTC (permalink / raw)
To: Mark Brown, Takashi Iwai, Liam Girdwood, Banajit Goswami,
Patrick Lai, David Brown, Bryan Huntsman, Greg KH
Cc: Kenneth Westfield, ALSA Mailing List, MSM Mailing List,
Device Tree Mailing List, Kernel Mailing List
From: Kenneth Westfield <kwestfie@codeaurora.org>
Add platform driver for the Qualcomm Technologies
low-power audio subsystem (LPASS) ports.
Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org>
Acked-by: Banajit Goswami <bgoswami@codeaurora.org>
---
sound/soc/qcom/lpass-platform.c | 526 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 526 insertions(+)
create mode 100644 sound/soc/qcom/lpass-platform.c
diff --git a/sound/soc/qcom/lpass-platform.c b/sound/soc/qcom/lpass-platform.c
new file mode 100644
index 0000000000000000000000000000000000000000..2fa6280dfb234b213904ad73dfad91c7f575538c
--- /dev/null
+++ b/sound/soc/qcom/lpass-platform.c
@@ -0,0 +1,526 @@
+/*
+ * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * lpass-platform.c -- ALSA SoC platform driver for QTi LPASS
+ */
+
+#include <linux/compiler.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/export.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <sound/memalloc.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <linux/regmap.h>
+#include <sound/soc.h>
+#include "lpass-lpaif-ipq806x.h"
+#include "lpass.h"
+
+#define LPASS_PLATFORM_BUFFER_SIZE (16 * 1024)
+#define LPASS_PLATFORM_PERIODS 2
+
+static struct snd_pcm_hardware lpass_platform_pcm_hardware = {
+ .info = SNDRV_PCM_INFO_MMAP |
+ SNDRV_PCM_INFO_MMAP_VALID |
+ SNDRV_PCM_INFO_INTERLEAVED |
+ SNDRV_PCM_INFO_PAUSE |
+ SNDRV_PCM_INFO_RESUME,
+ .formats = SNDRV_PCM_FMTBIT_S16 |
+ SNDRV_PCM_FMTBIT_S24 |
+ SNDRV_PCM_FMTBIT_S32,
+ .rates = SNDRV_PCM_RATE_8000_192000,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ .channels_min = 1,
+ .channels_max = 8,
+ .buffer_bytes_max = LPASS_PLATFORM_BUFFER_SIZE,
+ .period_bytes_max = LPASS_PLATFORM_BUFFER_SIZE /
+ LPASS_PLATFORM_PERIODS,
+ .period_bytes_min = LPASS_PLATFORM_BUFFER_SIZE /
+ LPASS_PLATFORM_PERIODS,
+ .periods_min = LPASS_PLATFORM_PERIODS,
+ .periods_max = LPASS_PLATFORM_PERIODS,
+ .fifo_size = 0,
+};
+
+static int lpass_platform_pcmops_open(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
+ int ret;
+
+ snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware);
+
+ runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max;
+
+ ret = snd_pcm_hw_constraint_integer(runtime,
+ SNDRV_PCM_HW_PARAM_PERIODS);
+ if (ret < 0) {
+ dev_err(soc_runtime->dev, "%s() setting constraints failed: %d\n",
+ __func__, ret);
+ return -EINVAL;
+ }
+
+ snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
+
+ return 0;
+}
+
+static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
+ struct lpass_data *drvdata =
+ snd_soc_platform_get_drvdata(soc_runtime->platform);
+ snd_pcm_format_t format = params_format(params);
+ unsigned int channels = params_channels(params);
+ unsigned int regval;
+ int bitwidth;
+ int ret;
+
+ bitwidth = snd_pcm_format_width(format);
+ if (bitwidth < 0) {
+ dev_err(soc_runtime->dev, "%s() invalid bit width given: %d\n",
+ __func__, bitwidth);
+ return bitwidth;
+ }
+
+ regval = LPAIF_RDMACTL_BURSTEN_INCR4 |
+ LPAIF_RDMACTL_AUDINTF_MI2S |
+ LPAIF_RDMACTL_FIFOWM_8;
+
+ switch (bitwidth) {
+ case 16:
+ switch (channels) {
+ case 1:
+ case 2:
+ regval |= LPAIF_RDMACTL_WPSCNT_ONE;
+ break;
+ case 4:
+ regval |= LPAIF_RDMACTL_WPSCNT_TWO;
+ break;
+ case 6:
+ regval |= LPAIF_RDMACTL_WPSCNT_THREE;
+ break;
+ case 8:
+ regval |= LPAIF_RDMACTL_WPSCNT_FOUR;
+ break;
+ default:
+ dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
+ __func__, bitwidth, channels);
+ return -EINVAL;
+ }
+ break;
+ case 24:
+ case 32:
+ switch (channels) {
+ case 1:
+ regval |= LPAIF_RDMACTL_WPSCNT_ONE;
+ break;
+ case 2:
+ regval |= LPAIF_RDMACTL_WPSCNT_TWO;
+ break;
+ case 4:
+ regval |= LPAIF_RDMACTL_WPSCNT_FOUR;
+ break;
+ case 6:
+ regval |= LPAIF_RDMACTL_WPSCNT_SIX;
+ break;
+ case 8:
+ regval |= LPAIF_RDMACTL_WPSCNT_EIGHT;
+ break;
+ default:
+ dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
+ __func__, bitwidth, channels);
+ return -EINVAL;
+ }
+ break;
+ default:
+ dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
+ __func__, bitwidth, channels);
+ return -EINVAL;
+ }
+
+ ret = regmap_write(drvdata->lpaif_map,
+ LPAIF_RDMACTL_REG(LPAIF_RDMA_CHAN_MI2S), regval);
+ if (ret) {
+ dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int lpass_platform_pcmops_hw_free(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
+ struct lpass_data *drvdata =
+ snd_soc_platform_get_drvdata(soc_runtime->platform);
+ int ret;
+
+ ret = regmap_write(drvdata->lpaif_map,
+ LPAIF_RDMACTL_REG(LPAIF_RDMA_CHAN_MI2S), 0);
+ if (ret)
+ dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
+ __func__, ret);
+
+ return ret;
+}
+
+static int lpass_platform_pcmops_prepare(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
+ struct lpass_data *drvdata =
+ snd_soc_platform_get_drvdata(soc_runtime->platform);
+ int ret;
+
+ ret = regmap_write(drvdata->lpaif_map,
+ LPAIF_RDMABASE_REG(LPAIF_RDMA_CHAN_MI2S),
+ runtime->dma_addr);
+ if (ret) {
+ dev_err(soc_runtime->dev, "%s() error writing to rdmabase reg: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = regmap_write(drvdata->lpaif_map,
+ LPAIF_RDMABUFF_REG(LPAIF_RDMA_CHAN_MI2S),
+ (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1);
+ if (ret) {
+ dev_err(soc_runtime->dev, "%s() error writing to rdmabuff reg: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = regmap_write(drvdata->lpaif_map,
+ LPAIF_RDMAPER_REG(LPAIF_RDMA_CHAN_MI2S),
+ (snd_pcm_lib_period_bytes(substream) >> 2) - 1);
+ if (ret) {
+ dev_err(soc_runtime->dev, "%s() error writing to rdmaper reg: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = regmap_update_bits(drvdata->lpaif_map,
+ LPAIF_RDMACTL_REG(LPAIF_RDMA_CHAN_MI2S),
+ LPAIF_RDMACTL_ENABLE_MASK, LPAIF_RDMACTL_ENABLE_ON);
+ if (ret) {
+ dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int lpass_platform_pcmops_trigger(struct snd_pcm_substream *substream,
+ int cmd)
+{
+ struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
+ struct lpass_data *drvdata =
+ snd_soc_platform_get_drvdata(soc_runtime->platform);
+ int ret;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ /* clear status before enabling interrupts */
+ ret = regmap_write(drvdata->lpaif_map,
+ LPAIF_IRQCLEAR_REG(LPAIF_IRQ_PORT_HOST),
+ LPAIF_IRQ_ALL(LPAIF_RDMA_CHAN_MI2S));
+ if (ret) {
+ dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = regmap_update_bits(drvdata->lpaif_map,
+ LPAIF_IRQEN_REG(LPAIF_IRQ_PORT_HOST),
+ LPAIF_IRQ_ALL(LPAIF_RDMA_CHAN_MI2S),
+ LPAIF_IRQ_ALL(LPAIF_RDMA_CHAN_MI2S));
+ if (ret) {
+ dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = regmap_update_bits(drvdata->lpaif_map,
+ LPAIF_RDMACTL_REG(LPAIF_RDMA_CHAN_MI2S),
+ LPAIF_RDMACTL_ENABLE_MASK,
+ LPAIF_RDMACTL_ENABLE_ON);
+ if (ret) {
+ dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ break;
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ ret = regmap_update_bits(drvdata->lpaif_map,
+ LPAIF_RDMACTL_REG(LPAIF_RDMA_CHAN_MI2S),
+ LPAIF_RDMACTL_ENABLE_MASK,
+ LPAIF_RDMACTL_ENABLE_OFF);
+ if (ret) {
+ dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = regmap_update_bits(drvdata->lpaif_map,
+ LPAIF_IRQEN_REG(LPAIF_IRQ_PORT_HOST),
+ LPAIF_IRQ_ALL(LPAIF_RDMA_CHAN_MI2S), 0);
+ if (ret) {
+ dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ break;
+ }
+
+ return 0;
+}
+
+static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
+ struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
+ struct lpass_data *drvdata =
+ snd_soc_platform_get_drvdata(soc_runtime->platform);
+ unsigned int base_addr, curr_addr;
+ int ret;
+
+ ret = regmap_read(drvdata->lpaif_map,
+ LPAIF_RDMABASE_REG(LPAIF_RDMA_CHAN_MI2S), &base_addr);
+ if (ret) {
+ dev_err(soc_runtime->dev, "%s() error reading from rdmabase reg: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = regmap_read(drvdata->lpaif_map,
+ LPAIF_RDMACURR_REG(LPAIF_RDMA_CHAN_MI2S), &curr_addr);
+ if (ret) {
+ dev_err(soc_runtime->dev, "%s() error reading from rdmacurr reg: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ return bytes_to_frames(substream->runtime, curr_addr - base_addr);
+}
+
+static int lpass_platform_pcmops_mmap(struct snd_pcm_substream *substream,
+ struct vm_area_struct *vma)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+
+ return dma_mmap_coherent(substream->pcm->card->dev, vma,
+ runtime->dma_area, runtime->dma_addr,
+ runtime->dma_bytes);
+}
+
+static struct snd_pcm_ops lpass_platform_pcm_ops = {
+ .open = lpass_platform_pcmops_open,
+ .ioctl = snd_pcm_lib_ioctl,
+ .hw_params = lpass_platform_pcmops_hw_params,
+ .hw_free = lpass_platform_pcmops_hw_free,
+ .prepare = lpass_platform_pcmops_prepare,
+ .trigger = lpass_platform_pcmops_trigger,
+ .pointer = lpass_platform_pcmops_pointer,
+ .mmap = lpass_platform_pcmops_mmap,
+};
+
+static irqreturn_t lpass_platform_lpaif_irq(int irq, void *data)
+{
+ struct snd_pcm_substream *substream = data;
+ struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
+ struct lpass_data *drvdata =
+ snd_soc_platform_get_drvdata(soc_runtime->platform);
+ unsigned int interrupts;
+ irqreturn_t ret = IRQ_NONE;
+ int rv;
+
+ rv = regmap_read(drvdata->lpaif_map,
+ LPAIF_IRQSTAT_REG(LPAIF_IRQ_PORT_HOST), &interrupts);
+ if (rv) {
+ dev_err(soc_runtime->dev, "%s() error reading from irqstat reg: %d\n",
+ __func__, rv);
+ return IRQ_NONE;
+ }
+ interrupts &= LPAIF_IRQ_ALL(LPAIF_RDMA_CHAN_MI2S);
+
+ if (interrupts & LPAIF_IRQ_PER(LPAIF_RDMA_CHAN_MI2S)) {
+ rv = regmap_write(drvdata->lpaif_map,
+ LPAIF_IRQCLEAR_REG(LPAIF_IRQ_PORT_HOST),
+ LPAIF_IRQ_PER(LPAIF_RDMA_CHAN_MI2S));
+ if (rv) {
+ dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
+ __func__, rv);
+ return IRQ_NONE;
+ }
+ snd_pcm_period_elapsed(substream);
+ ret = IRQ_HANDLED;
+ }
+
+ if (interrupts & LPAIF_IRQ_XRUN(LPAIF_RDMA_CHAN_MI2S)) {
+ rv = regmap_write(drvdata->lpaif_map,
+ LPAIF_IRQCLEAR_REG(LPAIF_IRQ_PORT_HOST),
+ LPAIF_IRQ_XRUN(LPAIF_RDMA_CHAN_MI2S));
+ if (rv) {
+ dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
+ __func__, rv);
+ return IRQ_NONE;
+ }
+ dev_warn(soc_runtime->dev, "%s() xrun warning\n", __func__);
+ snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
+ ret = IRQ_HANDLED;
+ }
+
+ if (interrupts & LPAIF_IRQ_ERR(LPAIF_RDMA_CHAN_MI2S)) {
+ rv = regmap_write(drvdata->lpaif_map,
+ LPAIF_IRQCLEAR_REG(LPAIF_IRQ_PORT_HOST),
+ LPAIF_IRQ_ERR(LPAIF_RDMA_CHAN_MI2S));
+ if (rv) {
+ dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
+ __func__, rv);
+ return IRQ_NONE;
+ }
+ dev_err(soc_runtime->dev, "%s() bus access error\n", __func__);
+ snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
+ ret = IRQ_HANDLED;
+ }
+
+ return ret;
+}
+
+static int lpass_platform_alloc_buffer(struct snd_pcm_substream *substream,
+ struct snd_soc_pcm_runtime *soc_runtime)
+{
+ struct snd_dma_buffer *buf = &substream->dma_buffer;
+ size_t size = lpass_platform_pcm_hardware.buffer_bytes_max;
+
+ buf->dev.type = SNDRV_DMA_TYPE_DEV;
+ buf->dev.dev = soc_runtime->dev;
+ buf->private_data = NULL;
+ buf->area = dma_alloc_coherent(soc_runtime->dev, size, &buf->addr,
+ GFP_KERNEL);
+ if (!buf->area) {
+ dev_err(soc_runtime->dev, "%s: Could not allocate DMA buffer\n",
+ __func__);
+ return -ENOMEM;
+ }
+ buf->bytes = size;
+
+ return 0;
+}
+
+static void lpass_platform_free_buffer(struct snd_pcm_substream *substream,
+ struct snd_soc_pcm_runtime *soc_runtime)
+{
+ struct snd_dma_buffer *buf = &substream->dma_buffer;
+
+ if (buf->area) {
+ dma_free_coherent(soc_runtime->dev, buf->bytes, buf->area,
+ buf->addr);
+ }
+ buf->area = NULL;
+}
+
+static int lpass_platform_pcm_new(struct snd_soc_pcm_runtime *soc_runtime)
+{
+ struct snd_pcm *pcm = soc_runtime->pcm;
+ struct snd_pcm_substream *substream =
+ pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
+ struct lpass_data *drvdata =
+ snd_soc_platform_get_drvdata(soc_runtime->platform);
+ int ret;
+
+ soc_runtime->dev->coherent_dma_mask = DMA_BIT_MASK(32);
+ soc_runtime->dev->dma_mask = &soc_runtime->dev->coherent_dma_mask;
+
+ ret = lpass_platform_alloc_buffer(substream, soc_runtime);
+ if (ret)
+ return ret;
+
+ ret = devm_request_irq(soc_runtime->dev, drvdata->lpaif_irq,
+ lpass_platform_lpaif_irq, IRQF_TRIGGER_RISING,
+ "lpass-irq-lpaif", substream);
+ if (ret) {
+ dev_err(soc_runtime->dev, "%s() irq request failed: %d\n",
+ __func__, ret);
+ goto err_buf;
+ }
+
+ /* ensure audio hardware is disabled */
+ ret = regmap_write(drvdata->lpaif_map,
+ LPAIF_IRQEN_REG(LPAIF_IRQ_PORT_HOST), 0);
+ if (ret) {
+ dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ ret = regmap_write(drvdata->lpaif_map,
+ LPAIF_RDMACTL_REG(LPAIF_RDMA_CHAN_MI2S), 0);
+ if (ret) {
+ dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ return 0;
+
+err_buf:
+ lpass_platform_free_buffer(substream, soc_runtime);
+ return ret;
+}
+
+static void lpass_platform_pcm_free(struct snd_pcm *pcm)
+{
+ struct snd_pcm_substream *substream =
+ pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
+ struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
+
+ lpass_platform_free_buffer(substream, soc_runtime);
+}
+
+static struct snd_soc_platform_driver lpass_platform_driver = {
+ .pcm_new = lpass_platform_pcm_new,
+ .pcm_free = lpass_platform_pcm_free,
+ .ops = &lpass_platform_pcm_ops,
+};
+
+int asoc_qcom_lpass_platform_register(struct platform_device *pdev)
+{
+ struct lpass_data *drvdata = platform_get_drvdata(pdev);
+
+ drvdata->lpaif_irq = platform_get_irq_byname(pdev, "lpass-irq-lpaif");
+ if (drvdata->lpaif_irq < 0) {
+ dev_err(&pdev->dev, "%s() error getting irq handle: %d\n",
+ __func__, drvdata->lpaif_irq);
+ return -ENODEV;
+ }
+
+ return devm_snd_soc_register_platform(&pdev->dev,
+ &lpass_platform_driver);
+}
+EXPORT_SYMBOL_GPL(asoc_qcom_lpass_platform_register);
+
+MODULE_DESCRIPTION("QTi LPASS Platform Driver");
+MODULE_LICENSE("GPL v2");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Patch V6 07/10] ASoC: qcom: Add Storm machine driver
2015-02-25 6:39 [Patch V6 00/10] ASoC: QCOM: Add support for ipq806x SOC Kenneth Westfield
` (5 preceding siblings ...)
2015-02-25 6:39 ` [Patch V6 06/10] ASoC: qcom: Add LPASS platform driver Kenneth Westfield
@ 2015-02-25 6:39 ` Kenneth Westfield
2015-02-25 6:39 ` [Patch V6 08/10] ASoC: qcom: Add ability to build QCOM drivers Kenneth Westfield
` (2 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Kenneth Westfield @ 2015-02-25 6:39 UTC (permalink / raw)
To: Mark Brown, Takashi Iwai, Liam Girdwood, Banajit Goswami,
Patrick Lai, David Brown, Bryan Huntsman, Greg KH
Cc: Kenneth Westfield, ALSA Mailing List, MSM Mailing List,
Device Tree Mailing List, Kernel Mailing List
From: Kenneth Westfield <kwestfie@codeaurora.org>
Add machine driver for the Storm board with the
IPQ806X SOC connected to the MAX98357A DAC.
Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org>
Acked-by: Banajit Goswami <bgoswami@codeaurora.org>
---
sound/soc/qcom/storm.c | 162 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 162 insertions(+)
create mode 100644 sound/soc/qcom/storm.c
diff --git a/sound/soc/qcom/storm.c b/sound/soc/qcom/storm.c
new file mode 100644
index 0000000000000000000000000000000000000000..5b981af4aa38a6a3bba926b3dd877239eefe8cb0
--- /dev/null
+++ b/sound/soc/qcom/storm.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * storm.c -- ALSA SoC machine driver for QTi ipq806x-based Storm board
+ */
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#define STORM_SYSCLK_MULT 4
+
+static int storm_ops_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
+ struct snd_soc_card *card = soc_runtime->card;
+ snd_pcm_format_t format = params_format(params);
+ unsigned int rate = params_rate(params);
+ unsigned int sysclk_freq;
+ int bitwidth, ret;
+
+ bitwidth = snd_pcm_format_width(format);
+ if (bitwidth < 0) {
+ dev_err(card->dev, "%s() invalid bit width given: %d\n",
+ __func__, bitwidth);
+ return bitwidth;
+ }
+
+ /*
+ * as the CPU DAI is the I2S bus master and no system clock is needed by
+ * the MAX98357a DAC, simply set the system clock to be a constant
+ * multiple of the bit clock for the clock divider
+ */
+ sysclk_freq = rate * bitwidth * 2 * STORM_SYSCLK_MULT;
+
+ ret = snd_soc_dai_set_sysclk(soc_runtime->cpu_dai, 0, sysclk_freq, 0);
+ if (ret) {
+ dev_err(card->dev, "%s() error setting sysclk to %u: %d\n",
+ __func__, sysclk_freq, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static struct snd_soc_ops storm_soc_ops = {
+ .hw_params = storm_ops_hw_params,
+};
+
+static struct snd_soc_dai_link storm_dai_link = {
+ .name = "Primary",
+ .stream_name = "Primary",
+ .codec_dai_name = "HiFi",
+ .ops = &storm_soc_ops,
+};
+
+static struct snd_soc_card storm_soc_card = {
+ .name = "ipq806x-storm",
+ .dev = NULL,
+};
+
+static int storm_parse_of(struct snd_soc_card *card)
+{
+ struct snd_soc_dai_link *dai_link = card->dai_link;
+ struct device_node *np = card->dev->of_node;
+
+ dai_link->cpu_of_node = of_parse_phandle(np, "cpu", 0);
+ if (!dai_link->cpu_of_node) {
+ dev_err(card->dev, "%s() error getting cpu phandle\n",
+ __func__);
+ return -EINVAL;
+ }
+ dai_link->platform_of_node = dai_link->cpu_of_node;
+
+ dai_link->codec_of_node = of_parse_phandle(np, "codec", 0);
+ if (!dai_link->codec_of_node) {
+ dev_err(card->dev, "%s() error getting codec phandle\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int storm_platform_probe(struct platform_device *pdev)
+{
+ struct snd_soc_card *card = &storm_soc_card;
+ int ret;
+
+ if (card->dev) {
+ dev_err(&pdev->dev, "%s() error, existing soundcard\n",
+ __func__);
+ return -ENODEV;
+ }
+ card->dev = &pdev->dev;
+ platform_set_drvdata(pdev, card);
+
+ ret = snd_soc_of_parse_card_name(card, "qcom,model");
+ if (ret) {
+ dev_err(&pdev->dev, "%s() error parsing card name: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ card->dai_link = &storm_dai_link;
+ card->num_links = 1;
+
+ ret = storm_parse_of(card);
+ if (ret) {
+ dev_err(&pdev->dev, "%s() error resolving dai links: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+ if (ret == -EPROBE_DEFER) {
+ card->dev = NULL;
+ return ret;
+ } else if (ret) {
+ dev_err(&pdev->dev, "%s() error registering soundcard: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id storm_device_id[] = {
+ { .compatible = "google,storm" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, storm_device_id);
+#endif
+
+static struct platform_driver storm_platform_driver = {
+ .driver = {
+ .name = "storm-audio",
+ .of_match_table =
+ of_match_ptr(storm_device_id),
+ },
+ .probe = storm_platform_probe,
+};
+module_platform_driver(storm_platform_driver);
+
+MODULE_DESCRIPTION("QTi IPQ806x-based Storm Machine Driver");
+MODULE_LICENSE("GPL v2");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Patch V6 08/10] ASoC: qcom: Add ability to build QCOM drivers
2015-02-25 6:39 [Patch V6 00/10] ASoC: QCOM: Add support for ipq806x SOC Kenneth Westfield
` (6 preceding siblings ...)
2015-02-25 6:39 ` [Patch V6 07/10] ASoC: qcom: Add Storm machine driver Kenneth Westfield
@ 2015-02-25 6:39 ` Kenneth Westfield
2015-02-25 8:40 ` Srinivas Kandagatla
2015-02-25 6:39 ` [Patch V6 09/10] ASoC: Allow for building " Kenneth Westfield
2015-02-25 6:39 ` [Patch V6 10/10] ARM: dts: Model IPQ LPASS audio hardware Kenneth Westfield
9 siblings, 1 reply; 12+ messages in thread
From: Kenneth Westfield @ 2015-02-25 6:39 UTC (permalink / raw)
To: Mark Brown, Takashi Iwai, Liam Girdwood, Banajit Goswami,
Patrick Lai, David Brown, Bryan Huntsman, Greg KH
Cc: Kenneth Westfield, ALSA Mailing List, MSM Mailing List,
Device Tree Mailing List, Kernel Mailing List
From: Kenneth Westfield <kwestfie@codeaurora.org>
Define the LPASS platform driver, the LPASS
CPU DAI driver and the Storm machine driver
configurations, and how to build them.
Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org>
Acked-by: Banajit Goswami <bgoswami@codeaurora.org>
---
sound/soc/qcom/Kconfig | 23 +++++++++++++++++++++++
sound/soc/qcom/Makefile | 11 +++++++++++
2 files changed, 34 insertions(+)
create mode 100644 sound/soc/qcom/Kconfig
create mode 100644 sound/soc/qcom/Makefile
diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..90e686be613a5ef7689582a9d085835d2fe12678
--- /dev/null
+++ b/sound/soc/qcom/Kconfig
@@ -0,0 +1,23 @@
+config SND_SOC_QCOM
+ tristate "ASoC support for QCOM platforms"
+ help
+ Say Y or M if you want to add support to use audio devices
+ in Qualcomm Technologies SOC-based platforms.
+
+config SND_SOC_LPASS_CPU
+ tristate
+ depends on SND_SOC_QCOM
+
+config SND_SOC_LPASS_PLATFORM
+ tristate
+ depends on SND_SOC_QCOM
+
+config SND_SOC_STORM
+ tristate "ASoC I2S support for Storm boards"
+ depends on (ARCH_QCOM && SND_SOC_QCOM) || COMPILE_TEST
+ select SND_SOC_LPASS_CPU
+ select SND_SOC_LPASS_PLATFORM
+ select SND_SOC_MAX98357A
+ help
+ Say Y or M if you want add support for SoC audio on the
+ Qualcomm Technologies IPQ806X-based Storm board.
diff --git a/sound/soc/qcom/Makefile b/sound/soc/qcom/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..c5ce96c761c47b3a1b98e27d863fe0b5b9bc019e
--- /dev/null
+++ b/sound/soc/qcom/Makefile
@@ -0,0 +1,11 @@
+# Platform
+snd-soc-lpass-cpu-objs := lpass-cpu.o
+snd-soc-lpass-platform-objs := lpass-platform.o
+
+obj-$(CONFIG_SND_SOC_LPASS_CPU) += snd-soc-lpass-cpu.o
+obj-$(CONFIG_SND_SOC_LPASS_PLATFORM) += snd-soc-lpass-platform.o
+
+# Machine
+snd-soc-storm-objs := storm.o
+
+obj-$(CONFIG_SND_SOC_STORM) += snd-soc-storm.o
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [Patch V6 08/10] ASoC: qcom: Add ability to build QCOM drivers
2015-02-25 6:39 ` [Patch V6 08/10] ASoC: qcom: Add ability to build QCOM drivers Kenneth Westfield
@ 2015-02-25 8:40 ` Srinivas Kandagatla
0 siblings, 0 replies; 12+ messages in thread
From: Srinivas Kandagatla @ 2015-02-25 8:40 UTC (permalink / raw)
To: Kenneth Westfield, Mark Brown, Takashi Iwai, Liam Girdwood,
Banajit Goswami, Patrick Lai, David Brown, Bryan Huntsman,
Greg KH
Cc: ALSA Mailing List, MSM Mailing List, Device Tree Mailing List,
Kernel Mailing List
On 25/02/15 06:39, Kenneth Westfield wrote:
> From: Kenneth Westfield <kwestfie@codeaurora.org>
>
> Define the LPASS platform driver, the LPASS
> CPU DAI driver and the Storm machine driver
> configurations, and how to build them.
>
> Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org>
> Acked-by: Banajit Goswami <bgoswami@codeaurora.org>
> ---
> sound/soc/qcom/Kconfig | 23 +++++++++++++++++++++++
> sound/soc/qcom/Makefile | 11 +++++++++++
> 2 files changed, 34 insertions(+)
> create mode 100644 sound/soc/qcom/Kconfig
> create mode 100644 sound/soc/qcom/Makefile
>
> diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig
> new file mode 100644
> index 0000000000000000000000000000000000000000..90e686be613a5ef7689582a9d085835d2fe12678
> --- /dev/null
> +++ b/sound/soc/qcom/Kconfig
> @@ -0,0 +1,23 @@
> +config SND_SOC_QCOM
> + tristate "ASoC support for QCOM platforms"
> + help
> + Say Y or M if you want to add support to use audio devices
> + in Qualcomm Technologies SOC-based platforms.
> +
> +config SND_SOC_LPASS_CPU
> + tristate
> + depends on SND_SOC_QCOM
> +
> +config SND_SOC_LPASS_PLATFORM
> + tristate
> + depends on SND_SOC_QCOM
I think both of the above configs should select REGMAP_MMIO.
> +
> +config SND_SOC_STORM
> + tristate "ASoC I2S support for Storm boards"
> + depends on (ARCH_QCOM && SND_SOC_QCOM) || COMPILE_TEST
> + select SND_SOC_LPASS_CPU
> + select SND_SOC_LPASS_PLATFORM
> + select SND_SOC_MAX98357A
> + help
> + Say Y or M if you want add support for SoC audio on the
> + Qualcomm Technologies IPQ806X-based Storm board.
> diff --git a/sound/soc/qcom/Makefile b/sound/soc/qcom/Makefile
> new file mode 100644
> index 0000000000000000000000000000000000000000..c5ce96c761c47b3a1b98e27d863fe0b5b9bc019e
> --- /dev/null
> +++ b/sound/soc/qcom/Makefile
> @@ -0,0 +1,11 @@
> +# Platform
> +snd-soc-lpass-cpu-objs := lpass-cpu.o
> +snd-soc-lpass-platform-objs := lpass-platform.o
> +
> +obj-$(CONFIG_SND_SOC_LPASS_CPU) += snd-soc-lpass-cpu.o
> +obj-$(CONFIG_SND_SOC_LPASS_PLATFORM) += snd-soc-lpass-platform.o
> +
> +# Machine
> +snd-soc-storm-objs := storm.o
> +
> +obj-$(CONFIG_SND_SOC_STORM) += snd-soc-storm.o
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Patch V6 09/10] ASoC: Allow for building QCOM drivers
2015-02-25 6:39 [Patch V6 00/10] ASoC: QCOM: Add support for ipq806x SOC Kenneth Westfield
` (7 preceding siblings ...)
2015-02-25 6:39 ` [Patch V6 08/10] ASoC: qcom: Add ability to build QCOM drivers Kenneth Westfield
@ 2015-02-25 6:39 ` Kenneth Westfield
2015-02-25 6:39 ` [Patch V6 10/10] ARM: dts: Model IPQ LPASS audio hardware Kenneth Westfield
9 siblings, 0 replies; 12+ messages in thread
From: Kenneth Westfield @ 2015-02-25 6:39 UTC (permalink / raw)
To: Mark Brown, Takashi Iwai, Liam Girdwood, Banajit Goswami,
Patrick Lai, David Brown, Bryan Huntsman, Greg KH
Cc: Kenneth Westfield, ALSA Mailing List, MSM Mailing List,
Device Tree Mailing List, Kernel Mailing List
From: Kenneth Westfield <kwestfie@codeaurora.org>
Allow for the Qualcomm Technologies ASoC drivers
to build.
Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org>
Acked-by: Banajit Goswami <bgoswami@codeaurora.org>
---
sound/soc/Kconfig | 1 +
sound/soc/Makefile | 1 +
2 files changed, 2 insertions(+)
diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
index dcc79aa0236b548bfe5408fe56689241fc597e97..3ba52da18bc69a9bb41c84627cfc7d08f47e3bf0 100644
--- a/sound/soc/Kconfig
+++ b/sound/soc/Kconfig
@@ -47,6 +47,7 @@ source "sound/soc/kirkwood/Kconfig"
source "sound/soc/intel/Kconfig"
source "sound/soc/mxs/Kconfig"
source "sound/soc/pxa/Kconfig"
+source "sound/soc/qcom/Kconfig"
source "sound/soc/rockchip/Kconfig"
source "sound/soc/samsung/Kconfig"
source "sound/soc/sh/Kconfig"
diff --git a/sound/soc/Makefile b/sound/soc/Makefile
index 5b3c8f67c8db7a29ff7199a6103d445428978125..974ba708b4826a03077a58251434a311542d5e3c 100644
--- a/sound/soc/Makefile
+++ b/sound/soc/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_SND_SOC) += nuc900/
obj-$(CONFIG_SND_SOC) += omap/
obj-$(CONFIG_SND_SOC) += kirkwood/
obj-$(CONFIG_SND_SOC) += pxa/
+obj-$(CONFIG_SND_SOC) += qcom/
obj-$(CONFIG_SND_SOC) += rockchip/
obj-$(CONFIG_SND_SOC) += samsung/
obj-$(CONFIG_SND_SOC) += sh/
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 12+ messages in thread* [Patch V6 10/10] ARM: dts: Model IPQ LPASS audio hardware
2015-02-25 6:39 [Patch V6 00/10] ASoC: QCOM: Add support for ipq806x SOC Kenneth Westfield
` (8 preceding siblings ...)
2015-02-25 6:39 ` [Patch V6 09/10] ASoC: Allow for building " Kenneth Westfield
@ 2015-02-25 6:39 ` Kenneth Westfield
9 siblings, 0 replies; 12+ messages in thread
From: Kenneth Westfield @ 2015-02-25 6:39 UTC (permalink / raw)
To: Mark Brown, Takashi Iwai, Liam Girdwood, Banajit Goswami,
Patrick Lai, David Brown, Bryan Huntsman, Greg KH
Cc: Kenneth Westfield, ALSA Mailing List, MSM Mailing List,
Device Tree Mailing List, Kernel Mailing List
From: Kenneth Westfield <kwestfie@codeaurora.org>
Model the Qualcomm Technologies LPASS hardware for
the ipq806x SOC.
Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org>
Acked-by: Banajit Goswami <bgoswami@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index cb225dafe97cd83c9ae4cc19482ed55d4a71b8b3..dd5cbb33cc2d89be57494e05b7477352358affa5 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -2,6 +2,7 @@
#include "skeleton.dtsi"
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
+#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
#include <dt-bindings/soc/qcom,gsbi.h>
/ {
@@ -96,6 +97,24 @@
cpu-offset = <0x80000>;
};
+ lpass@28100000 {
+ compatible = "qcom,lpass-cpu";
+ status = "disabled";
+ clocks = <&lcc AHBIX_CLK>,
+ <&lcc MI2S_OSR_CLK>,
+ <&lcc MI2S_BIT_CLK>;
+ clock-names = "ahbix-clk",
+ "mi2s-osr-clk",
+ "mi2s-bit-clk";
+ interrupts = <0 85 1>;
+ interrupt-names = "lpass-irq-lpaif";
+ reg = <0x28100000 0x10000>;
+ reg-names = "lpass-lpaif";
+ qcom,adsp {
+ status = "disabled";
+ };
+ };
+
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
@@ -273,6 +292,13 @@
qcom,controller-type = "pmic-arbiter";
};
+ lcc: clock-controller@28000000 {
+ compatible = "qcom,lcc-ipq8064";
+ reg = <0x28000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
gcc: clock-controller@900000 {
compatible = "qcom,gcc-ipq8064";
reg = <0x00900000 0x4000>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 12+ messages in thread