From mboxrd@z Thu Jan 1 00:00:00 1970 From: Roman Volkov Subject: [PATCH v3 2/2] dts: vt8500: Fix errors in SDHC node for WM8505 Date: Sun, 1 Mar 2015 19:06:47 +0300 Message-ID: <1425226007-2757-3-git-send-email-rvolkov@v1ros.org> References: <1423130878-3894-1-git-send-email-v1ron@v1ros.org> <1425226007-2757-1-git-send-email-rvolkov@v1ros.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1425226007-2757-1-git-send-email-rvolkov@v1ros.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King Cc: devicetree@vger.kernel.org, Alexey Charkov , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Roman Volkov List-Id: devicetree@vger.kernel.org According to datasheet, the registers space of SDHC controller is 1Kb, not '0x1000', the correct value should be '0x400'. Bracket interrupt numbers individually per recommendations. Signed-off-by: Roman Volkov --- arch/arm/boot/dts/wm8505.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi index a1a854b..e9ef539 100644 --- a/arch/arm/boot/dts/wm8505.dtsi +++ b/arch/arm/boot/dts/wm8505.dtsi @@ -281,8 +281,8 @@ sdhc@d800a000 { compatible = "wm,wm8505-sdhc"; - reg = <0xd800a000 0x1000>; - interrupts = <20 21>; + reg = <0xd800a000 0x400>; + interrupts = <20>, <21>; clocks = <&clksdhc>; bus-width = <4>; }; -- 2.3.1