[PATCH v2 0/5] ARM: sunxi: SRAM mapping support

[PATCH v2 0/5] ARM: sunxi: SRAM mapping support

[Hans de Goede]

Hi All,

Here is v2 of my cleaned up version of Maxime's sunxi SRAM controller driver.

Changes since v1:
- Make the SUNXI_SRAM Kconfig option hidden, enabled by default if ARCH_SUNXI
- Fix some typos in the comments in the dts file, both in the example in the
  devicetree-binding documentation, as well as in the actual dts files
- Drop the bogus change to drivers/net/ethernet/stmicro/stmmac/Kconfig

Since this is a prereq for my musb work, if there are no objections then I
would like to see this go upstream soon.

Since it only touches sunxi files (and one Makefile), it is probably best if
this all goes upstream through Maxime.

Regards,

Hans

[PATCH v2 1/5] drivers: soc: sunxi: Introduce SoC driver to map SRAMs

[Hans de Goede]

From: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>

The Allwinner SoCs have a handful of SRAM that can be either mapped to be
accessible by devices or the CPU.

That mapping is controlled by an SRAM controller, and that mapping might not be
set by the bootloader, for example if the device wasn't used at all, or if
we're using solutions like the U-Boot's Falcon Boot.

We could also imagine changing this at runtime for example to change the
mapping of these SRAMs to use them for suspend/resume or runtime memory rate
change, if that ever happens.

These use cases require some API in the kernel to control that mapping,
exported through a drivers/soc driver.

This driver also implement a debugfs file that shows the SRAM found in the
system, the current mapping and the SRAM that have been claimed by some drivers
in the kernel.

Signed-off-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
[hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org: Changed compat string to sun4i-a10-sram-controller, as
 the sram controller is identical on sun4i, sun5i & sun7i, added devicetree
 binding documentation, fixed some checkpatch warnings]
Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
 .../devicetree/bindings/soc/sunxi/sram.txt         |  64 ++++++
 drivers/soc/Kconfig                                |   1 +
 drivers/soc/Makefile                               |   1 +
 drivers/soc/sunxi/Kconfig                          |  11 +
 drivers/soc/sunxi/Makefile                         |   1 +
 drivers/soc/sunxi/sunxi_sram.c                     | 235 +++++++++++++++++++++
 include/linux/soc/sunxi/sunxi_sram.h               |  24 +++
 7 files changed, 337 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/sunxi/sram.txt
 create mode 100644 drivers/soc/sunxi/Kconfig
 create mode 100644 drivers/soc/sunxi/Makefile
 create mode 100644 drivers/soc/sunxi/sunxi_sram.c
 create mode 100644 include/linux/soc/sunxi/sunxi_sram.h

diff --git a/Documentation/devicetree/bindings/soc/sunxi/sram.txt b/Documentation/devicetree/bindings/soc/sunxi/sram.txt
new file mode 100644
index 0000000..bd3e53d
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/sunxi/sram.txt
@@ -0,0 +1,64 @@
+Allwinnner sun4i / sun5i / sun7i SoC SRAM controllers
+-----------------------------------------------------
+
+Required properties:
+- compatible : "allwinner,sun4i-a10-sram-controller"
+- reg : sram controller register offset + length
+
+SRAM nodes
+----------
+
+Besides a node for the SRAM controller the devicetree must also contain a
+node for each SRAM block controlled by the controller.
+
+Required sram node properties:
+- compatible : "allwinner,sun4i-a10-sram"
+- allwinner,sram-name : should be one of
+  * "A1"
+  * "A2"
+  * "A3-A4"
+  * "D"
+
+Example
+-------
+
+/*
+ * Note we use the address where the mmio registers start, not where
+ * the SRAM blocks start, this cannot be changed because that would be
+ * a devicetree ABI change.
+ */
+soc@01c00000 {
+	compatible = "simple-bus";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges;
+
+	sram@00000000 {
+		compatible = "allwinner,sun4i-a10-sram";
+		reg = <0x00000000 0x4000>;
+		allwinner,sram-name = "A1";
+	};
+
+	sram@00004000 {
+		compatible = "allwinner,sun4i-a10-sram";
+		reg = <0x00004000 0x4000>;
+		allwinner,sram-name = "A2";
+	};
+
+	sram@00008000 {
+		compatible = "allwinner,sun4i-a10-sram";
+		reg = <0x00008000 0x4000>;
+		allwinner,sram-name = "A3-A4";
+	};
+
+	sram@00010000 {
+		compatible = "allwinner,sun4i-a10-sram";
+		reg = <0x00010000 0x1000>;
+		allwinner,sram-name = "D";
+	};
+
+	sram-controller@01c00000 {
+		compatible = "allwinner,sun4i-a10-sram-controller";
+		reg = <0x01c00000 0x30>;
+	};
+};
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 76d6bd4..5d0f55d 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -1,6 +1,7 @@
 menu "SOC (System On Chip) specific Drivers"
 
 source "drivers/soc/qcom/Kconfig"
+source "drivers/soc/sunxi/Kconfig"
 source "drivers/soc/ti/Kconfig"
 source "drivers/soc/versatile/Kconfig"
 
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 063113d..170bba3 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -3,6 +3,7 @@
 #
 
 obj-$(CONFIG_ARCH_QCOM)		+= qcom/
+obj-$(CONFIG_ARCH_SUNXI)	+= sunxi/
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-$(CONFIG_SOC_TI)		+= ti/
 obj-$(CONFIG_PLAT_VERSATILE)	+= versatile/
diff --git a/drivers/soc/sunxi/Kconfig b/drivers/soc/sunxi/Kconfig
new file mode 100644
index 0000000..e6de9fe
--- /dev/null
+++ b/drivers/soc/sunxi/Kconfig
@@ -0,0 +1,11 @@
+#
+# Allwinner sunXi SoC drivers
+#
+config SUNXI_SRAM
+	boolean
+	depends on ARCH_SUNXI
+	default y
+	help
+	  Say y here to enable the SRAM controller support. This
+	  device is responsible on mapping the SRAM in the sunXi SoCs
+	  whether to the CPU/DMA, or to the devices.
diff --git a/drivers/soc/sunxi/Makefile b/drivers/soc/sunxi/Makefile
new file mode 100644
index 0000000..4cf9dbd
--- /dev/null
+++ b/drivers/soc/sunxi/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_SUNXI_SRAM) +=	sunxi_sram.o
diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
new file mode 100644
index 0000000..5b76fd1
--- /dev/null
+++ b/drivers/soc/sunxi/sunxi_sram.c
@@ -0,0 +1,235 @@
+/*
+ * Allwinner SoCs SRAM Controller Driver
+ *
+ * Copyright (C) 2015 Maxime Ripard
+ *
+ * Author: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/debugfs.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include <linux/soc/sunxi/sunxi_sram.h>
+
+struct sunxi_sram_func {
+	char	*func;
+	u8	val;
+};
+
+struct sunxi_sram_desc {
+	enum sunxi_sram_type	type;
+	char			*name;
+	u8			reg;
+	u8			offset;
+	u8			width;
+	struct sunxi_sram_func	*func;
+	bool			claimed;
+	bool			enabled;
+};
+
+#define SUNXI_SRAM_MAP(_val, _func)				\
+	{							\
+		.func = _func,					\
+		.val = _val,					\
+	}
+
+#define SUNXI_SRAM_DESC(_type, _name, _reg, _off, _width, ...)	\
+	{							\
+		.type = _type,					\
+		.name = _name,					\
+		.reg = _reg,					\
+		.offset = _off,					\
+		.width = _width,				\
+		.func = (struct sunxi_sram_func[]){		\
+			__VA_ARGS__, { } },			\
+	}
+
+struct sunxi_sram_desc sun4i_sram_desc[] = {
+	SUNXI_SRAM_DESC(SUNXI_SRAM_EMAC, "A3-A4", 0x4, 0x4, 1,
+			SUNXI_SRAM_MAP(0, "cpu"),
+			SUNXI_SRAM_MAP(1, "emac")),
+	SUNXI_SRAM_DESC(SUNXI_SRAM_USB_OTG, "D", 0x4, 0x0, 1,
+			SUNXI_SRAM_MAP(0, "cpu"),
+			SUNXI_SRAM_MAP(1, "usb-otg")),
+	{ /* Sentinel */ },
+};
+
+static struct sunxi_sram_desc *sram_list;
+static DEFINE_SPINLOCK(sram_lock);
+static void __iomem *base;
+
+static int sunxi_sram_show(struct seq_file *s, void *data)
+{
+	struct sunxi_sram_desc *sram;
+	struct sunxi_sram_func *func;
+	u32 val;
+
+	seq_puts(s, "Allwinner sunXi SRAM\n");
+	seq_puts(s, "--------------------\n");
+
+
+	for (sram = sram_list; sram->name; sram++) {
+		if (!sram->enabled)
+			continue;
+
+		seq_printf(s, "\n%s\n", sram->name);
+
+		val = readl(base + sram->reg);
+		val >>= sram->offset;
+		val &= sram->width;
+
+		for (func = sram->func; func->func; func++) {
+			seq_printf(s, "\t\t%s%c\n", func->func,
+				   func->val == val ? '*' : ' ');
+		}
+	}
+
+	return 0;
+}
+
+static int sunxi_sram_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, sunxi_sram_show, inode->i_private);
+}
+
+static const struct file_operations sunxi_sram_fops = {
+	.open = sunxi_sram_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+int sunxi_sram_claim(enum sunxi_sram_type type, const char *function)
+{
+	struct sunxi_sram_desc *sram;
+	struct sunxi_sram_func *func;
+	u32 val;
+
+	if (IS_ERR(base))
+		return -EPROBE_DEFER;
+
+	for (sram = sram_list; sram->name; sram++) {
+		if (sram->type != type)
+			continue;
+
+		if (!sram->enabled)
+			return -ENODEV;
+
+		spin_lock(&sram_lock);
+
+		if (sram->claimed) {
+			spin_unlock(&sram_lock);
+			return -EBUSY;
+		}
+
+		sram->claimed = true;
+		spin_unlock(&sram_lock);
+
+		for (func = sram->func; func->func; func++) {
+			if (strcmp(function, func->func))
+				continue;
+
+			val = readl(base + sram->reg);
+			val &= ~GENMASK(sram->offset + sram->width,
+					sram->offset);
+			writel(val | func->val, base + sram->reg);
+
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+EXPORT_SYMBOL(sunxi_sram_claim);
+
+int sunxi_sram_release(enum sunxi_sram_type type)
+{
+	struct sunxi_sram_desc *sram;
+
+	for (sram = sram_list; sram->type; sram++) {
+		if (sram->type != type)
+			continue;
+
+		if (!sram->enabled)
+			return -ENODEV;
+
+		spin_lock(&sram_lock);
+		sram->claimed = false;
+		spin_unlock(&sram_lock);
+
+		return 0;
+	}
+
+	return -EINVAL;
+}
+EXPORT_SYMBOL(sunxi_sram_release);
+
+static const struct of_device_id sunxi_sram_dt_match[] = {
+	{ .compatible = "allwinner,sun4i-a10-sram-controller",
+	  .data = &sun4i_sram_desc },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match);
+
+static int sunxi_sram_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *match;
+	struct sunxi_sram_desc *sram;
+	struct device_node *node;
+	struct resource *res;
+	struct dentry *d;
+	const char *name;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	match = of_match_device(sunxi_sram_dt_match, &pdev->dev);
+	if (!match)
+		return -ENODEV;
+
+	sram_list = (struct sunxi_sram_desc *)match->data;
+
+	for_each_compatible_node(node, NULL, "allwinner,sun4i-a10-sram") {
+		if (of_property_read_string(node, "allwinner,sram-name", &name))
+			continue;
+
+		for (sram = sram_list; sram->name; sram++)
+			if (!strcmp(name, sram->name))
+				break;
+
+		if (!sram->name)
+			continue;
+
+		sram->enabled = true;
+	}
+
+	d = debugfs_create_file("sram", S_IRUGO, NULL, NULL,
+				&sunxi_sram_fops);
+	if (!d)
+		return -ENOMEM;
+
+	return 0;
+}
+
+static struct platform_driver sunxi_sram_driver = {
+	.driver = {
+		.name		= "sunxi-sram",
+		.of_match_table	= sunxi_sram_dt_match,
+	},
+	.probe	= sunxi_sram_probe,
+};
+module_platform_driver(sunxi_sram_driver);
+
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>");
+MODULE_DESCRIPTION("Allwinner sunXi SRAM Controller Driver");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/soc/sunxi/sunxi_sram.h b/include/linux/soc/sunxi/sunxi_sram.h
new file mode 100644
index 0000000..351c31a
--- /dev/null
+++ b/include/linux/soc/sunxi/sunxi_sram.h
@@ -0,0 +1,24 @@
+/*
+ * Allwinner SoCs SRAM Controller Driver
+ *
+ * Copyright (C) 2015 Maxime Ripard
+ *
+ * Author: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef _SUNXI_SRAM_H_
+#define _SUNXI_SRAM_H_
+
+enum sunxi_sram_type {
+	SUNXI_SRAM_USB_OTG,
+	SUNXI_SRAM_EMAC,
+};
+
+int sunxi_sram_claim(enum sunxi_sram_type type, const char *function);
+int sunxi_sram_release(enum sunxi_sram_type type);
+
+#endif /* _SUNXI_SRAM_H_ */
-- 
2.3.3

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[PATCH v2 2/5] ARM: dts: sun4i: Add A10 SRAM and SRAM controller

[Hans de Goede]

The A10 has a few SRAM that can be mapped either to a device or to the CPU,
with the mapping being controlled by a SRAM controller.

Since most of the time these SRAM won't be accessible by the CPU,
we can't use the mmio-sram driver and compatible.

Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 59fc7f7..595b77c 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -451,12 +451,46 @@
 		};
 	};
 
+	/*
+	 * Note we use the address where the mmio registers start, not where
+	 * the SRAM blocks start, this cannot be changed because that would be
+	 * a devicetree ABI change.
+	 */
 	soc@01c00000 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
 
+		sram@00000000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00000000 0x4000>;
+			allwinner,sram-name = "A1";
+		};
+
+		sram@00004000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00004000 0x4000>;
+			allwinner,sram-name = "A2";
+		};
+
+		sram@00008000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00008000 0x4000>;
+			allwinner,sram-name = "A3-A4";
+		};
+
+		sram@00010000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00010000 0x1000>;
+			allwinner,sram-name = "D";
+		};
+
+		sram-controller@01c00000 {
+			compatible = "allwinner,sun4i-a10-sram-controller";
+			reg = <0x01c00000 0x30>;
+		};
+
 		dma: dma-controller@01c02000 {
 			compatible = "allwinner,sun4i-a10-dma";
 			reg = <0x01c02000 0x1000>;
-- 
2.3.3

[PATCH v2 3/5] ARM: dts: sun5i: Add A13 and A10s SRAM and SRAM controller

[Hans de Goede]

The A13 / A10s has a few SRAM that can be mapped either to a device or to
the CPU, with the mapping being controlled by a SRAM controller.

Since most of the time these SRAM won't be accessible by the CPU,
we can't use the mmio-sram driver and compatible.

Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/sun5i.dtsi | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index c797d88..8c04f24 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -298,12 +298,46 @@
 		};
 	};
 
+	/*
+	 * Note we use the address where the mmio registers start, not where
+	 * the SRAM blocks start, this cannot be changed because that would be
+	 * a devicetree ABI change.
+	 */
 	soc@01c00000 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
 
+		sram@00000000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00000000 0x4000>;
+			allwinner,sram-name = "A1";
+		};
+
+		sram@00004000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00004000 0x4000>;
+			allwinner,sram-name = "A2";
+		};
+
+		sram@00008000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00008000 0x4000>;
+			allwinner,sram-name = "A3-A4";
+		};
+
+		sram@00010000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00010000 0x1000>;
+			allwinner,sram-name = "D";
+		};
+
+		sram-controller@01c00000 {
+			compatible = "allwinner,sun4i-a10-sram-controller";
+			reg = <0x01c00000 0x30>;
+		};
+
 		dma: dma-controller@01c02000 {
 			compatible = "allwinner,sun4i-a10-dma";
 			reg = <0x01c02000 0x1000>;
-- 
2.3.3

[PATCH v2 4/5] ARM: dts: sun7i: Add A20 SRAM and SRAM controller

[Hans de Goede]

From: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>

The A20 has a few SRAM that can be mapped either to a device or to the CPU,
with the mapping being controlled by a SRAM controller.

Since most of the time these SRAM won't be accessible by the CPU,
we can't use the mmio-sram driver and compatible.

Signed-off-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
[hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org: Do not change soc node name, change compatible to
 sun4i-a10-sram-controller to match the driver change]
Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 465a19f..e6f4a33 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -529,12 +529,46 @@
 		};
 	};
 
+	/*
+	 * Note we use the address where the mmio registers start, not where
+	 * the SRAM blocks start, this cannot be changed because that would be
+	 * a devicetree ABI change.
+	 */
 	soc@01c00000 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
 
+		sram@00000000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00000000 0x4000>;
+			allwinner,sram-name = "A1";
+		};
+
+		sram@00004000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00004000 0x4000>;
+			allwinner,sram-name = "A2";
+		};
+
+		sram@00008000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00008000 0x4000>;
+			allwinner,sram-name = "A3-A4";
+		};
+
+		sram@00010000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00010000 0x1000>;
+			allwinner,sram-name = "D";
+		};
+
+		sram-controller@01c00000 {
+			compatible = "allwinner,sun4i-a10-sram-controller";
+			reg = <0x01c00000 0x30>;
+		};
+
 		nmi_intc: interrupt-controller@01c00030 {
 			compatible = "allwinner,sun7i-a20-sc-nmi";
 			interrupt-controller;
-- 
2.3.3

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[PATCH v2 5/5] net: allwinner: emac: Claim our SRAM

[Hans de Goede]

From: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>

The SRAM the EMAC is using might not have been mapped accordingly by the
bootloader, preventing the EMAC to work properly.

Ask for that SRAM to be mapped at probe time to make sure that this never
happens.

Signed-off-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
[hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org: Make sure SUNXI_SRAM gets enabled in Kconfig]
Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
 drivers/net/ethernet/allwinner/sun4i-emac.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/allwinner/sun4i-emac.c b/drivers/net/ethernet/allwinner/sun4i-emac.c
index f3470d9..9d0136b 100644
--- a/drivers/net/ethernet/allwinner/sun4i-emac.c
+++ b/drivers/net/ethernet/allwinner/sun4i-emac.c
@@ -29,6 +29,8 @@
 #include <linux/platform_device.h>
 #include <linux/phy.h>
 
+#include <linux/soc/sunxi/sunxi_sram.h>
+
 #include "sun4i-emac.h"
 
 #define DRV_NAME		"sun4i-emac"
@@ -857,11 +859,15 @@ static int emac_probe(struct platform_device *pdev)
 
 	clk_prepare_enable(db->clk);
 
+	ret = sunxi_sram_claim(SUNXI_SRAM_EMAC, "emac");
+	if (ret)
+		dev_warn(&pdev->dev, "Couldn't map SRAM to device\n");
+
 	db->phy_node = of_parse_phandle(np, "phy", 0);
 	if (!db->phy_node) {
 		dev_err(&pdev->dev, "no associated PHY\n");
 		ret = -ENODEV;
-		goto out;
+		goto out_release_sram;
 	}
 
 	/* Read MAC-address from DT */
@@ -893,7 +899,7 @@ static int emac_probe(struct platform_device *pdev)
 	if (ret) {
 		dev_err(&pdev->dev, "Registering netdev failed!\n");
 		ret = -ENODEV;
-		goto out;
+		goto out_release_sram;
 	}
 
 	dev_info(&pdev->dev, "%s: at %p, IRQ %d MAC: %pM\n",
@@ -901,6 +907,8 @@ static int emac_probe(struct platform_device *pdev)
 
 	return 0;
 
+out_release_sram:
+	sunxi_sram_release(SUNXI_SRAM_EMAC);
 out:
 	dev_err(db->dev, "not found (%d).\n", ret);
 
@@ -914,6 +922,7 @@ static int emac_remove(struct platform_device *pdev)
 	struct net_device *ndev = platform_get_drvdata(pdev);
 
 	unregister_netdev(ndev);
+	sunxi_sram_release(SUNXI_SRAM_EMAC);
 	free_netdev(ndev);
 
 	dev_dbg(&pdev->dev, "released and freed device\n");
-- 
2.3.3

Re: [PATCH v2 0/5] ARM: sunxi: SRAM mapping support

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1023 bytes --]

Hi,

On Thu, Mar 26, 2015 at 03:53:40PM +0100, Hans de Goede wrote:
> Hi All,
> 
> Here is v2 of my cleaned up version of Maxime's sunxi SRAM controller driver.
> 
> Changes since v1:
> - Make the SUNXI_SRAM Kconfig option hidden, enabled by default if ARCH_SUNXI
> - Fix some typos in the comments in the dts file, both in the example in the
>   devicetree-binding documentation, as well as in the actual dts files
> - Drop the bogus change to drivers/net/ethernet/stmicro/stmmac/Kconfig
> 
> Since this is a prereq for my musb work, if there are no objections then I
> would like to see this go upstream soon.
> 
> Since it only touches sunxi files (and one Makefile), it is probably best if
> this all goes upstream through Maxime.

I'm (obviously) fine with all the changes. Arnd, can I merge it
through my tree and send a pull request, or do you want to handle the
drivers/soc patches yourself?

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v2 0/5] ARM: sunxi: SRAM mapping support

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 873 bytes --]

On Thu, Mar 26, 2015 at 03:53:40PM +0100, Hans de Goede wrote:
> Hi All,
> 
> Here is v2 of my cleaned up version of Maxime's sunxi SRAM controller driver.
> 
> Changes since v1:
> - Make the SUNXI_SRAM Kconfig option hidden, enabled by default if ARCH_SUNXI
> - Fix some typos in the comments in the dts file, both in the example in the
>   devicetree-binding documentation, as well as in the actual dts files
> - Drop the bogus change to drivers/net/ethernet/stmicro/stmmac/Kconfig
> 
> Since this is a prereq for my musb work, if there are no objections then I
> would like to see this go upstream soon.
> 
> Since it only touches sunxi files (and one Makefile), it is probably best if
> this all goes upstream through Maxime.

Merged patches 1-4. Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com