[PATH] MIPS: ath79: Add OF support and DTS for TL-WR1043ND

[PATH] MIPS: ath79: Add OF support and DTS for TL-WR1043ND

[Alban Bedel]

This series add OF bindings and code support for the interrupt
controllers, clocks and GPIOs. However it was only tested on a
TL-WR1043ND with an AR9132, others SoCs are untested, and a few are
not supported at all.

Most code changes base on the previous bug fix series:
[PATH] MIPS: ath79: Various small fix to prepare OF support

[PATCH 01/14] devicetree: Add bindings for the SoC of the ATH79 familly

[Alban Bedel]

Signed-off-by: Alban Bedel <albeu@free.fr>
---
 .../devicetree/bindings/mips/ath79-soc.txt          | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mips/ath79-soc.txt

diff --git a/Documentation/devicetree/bindings/mips/ath79-soc.txt b/Documentation/devicetree/bindings/mips/ath79-soc.txt
new file mode 100644
index 0000000..88a12a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/ath79-soc.txt
@@ -0,0 +1,21 @@
+Binding for Qualcomm Atheros AR7xxx/AR9XXX SoC
+
+Each device tree must specify a compatible value for the AR SoC
+it uses in the compatible property of the root node. The compatible
+value must be one of the following values:
+
+- qca,ar7130
+- qca,ar7141
+- qca,ar7161
+- qca,ar7240
+- qca,ar7241
+- qca,ar7242
+- qca,ar9130
+- qca,ar9132
+- qca,ar9330
+- qca,ar9331
+- qca,ar9341
+- qca,ar9342
+- qca,ar9344
+- qca,qca9556
+- qca,qca9558
-- 
2.0.0

[PATCH 02/14] MIPS: ath79: Add basic device tree support

[Alban Bedel]

Add the bare minimum to load a device tree.

Signed-off-by: Alban Bedel <albeu@free.fr>
---
 arch/mips/Kconfig           |  1 +
 arch/mips/ath79/Kconfig     | 10 ++++++++++
 arch/mips/ath79/machtypes.h |  1 +
 arch/mips/ath79/setup.c     | 27 ++++++++++++++++++++++++++-
 4 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cc7f262..1fa7f2f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -129,6 +129,7 @@ config ATH79
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select SYS_SUPPORTS_MIPS16
 	select SYS_SUPPORTS_ZBOOT
+	select USE_OF
 	help
 	  Support for the Atheros AR71XX/AR724X/AR913X SoCs.
 
diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig
index dfc6020..1d38c6a 100644
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
@@ -71,6 +71,16 @@ config ATH79_MACH_UBNT_XM
 	  Say 'Y' here if you want your kernel to support the
 	  Ubiquiti Networks XM (rev 1.0) board.
 
+choice
+	prompt "Builtin devicetree selection"
+	default DTB_ATH79_NONE
+	help
+	  Select the devicetree.
+
+	config DTB_ATH79_NONE
+		bool "None"
+endchoice
+
 endmenu
 
 config SOC_AR71XX
diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h
index 2625405..a13db3d 100644
--- a/arch/mips/ath79/machtypes.h
+++ b/arch/mips/ath79/machtypes.h
@@ -15,6 +15,7 @@
 #include <asm/mips_machine.h>
 
 enum ath79_mach_type {
+	ATH79_MACH_GENERIC_OF = -1,	/* Device tree board */
 	ATH79_MACH_GENERIC = 0,
 	ATH79_MACH_AP121,		/* Atheros AP121 reference board */
 	ATH79_MACH_AP136_010,		/* Atheros AP136-010 reference board */
diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
index 74f1af7..01a644f 100644
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -17,12 +17,16 @@
 #include <linux/bootmem.h>
 #include <linux/err.h>
 #include <linux/clk.h>
+#include <linux/of_platform.h>
+#include <linux/of_fdt.h>
 
 #include <asm/bootinfo.h>
 #include <asm/idle.h>
 #include <asm/time.h>		/* for mips_hpt_frequency */
 #include <asm/reboot.h>		/* for _machine_{restart,halt} */
 #include <asm/mips_machine.h>
+#include <asm/prom.h>
+#include <asm/fw/fw.h>
 
 #include <asm/mach-ath79/ath79.h>
 #include <asm/mach-ath79/ar71xx_regs.h>
@@ -194,8 +198,19 @@ unsigned int get_c0_compare_int(void)
 
 void __init plat_mem_setup(void)
 {
+	unsigned long fdt_start;
+
 	set_io_port_base(KSEG1);
 
+	/* Get the position of the FDT passed by the bootloader */
+	fdt_start = fw_getenvl("fdt_start");
+	if (fdt_start)
+		__dt_setup_arch((void *)KSEG0ADDR(fdt_start));
+#ifdef CONFIG_BUILTIN_DTB
+	else
+		__dt_setup_arch(__dtb_start);
+#endif
+
 	ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 					   AR71XX_RESET_SIZE);
 	ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
@@ -203,7 +218,8 @@ void __init plat_mem_setup(void)
 	ath79_ddr_ctrl_init();
 
 	ath79_detect_sys_type();
-	detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
+	if (mips_machtype != ATH79_MACH_GENERIC_OF)
+		detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
 
 	_machine_restart = ath79_restart;
 	_machine_halt = ath79_halt;
@@ -235,6 +251,10 @@ void __init plat_time_init(void)
 
 static int __init ath79_setup(void)
 {
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+	if  (mips_machtype == ATH79_MACH_GENERIC_OF)
+		return 0;
+
 	ath79_gpio_init();
 	ath79_register_uart();
 	ath79_register_wdt();
@@ -246,6 +266,11 @@ static int __init ath79_setup(void)
 
 arch_initcall(ath79_setup);
 
+void __init device_tree_init(void)
+{
+	unflatten_and_copy_device_tree();
+}
+
 static void __init ath79_generic_init(void)
 {
 	/* Nothing to do */
-- 
2.0.0

Re: [PATCH 02/14] MIPS: ath79: Add basic device tree support

[Paul Bolle]

On Fri, 2015-04-17 at 16:24 +0200, Alban Bedel wrote:

> --- a/arch/mips/ath79/Kconfig
> +++ b/arch/mips/ath79/Kconfig
>  
> +choice
> +	prompt "Builtin devicetree selection"
> +	default DTB_ATH79_NONE
> +	help
> +	  Select the devicetree.
> +
> +	config DTB_ATH79_NONE
> +		bool "None"
> +endchoice

This adds a choice block with one config entry. So what this achieves is
that DTB_ATH79_NONE will always be 'y', right? Besides I didn't notice
on a user of CONFIG_DTB_ATH79_NONE. So as far as I can see this choice
has no effect on the build.

Why was this choice entry added?


Paul Bolle

Re: [PATCH 02/14] MIPS: ath79: Add basic device tree support

[Alban]

On Sat, 18 Apr 2015 09:05:52 +0200
Paul Bolle <pebolle-IWqWACnzNjzz+pZb47iToQ@public.gmane.org> wrote:

> On Fri, 2015-04-17 at 16:24 +0200, Alban Bedel wrote:
> 
> > --- a/arch/mips/ath79/Kconfig
> > +++ b/arch/mips/ath79/Kconfig
> >  
> > +choice
> > +	prompt "Builtin devicetree selection"
> > +	default DTB_ATH79_NONE
> > +	help
> > +	  Select the devicetree.
> > +
> > +	config DTB_ATH79_NONE
> > +		bool "None"
> > +endchoice
> 
> This adds a choice block with one config entry. So what this achieves
> is that DTB_ATH79_NONE will always be 'y', right? Besides I didn't
> notice on a user of CONFIG_DTB_ATH79_NONE. So as far as I can see
> this choice has no effect on the build.
> 
> Why was this choice entry added?

This menu is for boards that need a built-in DTB, as MIPS currently
doesn't support appended DTBs it is the only way to load a DTB on
boards stuck with a broken boot loader. But as no board has been added
yet it only contain the entry for boards that don't need a built-in
DTB, which do nothing as you pointed out.

A board is then added in this menu in patch 14, for some reasons git
send-email didn't send the whole serie at once :(

Alban
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Re: [PATCH 02/14] MIPS: ath79: Add basic device tree support

[Paul Bolle]

On Sat, 2015-04-18 at 18:31 +0200, Alban wrote:
> On Sat, 18 Apr 2015 09:05:52 +0200
> Paul Bolle <pebolle-IWqWACnzNjzz+pZb47iToQ@public.gmane.org> wrote:
> 
> > On Fri, 2015-04-17 at 16:24 +0200, Alban Bedel wrote:
> > 
> > > --- a/arch/mips/ath79/Kconfig
> > > +++ b/arch/mips/ath79/Kconfig
> > >  
> > > +choice
> > > +	prompt "Builtin devicetree selection"
> > > +	default DTB_ATH79_NONE
> > > +	help
> > > +	  Select the devicetree.
> > > +
> > > +	config DTB_ATH79_NONE
> > > +		bool "None"
> > > +endchoice
> > 
> > This adds a choice block with one config entry. So what this achieves
> > is that DTB_ATH79_NONE will always be 'y', right? Besides I didn't
> > notice on a user of CONFIG_DTB_ATH79_NONE. So as far as I can see
> > this choice has no effect on the build.
> > 
> > Why was this choice entry added?
> 
> This menu is for boards that need a built-in DTB, as MIPS currently
> doesn't support appended DTBs it is the only way to load a DTB on
> boards stuck with a broken boot loader. But as no board has been added
> yet it only contain the entry for boards that don't need a built-in
> DTB, which do nothing as you pointed out.
> 
> A board is then added in this menu in patch 14, for some reasons git
> send-email didn't send the whole serie at once :(

I saw 14/14 fly by now. (And I saw 12/12 of v2, which basically replaces
14/14.) That makes things clear.

Perhaps, if you're going to send a v3, you might move this change into
12/12. At least, I see little reason to add this choice block in two
separate steps in this series.

(Side note: you _might_ be able to drop config DTB_ATH79_NONE entirely
if you also replace
	default DTB_ATH79_NONE

with
	optional

optional is a little used option for choice blocks. I haven't tested
this, so this suggestion could end up wasting your time. And even then
this all looks like a complicated way to set just DTB_TL_WR1043ND_V1. I
suppose you expect to add things to this choice block in the future.)

Thanks,


Paul Bolle

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Re: [PATCH 02/14] MIPS: ath79: Add basic device tree support

[Alban]

On Mon, 20 Apr 2015 11:50:56 +0200
Paul Bolle <pebolle@tiscali.nl> wrote:

> On Sat, 2015-04-18 at 18:31 +0200, Alban wrote:
> > On Sat, 18 Apr 2015 09:05:52 +0200
> > Paul Bolle <pebolle@tiscali.nl> wrote:
> > 
> > > On Fri, 2015-04-17 at 16:24 +0200, Alban Bedel wrote:
> > > 
> > > > --- a/arch/mips/ath79/Kconfig
> > > > +++ b/arch/mips/ath79/Kconfig
> > > >  
> > > > +choice
> > > > +	prompt "Builtin devicetree selection"
> > > > +	default DTB_ATH79_NONE
> > > > +	help
> > > > +	  Select the devicetree.
> > > > +
> > > > +	config DTB_ATH79_NONE
> > > > +		bool "None"
> > > > +endchoice
> > > 
> > > This adds a choice block with one config entry. So what this
> > > achieves is that DTB_ATH79_NONE will always be 'y', right?
> > > Besides I didn't notice on a user of CONFIG_DTB_ATH79_NONE. So as
> > > far as I can see this choice has no effect on the build.
> > > 
> > > Why was this choice entry added?
> > 
> > This menu is for boards that need a built-in DTB, as MIPS currently
> > doesn't support appended DTBs it is the only way to load a DTB on
> > boards stuck with a broken boot loader. But as no board has been
> > added yet it only contain the entry for boards that don't need a
> > built-in DTB, which do nothing as you pointed out.
> > 
> > A board is then added in this menu in patch 14, for some reasons git
> > send-email didn't send the whole serie at once :(
> 
> I saw 14/14 fly by now. (And I saw 12/12 of v2, which basically
> replaces 14/14.) That makes things clear.
> 
> Perhaps, if you're going to send a v3, you might move this change into
> 12/12. At least, I see little reason to add this choice block in two
> separate steps in this series.

Ok, I'll do that.

> (Side note: you _might_ be able to drop config DTB_ATH79_NONE entirely
> if you also replace
> 	default DTB_ATH79_NONE
> 
> with
> 	optional
> 
> optional is a little used option for choice blocks. I haven't tested
> this, so this suggestion could end up wasting your time. And even then
> this all looks like a complicated way to set just DTB_TL_WR1043ND_V1.

I'll try that.

> I suppose you expect to add things to this choice block in the
> future.)

This is the only ATH79 board I currently have access to. However
openwrt has patches to add support for quiet a few, so I hope more
boards will be submitted once we have DT support in. Most of these
boards are appliance stuck with old bootloaders, so they will need this
too. 

Alban

[PATCH 03/14] devicetree: Add bindings for the ATH79 DDR controllers

[Alban Bedel]

The DDR controller of the ARxxx and AR9xxx famillies provides an
interface to flush the FIFO between various devices and the DDR.
This is mainly used by the IRQ controller to flush the FIFO before
running the interrupt handler of such devices.

Signed-off-by: Alban Bedel <albeu@free.fr>
---
 .../memory-controllers/ath79-ddr-controller.txt    | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt

diff --git a/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt
new file mode 100644
index 0000000..5541eed
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt
@@ -0,0 +1,35 @@
+Binding for Qualcomm  Atheros AR7xxx/AR9xxx DDR controller
+
+The DDR controller of the ARxxx and AR9xxx famillies provides an interface
+to flush the FIFO between various devices and the DDR. This is mainly used
+by the IRQ controller to flush the FIFO before running the interrupt handler
+of such devices.
+
+Required properties:
+
+- compatible: has to be "qca,<soc-type>-ddr-controller",
+  "qca,[ar7100|ar7240]-ddr-controller" as fallback.
+  On SoC with PCI support "qca,ar7100-ddr-controller" should be used as
+  fallback, otherwise "qca,ar7240-ddr-controller" should be used.
+- reg: Base address and size of the controllers memory area
+- #qca,ddr-wb-channel-cells: has to be 1, the index of the write buffer
+  channel
+
+Example:
+
+	ddr_ctrl: ddr-controller@18000000 {
+		compatible = "qca,ar9132-ddr-controller",
+				"qca,ar7240-ddr-controller";
+		reg = <0x18000000 0x100>;
+
+		#qca,ddr-wb-channel-cells = <1>;
+	};
+
+	...
+
+	cpuintc@0 {
+		...
+		qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
+		qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
+					<&ddr_ctrl 0>, <&ddr_ctrl 1>;
+	};
-- 
2.0.0

[PATCH 04/14] devicetree: Add bindings for the ATH79 interrupt controllers

[Alban Bedel]

Signed-off-by: Alban Bedel <albeu@free.fr>
---
 .../interrupt-controller/qca,ath79-cpu-intc.txt    | 45 ++++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt

diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt
new file mode 100644
index 0000000..1548512
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt
@@ -0,0 +1,45 @@
+Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller
+
+On most SoC the IRQ controller need to flush the DDR FIFO before running
+the interrupt handler of some devices. This is configured using the
+qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
+
+Required Properties:
+
+- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
+  as fallback
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode interrupt
+		     source, should be 1 for intc
+
+Please refer to interrupts.txt in this directory for details of the common
+Interrupt Controllers bindings used by client devices.
+
+Optional Properties:
+
+- qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
+  buffer flush
+- qca,ddr-wb-channels: List of phandles to the write buffer channels for
+  each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
+  default to the entry's index.
+
+Example:
+
+	cpuintc@0 {
+		compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
+		qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
+					<&ddr_ctrl 0>, <&ddr_ctrl 1>;
+	};
+
+	...
+
+	ddr_ctrl: ddr-controller@18000000 {
+		...
+		#qca,ddr-wb-channel-cells = <1>;
+	};
+
-- 
2.0.0

Re: [PATCH 04/14] devicetree: Add bindings for the ATH79 interrupt controllers

[Sergei Shtylyov]

Hello.

On 04/17/2015 05:24 PM, Alban Bedel wrote:

> Signed-off-by: Alban Bedel <albeu@free.fr>
> ---
>   .../interrupt-controller/qca,ath79-cpu-intc.txt    | 45 ++++++++++++++++++++++
>   1 file changed, 45 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt

> diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt
> new file mode 100644
> index 0000000..1548512
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt
> @@ -0,0 +1,45 @@
> +Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller
> +
> +On most SoC the IRQ controller need to flush the DDR FIFO before running
> +the interrupt handler of some devices. This is configured using the
> +qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
> +
> +Required Properties:
> +
> +- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
> +  as fallback
> +- interrupt-controller : Identifies the node as an interrupt controller
> +- #interrupt-cells : Specifies the number of cells needed to encode interrupt
> +		     source, should be 1 for intc
> +
> +Please refer to interrupts.txt in this directory for details of the common
> +Interrupt Controllers bindings used by client devices.
> +
> +Optional Properties:
> +
> +- qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
> +  buffer flush
> +- qca,ddr-wb-channels: List of phandles to the write buffer channels for
> +  each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
> +  default to the entry's index.
> +
> +Example:
> +
> +	cpuintc@0 {

    @0 without the "reg" property?
    And if this is an interrupt controller, the name should be 
"interrupt-controller", not "cpuintc", according to the ePAPR standard.

> +		compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
> +
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +
> +		qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
> +		qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
> +					<&ddr_ctrl 0>, <&ddr_ctrl 1>;
> +	};
> +
> +	...
> +
> +	ddr_ctrl: ddr-controller@18000000 {

    ePAPR standardized "memory-controller" node name in this case.

WBR, Sergei

[PATCH 05/14] devicetree: Add bindings for the ATH79 MISC interrupt controllers

[Alban Bedel]

Signed-off-by: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
---
 .../interrupt-controller/qca,ath79-misc-intc.txt   | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt

diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
new file mode 100644
index 0000000..11b54dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
@@ -0,0 +1,30 @@
+Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
+
+The MISC interrupt controller is a secondary controller for lower priority
+interrupt.
+
+Required Properties:
+- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc"
+  as fallback
+- reg: Base address and size of the controllers memory area
+- interrupt-parent: phandle of the parent interrupt controller.
+- interrupts: Interrupt specifier for the controllers interrupt.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode interrupt
+		     source, should be 1
+
+Please refer to interrupts.txt in this directory for details of the common
+Interrupt Controllers bindings used by client devices.
+
+Example:
+
+	miscintc@18060010 {
+		compatible = "qca,ar9132-misc-intc", qca,ar7100-misc-intc";
+		reg = <0x18060010 0x4>;
+
+		interrupt-parent = <&cpuintc>;
+		interrupts = <6>;
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+	};
-- 
2.0.0

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[PATCH 06/14] MIPS: ath79: Add OF support to the IRQ controllers

[Alban Bedel]

Add OF support for the CPU and MISC interrupt controllers of most
supported ATH79 devices.

Signed-off-by: Alban Bedel <albeu@free.fr>
---
 arch/mips/ath79/irq.c | 87 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 86 insertions(+), 1 deletion(-)

diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index 2c3991a..afb0096 100644
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -15,7 +15,9 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
-#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/of_irq.h>
+#include "../../../drivers/irqchip/irqchip.h"
 
 #include <asm/irq_cpu.h>
 #include <asm/mipsregs.h>
@@ -23,6 +25,7 @@
 #include <asm/mach-ath79/ath79.h>
 #include <asm/mach-ath79/ar71xx_regs.h>
 #include "common.h"
+#include "machtypes.h"
 
 static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
@@ -268,8 +271,90 @@ asmlinkage void plat_irq_dispatch(void)
 	}
 }
 
+#ifdef CONFIG_IRQCHIP
+static int misc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(irq, &ath79_misc_irq_chip, handle_level_irq);
+	return 0;
+}
+
+static const struct irq_domain_ops misc_irq_domain_ops = {
+	.xlate = irq_domain_xlate_onecell,
+	.map = misc_map,
+};
+
+static int __init ath79_misc_intc_of_init(
+	struct device_node *node, struct device_node *parent)
+{
+	void __iomem *base = ath79_reset_base;
+	struct irq_domain *domain;
+	int irq;
+
+	irq = irq_of_parse_and_map(node, 0);
+	if (!irq)
+		panic("Failed to get MISC IRQ");
+
+	domain = irq_domain_add_legacy(node, ATH79_MISC_IRQ_COUNT,
+			ATH79_MISC_IRQ_BASE, 0, &misc_irq_domain_ops, NULL);
+	if (!domain)
+		panic("Failed to add MISC irqdomain");
+
+	/* Disable and clear all interrupts */
+	__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+	__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
+
+
+	irq_set_chained_handler(irq, ath79_misc_irq_handler);
+
+	return 0;
+}
+IRQCHIP_DECLARE(ath79_misc_intc, "qca,ar7100-misc-intc",
+		ath79_misc_intc_of_init);
+
+static int __init ar79_cpu_intc_of_init(
+	struct device_node *node, struct device_node *parent)
+{
+	int err, i, count;
+
+	/* Fill the irq_wb_chan table */
+	count = of_count_phandle_with_args(
+		node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells");
+
+	for (i = 0; i < count; i++) {
+		struct of_phandle_args args;
+		u32 irq = i;
+
+		of_property_read_u32_index(
+			node, "qca,ddr-wb-channel-interrupts", i, &irq);
+		if (irq >= ARRAY_SIZE(irq_wb_chan))
+			continue;
+
+		err = of_parse_phandle_with_args(
+			node, "qca,ddr-wb-channels",
+			"#qca,ddr-wb-channel-cells",
+			i, &args);
+		if (err)
+			return err;
+
+		irq_wb_chan[irq] = args.args[0];
+		pr_info("IRQ: Set flush channel of IRQ%d to %d\n",
+			irq, args.args[0]);
+	}
+
+	return mips_cpu_irq_of_init(node, parent);
+}
+IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc",
+		ar79_cpu_intc_of_init);
+
+#endif
+
 void __init arch_init_irq(void)
 {
+	if (mips_machtype == ATH79_MACH_GENERIC_OF) {
+		irqchip_init();
+		return;
+	}
+
 	if (soc_is_ar71xx() || soc_is_ar724x() ||
 	    soc_is_ar913x() || soc_is_ar933x()) {
 		irq_wb_chan[2] = 3;
-- 
2.0.0

[PATCH 07/14] devicetree: Add bindings for the ATH79 PLL controllers

[Alban Bedel]

Signed-off-by: Alban Bedel <albeu@free.fr>
---
 .../devicetree/bindings/clock/qca,ath79-pll.txt    | 33 ++++++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qca,ath79-pll.txt

diff --git a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
new file mode 100644
index 0000000..2d2da3f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
@@ -0,0 +1,33 @@
+Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
+
+The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
+
+Required Properties:
+- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following
+  fallback:
+  - "qca,ar7100-pll"
+  - "qca,ar7240-pll"
+  - "qca,ar9130-pll"
+  - "qca,ar9330-pll"
+  - "qca,ar9340-pll"
+  - "qca,ar9550-pll"
+- reg: Base address and size of the controllers memory area
+- clock-names: Name of the input clock, has to be "ref"
+- clock: phandle of the external reference clock
+- #clock-cells: has to be one
+
+Optional properties:
+- clock-output-names: should be "cpu", "ddr", "ahb"
+
+Example:
+
+	pll-controller@18050000 {
+		compatible = "qca,ar9132-ppl", "qca,ar9130-pll";
+		reg = <0x18050000 0x20>;
+
+		clock-names = "ref";
+		clocks = <&extosc>;
+
+		#clock-cells = <1>;
+		clock-output-names = "cpu", "ddr", "ahb";
+	};
-- 
2.0.0

Re: [PATCH 07/14] devicetree: Add bindings for the ATH79 PLL controllers

[Sergei Shtylyov]

On 04/17/2015 05:24 PM, Alban Bedel wrote:

> Signed-off-by: Alban Bedel <albeu@free.fr>
> ---
>   .../devicetree/bindings/clock/qca,ath79-pll.txt    | 33 ++++++++++++++++++++++
>   1 file changed, 33 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/clock/qca,ath79-pll.txt

> diff --git a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
> new file mode 100644
> index 0000000..2d2da3f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
> @@ -0,0 +1,33 @@
> +Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
> +
> +The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
> +
> +Required Properties:
> +- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following
> +  fallback:

    Fallbacks.

> +  - "qca,ar7100-pll"
> +  - "qca,ar7240-pll"
> +  - "qca,ar9130-pll"
> +  - "qca,ar9330-pll"
> +  - "qca,ar9340-pll"
> +  - "qca,ar9550-pll"
> +- reg: Base address and size of the controllers memory area
> +- clock-names: Name of the input clock, has to be "ref"
> +- clock: phandle of the external reference clock

    The prop name is "clocks", not "clock".

[...]

WBR, Sergei

[PATCH 08/14] MIPS: ath79: Use the common clk API

[Alban Bedel]

Make the code simpler and open the way for device tree clocks.

Signed-off-by: Alban Bedel <albeu@free.fr>
---
 arch/mips/Kconfig       |  1 +
 arch/mips/ath79/clock.c | 29 ++---------------------------
 2 files changed, 3 insertions(+), 27 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1fa7f2f..a7b8ef4 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -120,6 +120,7 @@ config ATH79
 	select CSRC_R4K
 	select DMA_NONCOHERENT
 	select HAVE_CLK
+	select COMMON_CLK
 	select CLKDEV_LOOKUP
 	select IRQ_CPU
 	select MIPS_MACHINE
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index 226ddf0..1fcb691 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -17,6 +17,7 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/clk-provider.h>
 
 #include <asm/div64.h>
 
@@ -28,21 +29,15 @@
 #define AR724X_BASE_FREQ	5000000
 #define AR913X_BASE_FREQ	5000000
 
-struct clk {
-	unsigned long rate;
-};
-
 static void __init ath79_add_sys_clkdev(const char *id, unsigned long rate)
 {
 	struct clk *clk;
 	int err;
 
-	clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+	clk = clk_register_fixed_rate(NULL, id, NULL, CLK_IS_ROOT, rate);
 	if (!clk)
 		panic("failed to allocate %s clock structure", id);
 
-	clk->rate = rate;
-
 	err = clk_register_clkdev(clk, id, NULL);
 	if (err)
 		panic("unable to register %s clock device", id);
@@ -468,23 +463,3 @@ ath79_get_sys_clk_rate(const char *id)
 
 	return rate;
 }
-
-/*
- * Linux clock API
- */
-int clk_enable(struct clk *clk)
-{
-	return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-	return clk->rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-- 
2.0.0

[PATCH 09/14] MIPS: ath79: Add OF support to the clocks

[Alban Bedel]

Allow using the SoC clocks in the device tree.

Signed-off-by: Alban Bedel <albeu@free.fr>
---
 arch/mips/ath79/clock.c | 63 ++++++++++++++++++++++++++++++++++---------------
 1 file changed, 44 insertions(+), 19 deletions(-)

diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index 1fcb691..682bf61 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -29,7 +29,14 @@
 #define AR724X_BASE_FREQ	5000000
 #define AR913X_BASE_FREQ	5000000
 
-static void __init ath79_add_sys_clkdev(const char *id, unsigned long rate)
+static struct clk *clks[3];
+static struct clk_onecell_data clk_data = {
+	.clks = clks,
+	.clk_num = ARRAY_SIZE(clks),
+};
+
+static struct clk *__init ath79_add_sys_clkdev(
+	const char *id, unsigned long rate)
 {
 	struct clk *clk;
 	int err;
@@ -41,6 +48,8 @@ static void __init ath79_add_sys_clkdev(const char *id, unsigned long rate)
 	err = clk_register_clkdev(clk, id, NULL);
 	if (err)
 		panic("unable to register %s clock device", id);
+
+	return clk;
 }
 
 static void __init ar71xx_clocks_init(void)
@@ -70,9 +79,9 @@ static void __init ar71xx_clocks_init(void)
 	ahb_rate = cpu_rate / div;
 
 	ath79_add_sys_clkdev("ref", ref_rate);
-	ath79_add_sys_clkdev("cpu", cpu_rate);
-	ath79_add_sys_clkdev("ddr", ddr_rate);
-	ath79_add_sys_clkdev("ahb", ahb_rate);
+	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
+	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
+	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
 
 	clk_add_alias("wdt", NULL, "ahb", NULL);
 	clk_add_alias("uart", NULL, "ahb", NULL);
@@ -106,9 +115,9 @@ static void __init ar724x_clocks_init(void)
 	ahb_rate = cpu_rate / div;
 
 	ath79_add_sys_clkdev("ref", ref_rate);
-	ath79_add_sys_clkdev("cpu", cpu_rate);
-	ath79_add_sys_clkdev("ddr", ddr_rate);
-	ath79_add_sys_clkdev("ahb", ahb_rate);
+	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
+	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
+	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
 
 	clk_add_alias("wdt", NULL, "ahb", NULL);
 	clk_add_alias("uart", NULL, "ahb", NULL);
@@ -139,9 +148,9 @@ static void __init ar913x_clocks_init(void)
 	ahb_rate = cpu_rate / div;
 
 	ath79_add_sys_clkdev("ref", ref_rate);
-	ath79_add_sys_clkdev("cpu", cpu_rate);
-	ath79_add_sys_clkdev("ddr", ddr_rate);
-	ath79_add_sys_clkdev("ahb", ahb_rate);
+	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
+	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
+	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
 
 	clk_add_alias("wdt", NULL, "ahb", NULL);
 	clk_add_alias("uart", NULL, "ahb", NULL);
@@ -201,9 +210,9 @@ static void __init ar933x_clocks_init(void)
 	}
 
 	ath79_add_sys_clkdev("ref", ref_rate);
-	ath79_add_sys_clkdev("cpu", cpu_rate);
-	ath79_add_sys_clkdev("ddr", ddr_rate);
-	ath79_add_sys_clkdev("ahb", ahb_rate);
+	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
+	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
+	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
 
 	clk_add_alias("wdt", NULL, "ahb", NULL);
 	clk_add_alias("uart", NULL, "ref", NULL);
@@ -335,9 +344,9 @@ static void __init ar934x_clocks_init(void)
 		ahb_rate = cpu_pll / (postdiv + 1);
 
 	ath79_add_sys_clkdev("ref", ref_rate);
-	ath79_add_sys_clkdev("cpu", cpu_rate);
-	ath79_add_sys_clkdev("ddr", ddr_rate);
-	ath79_add_sys_clkdev("ahb", ahb_rate);
+	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
+	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
+	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
 
 	clk_add_alias("wdt", NULL, "ref", NULL);
 	clk_add_alias("uart", NULL, "ref", NULL);
@@ -422,9 +431,9 @@ static void __init qca955x_clocks_init(void)
 		ahb_rate = cpu_pll / (postdiv + 1);
 
 	ath79_add_sys_clkdev("ref", ref_rate);
-	ath79_add_sys_clkdev("cpu", cpu_rate);
-	ath79_add_sys_clkdev("ddr", ddr_rate);
-	ath79_add_sys_clkdev("ahb", ahb_rate);
+	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
+	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
+	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
 
 	clk_add_alias("wdt", NULL, "ref", NULL);
 	clk_add_alias("uart", NULL, "ref", NULL);
@@ -446,6 +455,8 @@ void __init ath79_clocks_init(void)
 		qca955x_clocks_init();
 	else
 		BUG();
+
+	of_clk_init(NULL);
 }
 
 unsigned long __init
@@ -463,3 +474,17 @@ ath79_get_sys_clk_rate(const char *id)
 
 	return rate;
 }
+
+#ifdef CONFIG_OF
+static void __init ath79_clocks_init_dt(struct device_node *np)
+{
+	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
+CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
+CLK_OF_DECLARE(ar9130, "qca,ar9130-pll", ath79_clocks_init_dt);
+CLK_OF_DECLARE(ar9330, "qca,ar9330-pll", ath79_clocks_init_dt);
+CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
+CLK_OF_DECLARE(ar9550, "qca,ar9550-pll", ath79_clocks_init_dt);
+#endif
-- 
2.0.0

[PATCH 10/14] devicetree: Add bindings for the ATH79 GPIO controllers

[Alban Bedel]

These bindings support the GPIO controllers found on the Qualcomm
Atheros AR7xxx/AR9XXX SoC.

Signed-off-by: Alban Bedel <albeu@free.fr>
---
 .../devicetree/bindings/gpio/gpio-ath79.txt        | 40 ++++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ath79.txt

diff --git a/Documentation/devicetree/bindings/gpio/gpio-ath79.txt b/Documentation/devicetree/bindings/gpio/gpio-ath79.txt
new file mode 100644
index 0000000..663c0b6
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-ath79.txt
@@ -0,0 +1,40 @@
+Binding for Qualcomm  Atheros AR7xxx/AR9xxx GPIO controller
+
+Required properties:
+- compatible: has to be "qca,<soctype>-gpio" and one of the following
+  fallback:
+  - "qca,ar7100-gpio"
+  - "qca,ar7240-gpio"
+  - "qca,ar7241-gpio"
+  - "qca,ar9130-gpio"
+  - "qca,ar9330-gpio"
+  - "qca,ar9340-gpio"
+  - "qca,qca9550-gpio"
+- reg: Base address and size of the controllers memory area
+- gpio-controller : Marks the device node as a GPIO controller.
+- #gpio-cells : Should be two. The first cell is the pin number and the
+  second cell is used to specify optional parameters.
+
+Optional properties:
+- interrupt-parent: phandle of the parent interrupt controller.
+- interrupts: Interrupt specifier for the controllers interrupt.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode interrupt
+		     source, should be 2
+
+Please refer to interrupts.txt in this directory for details of the common
+Interrupt Controllers bindings used by client devices.
+
+Example:
+
+	gpio@18040000 {
+		compatible = "qca,ar9132-gpio", "qca,ar9130-gpio";
+		reg = <0x18040000 0x30>;
+		interrupts = <2>;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
-- 
2.0.0

[PATCH 11/14] MIPS: ath79: Add OF support to the GPIO driver

[Alban Bedel]

Replace the simple GPIO chip registration by a platform driver
and make ath79_gpio_init() just register the device.

Signed-off-by: Alban Bedel <albeu@free.fr>
---
 arch/mips/ath79/dev-common.c | 13 ++++++++
 arch/mips/ath79/gpio.c       | 73 +++++++++++++++++++++++++++++++++++++++++---
 2 files changed, 81 insertions(+), 5 deletions(-)

diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c
index 516225d..4f397cb 100644
--- a/arch/mips/ath79/dev-common.c
+++ b/arch/mips/ath79/dev-common.c
@@ -106,3 +106,16 @@ void __init ath79_register_wdt(void)
 
 	platform_device_register_simple("ath79-wdt", -1, &res, 1);
 }
+
+void __init ath79_gpio_init(void)
+{
+	struct resource res;
+
+	memset(&res, 0, sizeof(res));
+
+	res.flags = IORESOURCE_MEM;
+	res.start = AR71XX_GPIO_BASE;
+	res.end = res.start + AR71XX_GPIO_SIZE - 1;
+
+	platform_device_register_simple("ath79-gpio", -1, &res, 1);
+}
diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c
index 8d025b0..ce1a61d 100644
--- a/arch/mips/ath79/gpio.c
+++ b/arch/mips/ath79/gpio.c
@@ -20,6 +20,7 @@
 #include <linux/io.h>
 #include <linux/ioport.h>
 #include <linux/gpio.h>
+#include <linux/of_device.h>
 
 #include <asm/mach-ath79/ar71xx_regs.h>
 #include <asm/mach-ath79/ath79.h>
@@ -178,11 +179,52 @@ void ath79_gpio_function_disable(u32 mask)
 	ath79_gpio_function_setup(0, mask);
 }
 
-void __init ath79_gpio_init(void)
+static const struct of_device_id ath79_gpio_of_match[] = {
+	{
+		.compatible = "qca,ar7100-gpio",
+		.data = (void *)AR71XX_GPIO_COUNT,
+	},
+	{
+		.compatible = "qca,ar7240-gpio",
+		.data = (void *)AR7240_GPIO_COUNT,
+	},
+	{
+		.compatible = "qca,ar7241-gpio",
+		.data = (void *)AR7241_GPIO_COUNT,
+	},
+	{
+		.compatible = "qca,ar9130-gpio",
+		.data = (void *)AR913X_GPIO_COUNT,
+	},
+	{
+		.compatible = "qca,ar9330-gpio",
+		.data = (void *)AR933X_GPIO_COUNT,
+	},
+	{
+		.compatible = "qca,ar9340-gpio",
+		.data = (void *)AR934X_GPIO_COUNT,
+	},
+	{
+		.compatible = "qca,qca9550-gpio",
+		.data = (void *)QCA955X_GPIO_COUNT,
+	},
+	{},
+};
+
+static int ath79_gpio_probe(struct platform_device *pdev)
 {
+	struct resource *res;
 	int err;
 
-	if (soc_is_ar71xx())
+	if (pdev->dev.of_node) {
+		const struct of_device_id *of_id =
+			of_match_device(ath79_gpio_of_match, &pdev->dev);
+		if (!of_id) {
+			dev_err(&pdev->dev, "Error: No device match found\n");
+			return -ENODEV;
+		}
+		ath79_gpio_count = (unsigned long)of_id->data;
+	} else if (soc_is_ar71xx())
 		ath79_gpio_count = AR71XX_GPIO_COUNT;
 	else if (soc_is_ar7240())
 		ath79_gpio_count = AR7240_GPIO_COUNT;
@@ -199,7 +241,13 @@ void __init ath79_gpio_init(void)
 	else
 		BUG();
 
-	ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	ath79_gpio_base = devm_ioremap_nocache(
+		&pdev->dev, res->start, resource_size(res));
+	if (!ath79_gpio_base)
+		return -ENOMEM;
+
+	ath79_gpio_chip.dev = &pdev->dev;
 	ath79_gpio_chip.ngpio = ath79_gpio_count;
 	if (soc_is_ar934x() || soc_is_qca955x()) {
 		ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
@@ -207,10 +255,25 @@ void __init ath79_gpio_init(void)
 	}
 
 	err = gpiochip_add(&ath79_gpio_chip);
-	if (err)
-		panic("cannot add AR71xx GPIO chip, error=%d", err);
+	if (err) {
+		dev_err(&pdev->dev,
+			"cannot add AR71xx GPIO chip, error=%d", err);
+		return err;
+	}
+
+	return 0;
 }
 
+static struct platform_driver ath79_gpio_driver = {
+	.driver = {
+		.name = "ath79-gpio",
+		.of_match_table	= ath79_gpio_of_match,
+	},
+	.probe = ath79_gpio_probe,
+};
+
+module_platform_driver(ath79_gpio_driver);
+
 int gpio_get_value(unsigned gpio)
 {
 	if (gpio < ath79_gpio_count)
-- 
2.0.0

Re: [PATCH 11/14] MIPS: ath79: Add OF support to the GPIO driver

[Arnd Bergmann]

On Friday 17 April 2015 16:24:26 Alban Bedel wrote:
> Replace the simple GPIO chip registration by a platform driver
> and make ath79_gpio_init() just register the device.
> 
> Signed-off-by: Alban Bedel <albeu@free.fr>
> ---
>  arch/mips/ath79/dev-common.c | 13 ++++++++
>  arch/mips/ath79/gpio.c       | 73 +++++++++++++++++++++++++++++++++++++++++---
>  2 files changed, 81 insertions(+), 5 deletions(-)

Could you move the driver to drivers/gpio/ now?

> +void __init ath79_gpio_init(void)
> +{
> +	struct resource res;
> +
> +	memset(&res, 0, sizeof(res));
> +
> +	res.flags = IORESOURCE_MEM;
> +	res.start = AR71XX_GPIO_BASE;
> +	res.end = res.start + AR71XX_GPIO_SIZE - 1;
> +
> +	platform_device_register_simple("ath79-gpio", -1, &res, 1);
> +}

Your code looks correct, but could be shortened to 

	struct resource mem = DEFINE_RES_MEM(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);

>  
> -void __init ath79_gpio_init(void)
> +static const struct of_device_id ath79_gpio_of_match[] = {
> +	{
> +		.compatible = "qca,ar7100-gpio",
> +		.data = (void *)AR71XX_GPIO_COUNT,
> +	},
> +	{
> +		.compatible = "qca,ar7240-gpio",
> +		.data = (void *)AR7240_GPIO_COUNT,
> +	},
> +	{
> +		.compatible = "qca,ar7241-gpio",
> +		.data = (void *)AR7241_GPIO_COUNT,
> +	},
> +	{
> +		.compatible = "qca,ar9130-gpio",
> +		.data = (void *)AR913X_GPIO_COUNT,
> +	},
> +	{
> +		.compatible = "qca,ar9330-gpio",
> +		.data = (void *)AR933X_GPIO_COUNT,
> +	},
> +	{
> +		.compatible = "qca,ar9340-gpio",
> +		.data = (void *)AR934X_GPIO_COUNT,
> +	},
> +	{
> +		.compatible = "qca,qca9550-gpio",
> +		.data = (void *)QCA955X_GPIO_COUNT,
> +	},
> +	{},
> +};

How about putting the number into an 'ngpios' property like some other
bindings do?

	Arnd

Re: [PATCH 11/14] MIPS: ath79: Add OF support to the GPIO driver

[Alban]

On Fri, 17 Apr 2015 16:53:31 +0200
Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> wrote:

> On Friday 17 April 2015 16:24:26 Alban Bedel wrote:
> > Replace the simple GPIO chip registration by a platform driver
> > and make ath79_gpio_init() just register the device.
> > 
> > Signed-off-by: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
> > ---
> >  arch/mips/ath79/dev-common.c | 13 ++++++++
> >  arch/mips/ath79/gpio.c       | 73
> > +++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 81
> > insertions(+), 5 deletions(-)
> 
> Could you move the driver to drivers/gpio/ now?

Sure, I'll add a patch to move it there.

> > +void __init ath79_gpio_init(void)
> > +{
> > +	struct resource res;
> > +
> > +	memset(&res, 0, sizeof(res));
> > +
> > +	res.flags = IORESOURCE_MEM;
> > +	res.start = AR71XX_GPIO_BASE;
> > +	res.end = res.start + AR71XX_GPIO_SIZE - 1;
> > +
> > +	platform_device_register_simple("ath79-gpio", -1, &res, 1);
> > +}
> 
> Your code looks correct, but could be shortened to 
> 
> 	struct resource mem = DEFINE_RES_MEM(AR71XX_GPIO_BASE,
> AR71XX_GPIO_SIZE);

I'll do that.

> >  
> > -void __init ath79_gpio_init(void)
> > +static const struct of_device_id ath79_gpio_of_match[] = {
> > +	{
> > +		.compatible = "qca,ar7100-gpio",
> > +		.data = (void *)AR71XX_GPIO_COUNT,
> > +	},
> > +	{
> > +		.compatible = "qca,ar7240-gpio",
> > +		.data = (void *)AR7240_GPIO_COUNT,
> > +	},
> > +	{
> > +		.compatible = "qca,ar7241-gpio",
> > +		.data = (void *)AR7241_GPIO_COUNT,
> > +	},
> > +	{
> > +		.compatible = "qca,ar9130-gpio",
> > +		.data = (void *)AR913X_GPIO_COUNT,
> > +	},
> > +	{
> > +		.compatible = "qca,ar9330-gpio",
> > +		.data = (void *)AR933X_GPIO_COUNT,
> > +	},
> > +	{
> > +		.compatible = "qca,ar9340-gpio",
> > +		.data = (void *)AR934X_GPIO_COUNT,
> > +	},
> > +	{
> > +		.compatible = "qca,qca9550-gpio",
> > +		.data = (void *)QCA955X_GPIO_COUNT,
> > +	},
> > +	{},
> > +};
> 
> How about putting the number into an 'ngpios' property like some other
> bindings do?

I'll do that, it would make things simpler.

Alban
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[PATCH 12/14] MIPS: Add a basic dtsi for the AR9132

[Alban Bedel]

A basic dtsi for the AR9132 with support for the DDR controller, CPU
and MISC interrupt controller, GPIO controller, the UART and the
watchdog.

Signed-off-by: Alban Bedel <albeu@free.fr>
---
 arch/mips/boot/dts/ar9132.dtsi | 119 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 119 insertions(+)
 create mode 100644 arch/mips/boot/dts/ar9132.dtsi

diff --git a/arch/mips/boot/dts/ar9132.dtsi b/arch/mips/boot/dts/ar9132.dtsi
new file mode 100644
index 0000000..ede58cd
--- /dev/null
+++ b/arch/mips/boot/dts/ar9132.dtsi
@@ -0,0 +1,119 @@
+/ {
+	compatible = "qca,ar9132";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "mips,mips24Kc";
+			reg = <0>;
+		};
+	};
+
+	cpuintc: cpuintc {
+		compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
+		qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
+					<&ddr_ctrl 0>, <&ddr_ctrl 1>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		ranges;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		interrupt-parent = <&cpuintc>;
+
+		apb {
+			compatible = "simple-bus";
+			ranges;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			interrupt-parent = <&miscintc>;
+
+			ddr_ctrl: ddr-controller@18000000 {
+				compatible = "qca,ar9132-ddr-controller",
+						"qca,ar7240-ddr-controller";
+				reg = <0x18000000 0x100>;
+
+				#qca,ddr-wb-channel-cells = <1>;
+			};
+
+			uart@18020000 {
+				compatible = "ns8250";
+				reg = <0x18020000 0x20>;
+				interrupts = <3>;
+
+				clocks = <&pll 2>;
+				clock-names = "uart";
+
+				reg-io-width = <4>;
+				reg-shift = <2>;
+				no-loopback-test;
+
+				status = "disabled";
+			};
+
+			gpio: gpio@18040000 {
+				compatible = "qca,ar9132-gpio",
+						"qca,ar9130-gpio";
+				reg = <0x18040000 0x30>;
+				interrupts = <2>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			pll: pll-controller@18050000 {
+				compatible = "qca,ar9132-ppl",
+						"qca,ar9130-pll";
+				reg = <0x18050000 0x20>;
+
+				clock-names = "ref";
+				/* The board must provides the ref clock */
+
+				#clock-cells = <1>;
+				clock-output-names = "cpu", "ddr", "ahb";
+			};
+
+			wdt@18060008 {
+				compatible = "qca,ar7130-wdt";
+				reg = <0x18060008 0x8>;
+
+				interrupts = <4>;
+
+				clocks = <&pll 2>;
+				clock-names = "wdt";
+			};
+
+			miscintc: miscintc@18060010 {
+				compatible = "qca,ar9132-misc-intc",
+					   qca,ar7100-misc-intc";
+				reg = <0x18060010 0x4>;
+
+				interrupt-parent = <&cpuintc>;
+				interrupts = <6>;
+
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+		};
+	};
+};
-- 
2.0.0

[PATCH 13/14] of: Add vendor prefix for TP-Link Technologies Co. Ltd

[Alban Bedel]

Signed-off-by: Alban Bedel <albeu@free.fr>
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index b13aa55..9e965b6 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -185,6 +185,7 @@ tbs	TBS Technologies
 thine	THine Electronics, Inc.
 ti	Texas Instruments
 tlm	Trusted Logic Mobility
+tplink	TP-LINK Technologies Co., Ltd.
 toradex	Toradex AG
 toshiba	Toshiba Corporation
 toumaz	Toumaz
-- 
2.0.0

Re: [PATCH 13/14] of: Add vendor prefix for TP-Link Technologies Co. Ltd

[Rob Herring]

On Sat, Apr 18, 2015 at 11:13 AM, Alban Bedel <albeu-GANU6spQydw@public.gmane.org> wrote:
> Signed-off-by: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index b13aa55..9e965b6 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -185,6 +185,7 @@ tbs TBS Technologies
>  thine  THine Electronics, Inc.
>  ti     Texas Instruments
>  tlm    Trusted Logic Mobility
> +tplink TP-LINK Technologies Co., Ltd.

Alphabetical order please.

Rob

>  toradex        Toradex AG
>  toshiba        Toshiba Corporation
>  toumaz Toumaz
> --
> 2.0.0
>
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[PATCH 14/14] MIPS: Add basic support for the TL-WR1043ND version 1

[Alban Bedel]

Add a DTS for TL-WR1043ND version 1 and allow to have it built in the
kernel to circumvent the broken u-boot found on these boards.
Currently only the UART, LEDs and buttons are supported.

Signed-off-by: Alban Bedel <albeu@free.fr>
---
 arch/mips/ath79/Kconfig                      |  5 ++
 arch/mips/boot/dts/Makefile                  |  1 +
 arch/mips/boot/dts/ar9132_tl_wr1043nd_v1.dts | 83 ++++++++++++++++++++++++++++
 3 files changed, 89 insertions(+)
 create mode 100644 arch/mips/boot/dts/ar9132_tl_wr1043nd_v1.dts

diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig
index 1d38c6a..0df05d0 100644
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
@@ -79,6 +79,11 @@ choice
 
 	config DTB_ATH79_NONE
 		bool "None"
+
+	config DTB_TL_WR1043ND_V1
+		bool "TL-WR1043ND Version 1"
+		select BUILTIN_DTB
+		select SOC_AR913X
 endchoice
 
 endmenu
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index 4f49fa4..d40aae2 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -10,6 +10,7 @@ dtb-$(CONFIG_DTB_RT305X_EVAL)		+= rt3052_eval.dtb
 dtb-$(CONFIG_DTB_RT3883_EVAL)		+= rt3883_eval.dtb
 dtb-$(CONFIG_DTB_MT7620A_EVAL)		+= mt7620a_eval.dtb
 dtb-$(CONFIG_MIPS_SEAD3)		+= sead3.dtb
+dtb-$(CONFIG_DTB_TL_WR1043ND_V1)	+= ar9132_tl_wr1043nd.dtb
 
 obj-y		+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))
 
diff --git a/arch/mips/boot/dts/ar9132_tl_wr1043nd_v1.dts b/arch/mips/boot/dts/ar9132_tl_wr1043nd_v1.dts
new file mode 100644
index 0000000..ab36c7c
--- /dev/null
+++ b/arch/mips/boot/dts/ar9132_tl_wr1043nd_v1.dts
@@ -0,0 +1,83 @@
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9132.dtsi"
+
+/ {
+	compatible = "tplink,tl-wr1043nd-v1", "qca,ar9132";
+	model = "TP-Link TL-WR1043ND Version 1";
+
+	alias {
+		serial0 = "/ahb/apb/uart@18020000";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x2000000>;
+	};
+
+	extosc: oscillator {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <40000000>;
+	};
+
+	ahb {
+		apb {
+			uart@18020000 {
+				status = "okay";
+			};
+
+			pll-controller@18050000 {
+				clocks = <&extosc>;
+			};
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		poll-interval = <20>;
+		button@0 {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
+			debounce-interval = <60>;
+		};
+
+		button@1 {
+			label = "qss";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
+			debounce-interval = <60>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led@0 {
+			label = "tp-link:green:usb";
+			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+		};
+
+		led@1 {
+			label = "tp-link:green:system";
+			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "heartbeat";
+		};
+
+		led@2 {
+			label = "tp-link:green:qss";
+			gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+		};
+
+		led@3 {
+			label = "tp-link:green:wlan";
+			gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
-- 
2.0.0

Re: [PATH] MIPS: ath79: Add OF support and DTS for TL-WR1043ND

[Florian Fainelli]

Le 17/04/2015 07:24, Alban Bedel a écrit :
> This series add OF bindings and code support for the interrupt
> controllers, clocks and GPIOs. However it was only tested on a
> TL-WR1043ND with an AR9132, others SoCs are untested, and a few are
> not supported at all.
> 
> Most code changes base on the previous bug fix series:
> [PATH] MIPS: ath79: Various small fix to prepare OF support

Any reasons why Gabor Juhos is not CC'd on these patches?
--
Florian

Re: [PATH] MIPS: ath79: Add OF support and DTS for TL-WR1043ND

[Alban]

On Sat, 18 Apr 2015 13:33:20 -0700
Florian Fainelli <f.fainelli@gmail.com> wrote:

> Le 17/04/2015 07:24, Alban Bedel a écrit :
> > This series add OF bindings and code support for the interrupt
> > controllers, clocks and GPIOs. However it was only tested on a
> > TL-WR1043ND with an AR9132, others SoCs are untested, and a few are
> > not supported at all.
> > 
> > Most code changes base on the previous bug fix series:
> > [PATH] MIPS: ath79: Various small fix to prepare OF support
> 
> Any reasons why Gabor Juhos is not CC'd on these patches?

Because get_maintainer.pl didn't return him, I'll add him from now on.

Alban