[PATCH] powerpc/dts: Move pll0/1-div4 index

[PATCH] powerpc/dts: Move pll0/1-div4 index

[Igal.Liberman]

From: Igal Liberman <Igal.Liberman@freescale.com>

This patch updates pll0/1-div4 index to '3'.
Originally it was '2'.

The following patch adds pll0/1-div3 option:
	https://patchwork.ozlabs.org/patch/461151/
After this patch, index '2' becomes pll0/1-div3.

This patch based on top of the following:
	https://patchwork.ozlabs.org/patch/461811/

Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
---
 arch/powerpc/boot/dts/fsl/b4si-post.dtsi    |    4 ++--
 arch/powerpc/boot/dts/fsl/t2081si-post.dtsi |    8 ++++----
 arch/powerpc/boot/dts/fsl/t4240si-post.dtsi |    8 ++++----
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index 8d061a4..d6c410d 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -446,8 +446,8 @@
 			#clock-cells = <0>;
 			reg = <0x0 0x4>;
 			compatible = "fsl,qoriq-core-mux-2.0";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
-				<&pll1 0>, <&pll1 1>, <&pll1 2>;
+			clocks = <&pll0 0>, <&pll0 1>, <&pll0 3>,
+				<&pll1 0>, <&pll1 1>, <&pll1 3>;
 			clock-names = "pll0", "pll0-div2", "pll0-div4",
 				"pll1", "pll1-div2", "pll1-div4";
 			clock-output-names = "cmux0";
diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
index 1462431..e347f2d 100644
--- a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
@@ -587,8 +587,8 @@
 			#clock-cells = <0>;
 			reg = <0x0 4>;
 			compatible = "fsl,qoriq-core-mux-2.0";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
-				 <&pll1 0>, <&pll1 1>, <&pll1 2>;
+			clocks = <&pll0 0>, <&pll0 1>, <&pll0 3>,
+				 <&pll1 0>, <&pll1 1>, <&pll1 3>;
 			clock-names = "pll0", "pll0-div2", "pll0-div4",
 				"pll1", "pll1-div2", "pll1-div4";
 			clock-output-names = "cmux0";
@@ -598,8 +598,8 @@
 			#clock-cells = <0>;
 			reg = <0x20 4>;
 			compatible = "fsl,qoriq-core-mux-2.0";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
-				 <&pll1 0>, <&pll1 1>, <&pll1 2>;
+			clocks = <&pll0 0>, <&pll0 1>, <&pll0 3>,
+				 <&pll1 0>, <&pll1 1>, <&pll1 3>;
 			clock-names = "pll0", "pll0-div2", "pll0-div4",
 				"pll1", "pll1-div2", "pll1-div4";
 			clock-output-names = "cmux1";
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index 1c91d00..1fdce44 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -1099,8 +1099,8 @@
 			#clock-cells = <0>;
 			reg = <0x0 0x4>;
 			compatible = "fsl,qoriq-core-mux-2.0";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
-				<&pll1 0>, <&pll1 1>, <&pll1 2>,
+			clocks = <&pll0 0>, <&pll0 1>, <&pll0 3>,
+				<&pll1 0>, <&pll1 1>, <&pll1 3>,
 				<&pll2 0>, <&pll2 1>, <&pll2 2>;
 			clock-names = "pll0", "pll0-div2", "pll0-div4",
 				"pll1", "pll1-div2", "pll1-div4",
@@ -1112,8 +1112,8 @@
 			#clock-cells = <0>;
 			reg = <0x20 0x4>;
 			compatible = "fsl,qoriq-core-mux-2.0";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
-				<&pll1 0>, <&pll1 1>, <&pll1 2>,
+			clocks = <&pll0 0>, <&pll0 1>, <&pll0 3>,
+				<&pll1 0>, <&pll1 1>, <&pll1 3>,
 				<&pll2 0>, <&pll2 1>, <&pll2 2>;
 			clock-names = "pll0", "pll0-div2", "pll0-div4",
 				"pll1", "pll1-div2", "pll1-div4",
-- 
1.7.9.5

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Re: [PATCH] powerpc/dts: Move pll0/1-div4 index

[Scott Wood]

On Thu, 2015-04-16 at 15:08 +0300, Igal.Liberman wrote:
> From: Igal Liberman <Igal.Liberman@freescale.com>
> 
> This patch updates pll0/1-div4 index to '3'.
> Originally it was '2'.
> 
> The following patch adds pll0/1-div3 option:
> 	https://patchwork.ozlabs.org/patch/461151/
> After this patch, index '2' becomes pll0/1-div3.
> 
> This patch based on top of the following:
> 	https://patchwork.ozlabs.org/patch/461811/
> 
> Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>

This needs to be done in the same patch as the provider change, to avoid
a buggy intermediate state.

Will there be a new binding patch coming?

-Scott


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RE: [PATCH] powerpc/dts: Move pll0/1-div4 index

[Igal.Liberman-KZfg59tc24xl57MIdRCFDg]

Regards,
Igal Liberman.

> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Friday, April 17, 2015 8:42 AM
> To: Liberman Igal-B31950
> Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH] powerpc/dts: Move pll0/1-div4 index
> 
> On Thu, 2015-04-16 at 15:08 +0300, Igal.Liberman wrote:
> > From: Igal Liberman <Igal.Liberman@freescale.com>
> >
> > This patch updates pll0/1-div4 index to '3'.
> > Originally it was '2'.
> >
> > The following patch adds pll0/1-div3 option:
> > 	https://patchwork.ozlabs.org/patch/461151/
> > After this patch, index '2' becomes pll0/1-div3.
> >
> > This patch based on top of the following:
> > 	https://patchwork.ozlabs.org/patch/461811/
> >
> > Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
> 
> This needs to be done in the same patch as the provider change, to avoid a
> buggy intermediate state.
> 
> Will there be a new binding patch coming?
> 

OK, I'll add those changes as on patch.

Regarding the binding,
I already submitted https://patchwork.ozlabs.org/patch/461150/
Do you mean that I should add comment that the driver parses the node by reading the number of input clocks and not the compatible?

> -Scott
> 

Igal

Re: [PATCH] powerpc/dts: Move pll0/1-div4 index

[Scott Wood]

On Mon, 2015-04-20 at 06:10 -0500, Liberman Igal-B31950 wrote:
> 
> 
> Regards,
> Igal Liberman.
> 
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: Friday, April 17, 2015 8:42 AM
> > To: Liberman Igal-B31950
> > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
> > Subject: Re: [PATCH] powerpc/dts: Move pll0/1-div4 index
> > 
> > On Thu, 2015-04-16 at 15:08 +0300, Igal.Liberman wrote:
> > > From: Igal Liberman <Igal.Liberman-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> > >
> > > This patch updates pll0/1-div4 index to '3'.
> > > Originally it was '2'.
> > >
> > > The following patch adds pll0/1-div3 option:
> > > 	https://patchwork.ozlabs.org/patch/461151/
> > > After this patch, index '2' becomes pll0/1-div3.
> > >
> > > This patch based on top of the following:
> > > 	https://patchwork.ozlabs.org/patch/461811/
> > >
> > > Signed-off-by: Igal Liberman <Igal.Liberman-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> > 
> > This needs to be done in the same patch as the provider change, to avoid a
> > buggy intermediate state.
> > 
> > Will there be a new binding patch coming?
> > 
> 
> OK, I'll add those changes as on patch.
> 
> Regarding the binding,
> I already submitted https://patchwork.ozlabs.org/patch/461150/

Which is an incompatible change as I noted in a comment on a different
patch.

> Do you mean that I should add comment that the driver parses the node by reading the number of input clocks and not the compatible?

No, you should make the binding document reflect how things currently
work.

-Scott


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