From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paul Burton Subject: [PATCH v4 10/37] devicetree: document Ingenic SoC interrupt controller binding Date: Fri, 24 Apr 2015 14:17:10 +0100 Message-ID: <1429881457-16016-11-git-send-email-paul.burton@imgtec.com> References: <1429881457-16016-1-git-send-email-paul.burton@imgtec.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1429881457-16016-1-git-send-email-paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org Cc: Paul Burton , Ian Campbell , Jason Cooper , Kumar Gala , Lars-Peter Clausen , Mark Rutland , Pawel Moll , Rob Herring , Thomas Gleixner , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org Add binding documentation for Ingenic SoC interrupt controllers. Signed-off-by: Paul Burton Acked-by: Rob Herring Cc: Ian Campbell Cc: Jason Cooper Cc: Kumar Gala Cc: Lars-Peter Clausen Cc: Mark Rutland Cc: Pawel Moll Cc: Rob Herring Cc: Thomas Gleixner Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org --- Changes in v4: - s/intc/interrupt-controller/ in example. Changes in v3: - Merge documentation for various Ingenic SoCs, which only differ by their compatible strings. Changes in v2: - None. --- .../bindings/interrupt-controller/ingenic,intc.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt new file mode 100644 index 0000000..c396fa0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt @@ -0,0 +1,25 @@ +Ingenic SoC Interrupt Controller + +Required properties: + +- compatible : should be "ingenic,-intc". For example + "ingenic,jz4740-intc" or "ingenic,jz4780-intc". +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1. +- interrupt-parent : phandle of the CPU interrupt controller. +- interrupts : Specifies the CPU interrupt the controller is connected to. + +Example: + +intc: interrupt-controller@10001000 { + compatible = "ingenic,jz4740-intc"; + reg = <0x10001000 0x14>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; +}; -- 2.3.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html