From: Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
To: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
Cc: Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>,
Ian Campbell
<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>,
Ralf Baechle <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: [PATCH v4 07/37] MIPS: JZ4740: probe CPU interrupt controller via DT
Date: Fri, 24 Apr 2015 14:17:07 +0100 [thread overview]
Message-ID: <1429881457-16016-8-git-send-email-paul.burton@imgtec.com> (raw)
In-Reply-To: <1429881457-16016-1-git-send-email-paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
Use the generic irqchip_init function to probe irqchip drivers using DT,
and add the appropriate node to the JZ4740 devicetree in place of the
call to mips_cpu_irq_init.
Signed-off-by: Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
Cc: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Cc: Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
Cc: Ralf Baechle <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
---
Changes in v4:
- None.
Changes in v3:
- Rebase.
Changes in v2:
- None.
---
arch/mips/boot/dts/ingenic/jz4740.dtsi | 7 +++++++
arch/mips/jz4740/irq.c | 4 ++--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi b/arch/mips/boot/dts/ingenic/jz4740.dtsi
index c538691f..2d64765c 100644
--- a/arch/mips/boot/dts/ingenic/jz4740.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi
@@ -2,4 +2,11 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "ingenic,jz4740";
+
+ cpuintc: cpuintc@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
};
diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c
index 97206b3..3ec90875 100644
--- a/arch/mips/jz4740/irq.c
+++ b/arch/mips/jz4740/irq.c
@@ -18,6 +18,7 @@
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
+#include <linux/irqchip.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/delay.h>
@@ -27,7 +28,6 @@
#include <asm/io.h>
#include <asm/mipsregs.h>
-#include <asm/irq_cpu.h>
#include <asm/mach-jz4740/base.h>
#include <asm/mach-jz4740/irq.h>
@@ -84,7 +84,7 @@ void __init arch_init_irq(void)
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
- mips_cpu_irq_init();
+ irqchip_init();
jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
--
2.3.5
--
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next prev parent reply other threads:[~2015-04-24 13:17 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-24 13:17 [PATCH v4 00/37] JZ4780 & CI20 support Paul Burton
[not found] ` <1429881457-16016-1-git-send-email-paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
2015-04-24 13:17 ` [PATCH v4 01/37] devicetree/bindings: add Ingenic Semiconductor vendor prefix Paul Burton
2015-04-24 13:17 ` [PATCH v4 02/37] devicetree/bindings: add Qi Hardware " Paul Burton
2015-04-24 13:17 ` [PATCH v4 05/37] MIPS: JZ4740: require & include DT Paul Burton
2015-04-24 13:17 ` Paul Burton [this message]
2015-04-24 13:17 ` [PATCH v4 10/37] devicetree: document Ingenic SoC interrupt controller binding Paul Burton
2015-04-24 13:17 ` [PATCH v4 11/37] MIPS: JZ4740: probe interrupt controller via DT Paul Burton
2015-04-24 13:17 ` [PATCH v4 24/37] devicetree: add Ingenic CGU binding documentation Paul Burton
2015-04-24 13:17 ` [PATCH v4 26/37] MIPS,clk: migrate JZ4740 to common clock framework Paul Burton
[not found] ` <1429881457-16016-27-git-send-email-paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
2015-05-13 2:52 ` Michael Turquette
2015-05-24 15:01 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 33/37] devicetree: document Ingenic SoC UART binding Paul Burton
2015-04-24 13:17 ` [PATCH v4 35/37] MIPS: JZ4740: use Ingenic SoC UART driver Paul Burton
2015-04-24 13:17 ` [PATCH v4 36/37] MIPS: ingenic: initial JZ4780 support Paul Burton
[not found] ` <1429881457-16016-37-git-send-email-paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
2015-04-28 10:36 ` James Hogan
2015-04-24 13:17 ` [PATCH v4 37/37] MIPS: ingenic: initial MIPS Creator CI20 support Paul Burton
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