From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Jon Medhurst (Tixy)" <tixy@linaro.org>
Subject: Re: [PATCH v2 3/5] arm64: Juno: Add memory mapped timer node
Date: Tue, 19 May 2015 11:56:43 +0100
Message-ID: <1432033003.3047.43.camel@linaro.org>
References: <1431970109-8902-1-git-send-email-Liviu.Dudau@arm.com>
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To: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Arnd Bergmann <arnd@arndb.de>, Olof Johansson <olof@lixom.net>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Ian Campbell <ijc+devicetree@hellion.org.uk>, Marc Zyngier <marc.zyngier@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will.deacon@arm.com>, Sudeep Holla <sudeep.holla@arm.com>, devicetree <devicetree@vger.kernel.org>, LAKML <linux-arm-kernel@lists.infradead.org>, LKML <linux-kernel@vger.kernel.org>
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On Mon, 2015-05-18 at 18:28 +0100, Liviu Dudau wrote:
> Juno based boards have a memory mapped timer @ 0x2a810000. This
> is disabled on r0 version of the board due to an SoC errata.

So wouldn't it make more sense then to disable it in the dts for r0? As
it is, you disable it in the common file below then have to later
re-enable it in juno-r1.dts.

Apart from that, the whole series looks good to be and I've given it a
spin on r0 and r1. So consider that an
Acked-by: Jon Medhurst <tixy@linaro.org>


> 
> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
> ---
>  arch/arm64/boot/dts/arm/juno-base.dtsi | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
> index 5c4c035..b7e862f 100644
> --- a/arch/arm64/boot/dts/arm/juno-base.dtsi
> +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
> @@ -2,6 +2,21 @@
>  	 *  Devices shared by all Juno boards
>  	 */
>  
> +	memtimer: timer@2a810000 {
> +		compatible = "arm,armv7-timer-mem";
> +		reg = <0x0 0x2a810000 0x0 0x10000>;
> +		clock-frequency = <50000000>;


> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +		status = "disabled";
> +		frame@2a830000 {
> +			frame-number = <1>;
> +			interrupts = <0 60 4>;
> +			reg = <0x0 0x2a830000 0x0 0x10000>;
> +		};
> +	};
> +
>  	gic: interrupt-controller@2c010000 {
>  		compatible = "arm,gic-400", "arm,cortex-a15-gic";
>  		reg = <0x0 0x2c010000 0 0x1000>,