[PATCH RESEND v7 0/2] Add SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller.

[PATCH RESEND v7 0/2] Add SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller.

[Suman Tripathi]

This patch adds the SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller.

v1 change:
 * Use the CONFIG_ARM64_DMA_HAS_IOMMU for dma-mapping.

v2 change:
 * Drop the IOMMU support and switching to PIO mode for arasan.
   controller integrated inside APM X-Gene SoC.

v3 change:
 * Change the sdhci-of-arasan.c to support arasan4.9a.
 * Add quirks for arasan4.9a.

v4 change:
 * Cleanup the Documentation and dts.

v5 change:
 * Rebase the dts files.
 * Drop patch 2 and 3 as it is applied.

v6 change:
 * Clean the unrequired properties from dts.
 * Rename sdhc to sdhci.
 * support to disable timming using capability register read.

v7 change:
 * Rename sdhci nodes to mmc.

Signed-off-by: Suman Tripathi <stripathi@apm.com>
---
Suman Tripathi (2):
  arm64: dts: Add the arasan mmc nodes in apm-storm.dtsi
  mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on
    capability register 0.

 arch/arm64/boot/dts/apm/apm-mustang.dts |  4 +++
 arch/arm64/boot/dts/apm/apm-storm.dtsi  | 43 +++++++++++++++++++++++++++++++++
 drivers/mmc/host/sdhci.c                |  3 ++-
 3 files changed, 49 insertions(+), 1 deletion(-)

--
1.8.2.1

[PATCH RESEND v7 1/2] arm64: dts: Add the arasan mmc nodes in apm-storm.dtsi

[Suman Tripathi]

This patch adds the arasan mmc nodes to reuse the of-arasan
driver for APM X-Gene SoC.

Signed-off-by: Suman Tripathi <stripathi@apm.com>
---
---
 arch/arm64/boot/dts/apm/apm-mustang.dts |  4 +++
 arch/arm64/boot/dts/apm/apm-storm.dtsi  | 43 +++++++++++++++++++++++++++++++++
 2 files changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts b/arch/arm64/boot/dts/apm/apm-mustang.dts
index 83578e7..7a3ea72 100644
--- a/arch/arm64/boot/dts/apm/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
@@ -52,3 +52,7 @@
 &xgenet {
 	status = "ok";
 };
+
+&mmc0 {
+	status = "ok";
+};
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index c8d3e0e..8e03ecd 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -145,6 +145,40 @@
 				clock-output-names = "socplldiv2";
 			};

+			ahbclk: ahbclk@1f2ac000 {
+				compatible = "apm,xgene-device-clock";
+				#clock-cells = <1>;
+				clocks = <&socplldiv2 0>;
+				reg = <0x0 0x1f2ac000 0x0 0x1000
+					0x0 0x17000000 0x0 0x2000>;
+				reg-names = "csr-reg", "div-reg";
+				csr-offset = <0x0>;
+				csr-mask = <0x1>;
+				enable-offset = <0x8>;
+				enable-mask = <0x1>;
+				divider-offset = <0x164>;
+				divider-width = <0x5>;
+				divider-shift = <0x0>;
+				clock-output-names = "ahbclk";
+			};
+
+			sdioclk: sdioclk@1f2ac000 {
+				compatible = "apm,xgene-device-clock";
+				#clock-cells = <1>;
+				clocks = <&socplldiv2 0>;
+				reg = <0x0 0x1f2ac000 0x0 0x1000
+					0x0 0x17000000 0x0 0x2000>;
+				reg-names = "csr-reg", "div-reg";
+				csr-offset = <0x0>;
+				csr-mask = <0x2>;
+				enable-offset = <0x8>;
+				enable-mask = <0x2>;
+				divider-offset = <0x178>;
+				divider-width = <0x8>;
+				divider-shift = <0x0>;
+				clock-output-names = "sdioclk";
+			};
+
 			qmlclk: qmlclk {
 				compatible = "apm,xgene-device-clock";
 				#clock-cells = <1>;
@@ -533,6 +567,15 @@
 			interrupts = <0x0 0x4f 0x4>;
 		};

+		mmc0: mmc@1c000000 {
+			compatible = "arasan,sdhci-4.9a";
+			reg = <0x0 0x1c000000 0x0 0x100>;
+			interrupts = <0x0 0x49 0x4>;
+			dma-coherent;
+			clock-names = "clk_xin", "clk_ahb";
+			clocks = <&sdioclk 0>, <&ahbclk 0>;
+		};
+
 		phy1: phy@1f21a000 {
 			compatible = "apm,xgene-phy";
 			reg = <0x0 0x1f21a000 0x0 0x100>;
--
1.8.2.1

Re: [PATCH RESEND v7 1/2] arm64: dts: Add the arasan mmc nodes in apm-storm.dtsi

[Suman Tripathi]

[-- Attachment #1.1: Type: text/plain, Size: 3947 bytes --]

Hi ,

On Thu, May 21, 2015 at 2:13 PM, Suman Tripathi <stripathi@apm.com> wrote:

> This patch adds the arasan mmc nodes to reuse the of-arasan
> driver for APM X-Gene SoC.
>
> Signed-off-by: Suman Tripathi <stripathi@apm.com>
> ---
> ---
>  arch/arm64/boot/dts/apm/apm-mustang.dts |  4 +++
>  arch/arm64/boot/dts/apm/apm-storm.dtsi  | 43
> +++++++++++++++++++++++++++++++++
>  2 files changed, 47 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts
> b/arch/arm64/boot/dts/apm/apm-mustang.dts
> index 83578e7..7a3ea72 100644
> --- a/arch/arm64/boot/dts/apm/apm-mustang.dts
> +++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
> @@ -52,3 +52,7 @@
>  &xgenet {
>         status = "ok";
>  };
> +
> +&mmc0 {
> +       status = "ok";
> +};
> diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
> b/arch/arm64/boot/dts/apm/apm-storm.dtsi
> index c8d3e0e..8e03ecd 100644
> --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
> +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
> @@ -145,6 +145,40 @@
>                                 clock-output-names = "socplldiv2";
>                         };
>
> +                       ahbclk: ahbclk@1f2ac000 {
> +                               compatible = "apm,xgene-device-clock";
> +                               #clock-cells = <1>;
> +                               clocks = <&socplldiv2 0>;
> +                               reg = <0x0 0x1f2ac000 0x0 0x1000
> +                                       0x0 0x17000000 0x0 0x2000>;
> +                               reg-names = "csr-reg", "div-reg";
> +                               csr-offset = <0x0>;
> +                               csr-mask = <0x1>;
> +                               enable-offset = <0x8>;
> +                               enable-mask = <0x1>;
> +                               divider-offset = <0x164>;
> +                               divider-width = <0x5>;
> +                               divider-shift = <0x0>;
> +                               clock-output-names = "ahbclk";
> +                       };
> +
> +                       sdioclk: sdioclk@1f2ac000 {
> +                               compatible = "apm,xgene-device-clock";
> +                               #clock-cells = <1>;
> +                               clocks = <&socplldiv2 0>;
> +                               reg = <0x0 0x1f2ac000 0x0 0x1000
> +                                       0x0 0x17000000 0x0 0x2000>;
> +                               reg-names = "csr-reg", "div-reg";
> +                               csr-offset = <0x0>;
> +                               csr-mask = <0x2>;
> +                               enable-offset = <0x8>;
> +                               enable-mask = <0x2>;
> +                               divider-offset = <0x178>;
> +                               divider-width = <0x8>;
> +                               divider-shift = <0x0>;
> +                               clock-output-names = "sdioclk";
> +                       };
> +
>                         qmlclk: qmlclk {
>                                 compatible = "apm,xgene-device-clock";
>                                 #clock-cells = <1>;
> @@ -533,6 +567,15 @@
>                         interrupts = <0x0 0x4f 0x4>;
>                 };
>
> +               mmc0: mmc@1c000000 {
> +                       compatible = "arasan,sdhci-4.9a";
> +                       reg = <0x0 0x1c000000 0x0 0x100>;
> +                       interrupts = <0x0 0x49 0x4>;
> +                       dma-coherent;
> +                       clock-names = "clk_xin", "clk_ahb";
> +                       clocks = <&sdioclk 0>, <&ahbclk 0>;
> +               };
> +
>                 phy1: phy@1f21a000 {
>                         compatible = "apm,xgene-phy";
>                         reg = <0x0 0x1f21a000 0x0 0x100>;
> --
> 1.8.2.1
>
>

Any comments on this patch ?? I changed the dts node name as per EPAR and
Arnd comments.
-- 
Thanks,
with regards,
Suman Tripathi

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[PATCH RESEND v7 2/2] mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.

[Suman Tripathi]

The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk.
This patch adds the support to disable SDR104/SDR50/DDR50 based on
reading the capability register 0.

Signed-off-by: Suman Tripathi <stripathi-qTEPVZfXA3Y@public.gmane.org>
---
---
 drivers/mmc/host/sdhci.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 58c1770..a3d9b8a 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3118,7 +3118,8 @@ int sdhci_add_host(struct sdhci_host *host)
 		}
 	}

-	if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
+	if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V ||
+	    !(caps[0] & SDHCI_CAN_VDD_180))
 		caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 		       SDHCI_SUPPORT_DDR50);

--
1.8.2.1

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Re: [PATCH RESEND v7 2/2] mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.

[Suman Tripathi]

On Thu, May 21, 2015 at 2:13 PM, Suman Tripathi <stripathi@apm.com> wrote:
> The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk.
> This patch adds the support to disable SDR104/SDR50/DDR50 based on
> reading the capability register 0.
>
> Signed-off-by: Suman Tripathi <stripathi@apm.com>
> ---
> ---
>  drivers/mmc/host/sdhci.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 58c1770..a3d9b8a 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -3118,7 +3118,8 @@ int sdhci_add_host(struct sdhci_host *host)
>                 }
>         }
>
> -       if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
> +       if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V ||
> +           !(caps[0] & SDHCI_CAN_VDD_180))
>                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
>                        SDHCI_SUPPORT_DDR50);
>
> --
> 1.8.2.1
>

Any comments on this patch ?


-- 
Thanks,
with regards,
Suman Tripathi
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Re: [PATCH RESEND v7 2/2] mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.

[Ulf Hansson]

On 21 May 2015 at 10:43, Suman Tripathi <stripathi@apm.com> wrote:
> The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk.
> This patch adds the support to disable SDR104/SDR50/DDR50 based on
> reading the capability register 0.
>
> Signed-off-by: Suman Tripathi <stripathi@apm.com>
> ---
> ---
>  drivers/mmc/host/sdhci.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 58c1770..a3d9b8a 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -3118,7 +3118,8 @@ int sdhci_add_host(struct sdhci_host *host)
>                 }
>         }
>
> -       if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
> +       if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V ||
> +           !(caps[0] & SDHCI_CAN_VDD_180))
>                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
>                        SDHCI_SUPPORT_DDR50);
>
> --
> 1.8.2.1
>

I have no problem with this patch, except that it would be nice to get
a few "tested by" to make sure it doesn't break UHS support for some
SoCs.

Kind regards
Uffe
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Re: [PATCH RESEND v7 2/2] mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.

[Suman Tripathi]

[-- Attachment #1.1: Type: text/plain, Size: 1384 bytes --]

On Tue, May 26, 2015 at 6:06 PM, Ulf Hansson <ulf.hansson@linaro.org> wrote:

> On 21 May 2015 at 10:43, Suman Tripathi <stripathi@apm.com> wrote:
> > The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk.
> > This patch adds the support to disable SDR104/SDR50/DDR50 based on
> > reading the capability register 0.
> >
> > Signed-off-by: Suman Tripathi <stripathi@apm.com>
> > ---
> > ---
> >  drivers/mmc/host/sdhci.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> > index 58c1770..a3d9b8a 100644
> > --- a/drivers/mmc/host/sdhci.c
> > +++ b/drivers/mmc/host/sdhci.c
> > @@ -3118,7 +3118,8 @@ int sdhci_add_host(struct sdhci_host *host)
> >                 }
> >         }
> >
> > -       if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
> > +       if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V ||
> > +           !(caps[0] & SDHCI_CAN_VDD_180))
> >                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
> >                        SDHCI_SUPPORT_DDR50);
> >
> > --
> > 1.8.2.1
> >
>
> I have no problem with this patch, except that it would be nice to get
> a few "tested by" to make sure it doesn't break UHS support for some
> SoCs.
>
> Kind regards
> Uffe
>

Can anyone test this in some other SoC ? Appreciate your help ..


-- 
Thanks,
with regards,
Suman Tripathi

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Re: [PATCH RESEND v7 2/2] mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.

[Suman Tripathi]

[-- Attachment #1.1: Type: text/plain, Size: 1620 bytes --]

Hi Aisheng,

On Wed, May 27, 2015 at 7:46 PM, Suman Tripathi <stripathi@apm.com> wrote:

>
>
> On Tue, May 26, 2015 at 6:06 PM, Ulf Hansson <ulf.hansson@linaro.org>
> wrote:
>
>> On 21 May 2015 at 10:43, Suman Tripathi <stripathi@apm.com> wrote:
>> > The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk.
>> > This patch adds the support to disable SDR104/SDR50/DDR50 based on
>> > reading the capability register 0.
>> >
>> > Signed-off-by: Suman Tripathi <stripathi@apm.com>
>> > ---
>> > ---
>> >  drivers/mmc/host/sdhci.c | 3 ++-
>> >  1 file changed, 2 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
>> > index 58c1770..a3d9b8a 100644
>> > --- a/drivers/mmc/host/sdhci.c
>> > +++ b/drivers/mmc/host/sdhci.c
>> > @@ -3118,7 +3118,8 @@ int sdhci_add_host(struct sdhci_host *host)
>> >                 }
>> >         }
>> >
>> > -       if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
>> > +       if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V ||
>> > +           !(caps[0] & SDHCI_CAN_VDD_180))
>> >                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50
>> |
>> >                        SDHCI_SUPPORT_DDR50);
>> >
>> > --
>> > 1.8.2.1
>> >
>>
>> I have no problem with this patch, except that it would be nice to get
>> a few "tested by" to make sure it doesn't break UHS support for some
>> SoCs.
>>
>> Kind regards
>> Uffe
>>
>
> Can anyone test this in some other SoC ? Appreciate your help ..
>
> Can you test this patch  on imx SoC ?

>
> --
> Thanks,
> with regards,
> Suman Tripathi
>



-- 
Thanks,
with regards,
Suman Tripathi

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Re: [PATCH RESEND v7 2/2] mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.

[Dong Aisheng]

On Mon, Jun 01, 2015 at 01:38:47PM +0530, Suman Tripathi wrote:
>    Hi Aisheng,
>    On Wed, May 27, 2015 at 7:46 PM, Suman Tripathi <[1]stripathi@apm.com>
>    wrote:
> 
>      On Tue, May 26, 2015 at 6:06 PM, Ulf Hansson <[2]ulf.hansson@linaro.org>
>      wrote:
> 
>        On 21 May 2015 at 10:43, Suman Tripathi <[3]stripathi@apm.com> wrote:
>        > The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk.
>        > This patch adds the support to disable SDR104/SDR50/DDR50 based on
>        > reading the capability register 0.
>        >
>        > Signed-off-by: Suman Tripathi <[4]stripathi@apm.com>
>        > ---
>        > ---
>        >  drivers/mmc/host/sdhci.c | 3 ++-
>        >  1 file changed, 2 insertions(+), 1 deletion(-)
>        >
>        > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
>        > index 58c1770..a3d9b8a 100644
>        > --- a/drivers/mmc/host/sdhci.c
>        > +++ b/drivers/mmc/host/sdhci.c
>        > @@ -3118,7 +3118,8 @@ int sdhci_add_host(struct sdhci_host *host)
>        >                 }
>        >         }
>        >
>        > -       if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
>        > +       if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V ||
>        > +           !(caps[0] & SDHCI_CAN_VDD_180))
>        >                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
>        SDHCI_SUPPORT_SDR50 |
>        >                        SDHCI_SUPPORT_DDR50);
>        >
>        > --
>        > 1.8.2.1
>        >
> 
>        I have no problem with this patch, except that it would be nice to get
>        a few "tested by" to make sure it doesn't break UHS support for some
>        SoCs.
> 
>        Kind regards
>        Uffe
> 
>      Can anyone test this in some other SoC ? Appreciate your help ..
> 
>    Can you test this patch  on imx SoC ?
> 

(Your email have some format issue.)

I have tested this patch and it does not break imx SoC.
You can add my tag.
Tested-by: Dong Aisheng <aisheng.dong@freescale.com>

However, it looks to me SDHCI_CAN_VDD_180 is only indicating the host VDD
capabiliies, not IO voltage capability.
SD3.0 cards require 1.8v IO voltage support.
So should this bit affect SD3.0 support?
e.g. some hosts can only work at VDD_330 (most VDD of SD slot on IMX boards
is using external regulator and is fixed to 3.3v), but it can support 1.8v
IO voltage, so it can support SD3.0 cards as well.

Ulf,
Can you help confirm it?

Regards
Dong Aisheng

>      --
>      Thanks,
>      with regards,
>      Suman Tripathi
> 
>    --
>    Thanks,
>    with regards,
>    Suman Tripathi
> 
> References
> 
>    Visible links
>    1. mailto:stripathi@apm.com
>    2. mailto:ulf.hansson@linaro.org
>    3. mailto:stripathi@apm.com
>    4. mailto:stripathi@apm.com
> perl: warning: Setting locale failed.
> perl: warning: Please check that your locale settings:
> 	LANGUAGE = (unset),
> 	LC_ALL = (unset),
> 	LC_TIME = "zh_CN.UTF-8",
> 	LC_MONETARY = "zh_CN.UTF-8",
> 	LC_ADDRESS = "zh_CN.UTF-8",
> 	LC_TELEPHONE = "zh_CN.UTF-8",
> 	LC_NAME = "zh_CN.UTF-8",
> 	LC_MEASUREMENT = "zh_CN.UTF-8",
> 	LC_IDENTIFICATION = "zh_CN.UTF-8",
> 	LC_NUMERIC = "zh_CN.UTF-8",
> 	LC_PAPER = "zh_CN.UTF-8",
> 	LANG = "en_US.UTF-8"
>     are supported and installed on your system.
> perl: warning: Falling back to the standard locale ("C").

Re: [PATCH RESEND v7 2/2] mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.

[Suman Tripathi]

On Fri, Jun 5, 2015 at 8:23 PM, Dong Aisheng <b29396@freescale.com> wrote:
>
> On Mon, Jun 01, 2015 at 01:38:47PM +0530, Suman Tripathi wrote:
> >    Hi Aisheng,
> >    On Wed, May 27, 2015 at 7:46 PM, Suman Tripathi <[1]stripathi@apm.com>
> >    wrote:
> >
> >      On Tue, May 26, 2015 at 6:06 PM, Ulf Hansson <[2]ulf.hansson@linaro.org>
> >      wrote:
> >
> >        On 21 May 2015 at 10:43, Suman Tripathi <[3]stripathi@apm.com> wrote:
> >        > The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk.
> >        > This patch adds the support to disable SDR104/SDR50/DDR50 based on
> >        > reading the capability register 0.
> >        >
> >        > Signed-off-by: Suman Tripathi <[4]stripathi@apm.com>
> >        > ---
> >        > ---
> >        >  drivers/mmc/host/sdhci.c | 3 ++-
> >        >  1 file changed, 2 insertions(+), 1 deletion(-)
> >        >
> >        > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> >        > index 58c1770..a3d9b8a 100644
> >        > --- a/drivers/mmc/host/sdhci.c
> >        > +++ b/drivers/mmc/host/sdhci.c
> >        > @@ -3118,7 +3118,8 @@ int sdhci_add_host(struct sdhci_host *host)
> >        >                 }
> >        >         }
> >        >
> >        > -       if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
> >        > +       if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V ||
> >        > +           !(caps[0] & SDHCI_CAN_VDD_180))
> >        >                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
> >        SDHCI_SUPPORT_SDR50 |
> >        >                        SDHCI_SUPPORT_DDR50);
> >        >
> >        > --
> >        > 1.8.2.1
> >        >
> >
> >        I have no problem with this patch, except that it would be nice to get
> >        a few "tested by" to make sure it doesn't break UHS support for some
> >        SoCs.
> >
> >        Kind regards
> >        Uffe
> >
> >      Can anyone test this in some other SoC ? Appreciate your help ..
> >
> >    Can you test this patch  on imx SoC ?
> >
>
> (Your email have some format issue.)

Yeah missed to sent in plain text mode.

>
> I have tested this patch and it does not break imx SoC.
> You can add my tag.
> Tested-by: Dong Aisheng <aisheng.dong@freescale.com>

Thanks Dong !!

>
> However, it looks to me SDHCI_CAN_VDD_180 is only indicating the host VDD
> capabiliies, not IO voltage capability.

Are you sure on this ?? If SDHCI host VDD is  1.8V then the cards are
also capable to operate at 1.8V ? Didn't understand what you mean by
IO voltage capability


> SD3.0 cards require 1.8v IO voltage support.
> So should this bit affect SD3.0 support?

The preset value resgister says that  SDR modes requires 1.8V and we
disable the modes based on capability or quirk.

> e.g. some hosts can only work at VDD_330 (most VDD of SD slot on IMX boards
> is using external regulator and is fixed to 3.3v), but it can support 1.8v
> IO voltage, so it can support SD3.0 cards as well.

Same for us but somehow 1.8v is broken in our version.  Yeah so those
host can still use 1.8V by not setting the quirk or not setting the
capability register.
>
> Ulf,
> Can you help confirm it?
>
> Regards
> Dong Aisheng
>
> >      --
> >      Thanks,
> >      with regards,
> >      Suman Tripathi
> >
> >    --
> >    Thanks,
> >    with regards,
> >    Suman Tripathi
> >
> > References
> >
> >    Visible links
> >    1. mailto:stripathi@apm.com
> >    2. mailto:ulf.hansson@linaro.org
> >    3. mailto:stripathi@apm.com
> >    4. mailto:stripathi@apm.com
> > perl: warning: Setting locale failed.
> > perl: warning: Please check that your locale settings:
> >       LANGUAGE = (unset),
> >       LC_ALL = (unset),
> >       LC_TIME = "zh_CN.UTF-8",
> >       LC_MONETARY = "zh_CN.UTF-8",
> >       LC_ADDRESS = "zh_CN.UTF-8",
> >       LC_TELEPHONE = "zh_CN.UTF-8",
> >       LC_NAME = "zh_CN.UTF-8",
> >       LC_MEASUREMENT = "zh_CN.UTF-8",
> >       LC_IDENTIFICATION = "zh_CN.UTF-8",
> >       LC_NUMERIC = "zh_CN.UTF-8",
> >       LC_PAPER = "zh_CN.UTF-8",
> >       LANG = "en_US.UTF-8"
> >     are supported and installed on your system.
> > perl: warning: Falling back to the standard locale ("C").




-- 
Thanks,
with regards,
Suman Tripathi

Re: [PATCH RESEND v7 2/2] mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.

[Ulf Hansson]

[...]

>> >
>> >    Can you test this patch  on imx SoC ?
>> >
>>
>> (Your email have some format issue.)
>
> Yeah missed to sent in plain text mode.
>
>>
>> I have tested this patch and it does not break imx SoC.
>> You can add my tag.
>> Tested-by: Dong Aisheng <aisheng.dong@freescale.com>
>
> Thanks Dong !!
>
>>
>> However, it looks to me SDHCI_CAN_VDD_180 is only indicating the host VDD
>> capabiliies, not IO voltage capability.

I think Dong is correct. I don't think SDHCI_CAN_VDD_180 is not
related to UHS modes at all.

At least the name of the field (SDHCI_CAN_VDD_180) indicates it's
about VDD/VCC, the core power and not the IO voltage.

> Are you sure on this ?? If SDHCI host VDD is  1.8V then the cards are
> also capable to operate at 1.8V ? Didn't understand what you mean by
> IO voltage capability
>
>
>> SD3.0 cards require 1.8v IO voltage support.
>> So should this bit affect SD3.0 support?
>
> The preset value resgister says that  SDR modes requires 1.8V and we
> disable the modes based on capability or quirk.

It requires 1.8V *IO voltage*, not VDD/VCC.

[...]

Kind regards
Uffe

Re: [PATCH RESEND v7 2/2] mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.

[Ulf Hansson]

On 8 June 2015 at 10:37, Ulf Hansson <ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> [...]
>
>>> >
>>> >    Can you test this patch  on imx SoC ?
>>> >
>>>
>>> (Your email have some format issue.)
>>
>> Yeah missed to sent in plain text mode.
>>
>>>
>>> I have tested this patch and it does not break imx SoC.
>>> You can add my tag.
>>> Tested-by: Dong Aisheng <aisheng.dong-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
>>
>> Thanks Dong !!
>>
>>>
>>> However, it looks to me SDHCI_CAN_VDD_180 is only indicating the host VDD
>>> capabiliies, not IO voltage capability.
>
> I think Dong is correct. I don't think SDHCI_CAN_VDD_180 is not

/s /is not /is

> related to UHS modes at all.
>
> At least the name of the field (SDHCI_CAN_VDD_180) indicates it's
> about VDD/VCC, the core power and not the IO voltage.
>
>> Are you sure on this ?? If SDHCI host VDD is  1.8V then the cards are
>> also capable to operate at 1.8V ? Didn't understand what you mean by
>> IO voltage capability
>>
>>
>>> SD3.0 cards require 1.8v IO voltage support.
>>> So should this bit affect SD3.0 support?
>>
>> The preset value resgister says that  SDR modes requires 1.8V and we
>> disable the modes based on capability or quirk.
>
> It requires 1.8V *IO voltage*, not VDD/VCC.
>
> [...]
>
> Kind regards
> Uffe
--
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Re: [PATCH RESEND v7 2/2] mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.

[Suman Tripathi]

Hi Ulf, Dong

On Mon, Jun 8, 2015 at 2:08 PM, Ulf Hansson <ulf.hansson@linaro.org> wrote:
> On 8 June 2015 at 10:37, Ulf Hansson <ulf.hansson@linaro.org> wrote:
>> [...]
>>
>>>> >
>>>> >    Can you test this patch  on imx SoC ?
>>>> >
>>>>
>>>> (Your email have some format issue.)
>>>
>>> Yeah missed to sent in plain text mode.
>>>
>>>>
>>>> I have tested this patch and it does not break imx SoC.
>>>> You can add my tag.
>>>> Tested-by: Dong Aisheng <aisheng.dong@freescale.com>
>>>
>>> Thanks Dong !!
>>>
>>>>
>>>> However, it looks to me SDHCI_CAN_VDD_180 is only indicating the host VDD
>>>> capabiliies, not IO voltage capability.
>>
>> I think Dong is correct. I don't think SDHCI_CAN_VDD_180 is not
>
> /s /is not /is
>
>> related to UHS modes at all.
>>
>> At least the name of the field (SDHCI_CAN_VDD_180) indicates it's
>> about VDD/VCC, the core power and not the IO voltage.
>>
>>> Are you sure on this ?? If SDHCI host VDD is  1.8V then the cards are
>>> also capable to operate at 1.8V ? Didn't understand what you mean by
>>> IO voltage capability
>>>
>>>
>>>> SD3.0 cards require 1.8v IO voltage support.
>>>> So should this bit affect SD3.0 support?
>>>
>>> The preset value resgister says that  SDR modes requires 1.8V and we
>>> disable the modes based on capability or quirk.
>>
>> It requires 1.8V *IO voltage*, not VDD/VCC.

I agree on this now  . I will post a version where this quirk will be
added for arasan 4.9a that doesn't support 1.8v voltage signalling.

>>
>> [...]
>>
>> Kind regards
>> Uffe



-- 
Thanks,
with regards,
Suman Tripathi