[PATCH v2 0/2] arm64: dts: Mediatek: MT8173 updtes

[PATCH v2 0/2] arm64: dts: Mediatek: MT8173 updtes

[Eddie Huang]

This series add MT8173 watchdog and I2C device nodes. Both device nodes 
are based on 4.1-rc1, but I2C need two extra CCF patches from Sascha [1][2].

[1] clk: Add common clock support for Mediatek MT8135 and MT8173
    http://lists.infradead.org/pipermail/linux-arm-kernel/2015-April/338763.html
[2] ARM64: dts: mt8173: Add clock controller device nodes
    http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/344753.html

Change in v2:
Modify I2C device node accroding register address order.

Eddie Huang (2):
  arm64: dts: mt8173: Add watchdog device node
  arm64: dts: mt8173: Add I2C device node

 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 125 +++++++++++++++++++++++++++++++
 1 file changed, 125 insertions(+)

-- 
1.8.1.1.dirty

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[PATCH v2 1/2] arm64: dts: mt8173: Add watchdog device node

[Eddie Huang]

Add MT8173 watchdog device node.

Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 30ac8dd..b52ec43 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -160,6 +160,12 @@
 						<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		watchdog: watchdog@10007000 {
+			compatible = "mediatek,mt8173-wdt",
+				     "mediatek,mt6589-wdt";
+			reg = <0 0x10007000 0 0x100>;
+		};
+
 		sysirq: intpol-controller@10200620 {
 			compatible = "mediatek,mt8173-sysirq",
 					"mediatek,mt6577-sysirq";
-- 
1.8.1.1.dirty

Re: [PATCH v2 1/2] arm64: dts: mt8173: Add watchdog device node

[Matthias Brugger]

On Monday, June 01, 2015 09:08:26 PM Eddie Huang wrote:
> Add MT8173 watchdog device node.
> 
> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
> ---

applied to v4.2-next/arm64

[PATCH v2 2/2] arm64: dts: mt8173: Add I2C device node

[Eddie Huang]

Add MT8173 I2C device nodes, include I2C controllers and pins.
MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
The 6th I2C controller register base doesn't next to 5th I2C,
and there is a hardware between 5th and 6th I2C controller. So
SoC designer name 6th controller as "i2c6", not "i2c5".

Signed-off-by: Eddie Huang <eddie.huang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 119 +++++++++++++++++++++++++++++++
 1 file changed, 119 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index b52ec43..7003ed2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -158,6 +158,53 @@
 			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 						<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 						<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+			i2c0_pins_a: i2c0@0 {
+				pins1 {
+					pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
+						 <MT8173_PIN_46_SCL0__FUNC_SCL0>;
+					bias-disable;
+				};
+			};
+
+			i2c1_pins_a: i2c1@0 {
+				pins1 {
+					pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
+						 <MT8173_PIN_126_SCL1__FUNC_SCL1>;
+					bias-disable;
+				};
+			};
+
+			i2c2_pins_a: i2c2@0 {
+				pins1 {
+					pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
+						 <MT8173_PIN_44_SCL2__FUNC_SCL2>;
+					bias-disable;
+				};
+			};
+
+			i2c3_pins_a: i2c3@0 {
+				pins1 {
+					pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
+						 <MT8173_PIN_107_SCL3__FUNC_SCL3>;
+					bias-disable;
+				};
+			};
+
+			i2c4_pins_a: i2c4@0 {
+				pins1 {
+					pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
+						 <MT8173_PIN_134_SCL4__FUNC_SCL4>;
+					bias-disable;
+				};
+			};
+
+			i2c6_pins_a: i2c6@0 {
+				pins1 {
+					pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
+						 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
+					bias-disable;
+				};
+			};
 		};
 
 		watchdog: watchdog@10007000 {
@@ -229,6 +276,78 @@
 			clocks = <&uart_clk>;
 			status = "disabled";
 		};
+
+		i2c0: i2c@11007000 {
+			compatible = "mediatek,mt8173-i2c";
+			reg = <0 0x11007000 0 0x70>,
+			      <0 0x11000100 0 0x80>;
+			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
+			clock-div = <16>;
+			clocks = <&pericfg CLK_PERI_I2C0>,
+				 <&pericfg CLK_PERI_AP_DMA>;
+			clock-names = "main", "dma";
+			status = "disabled";
+		};
+
+		i2c1: i2c@11008000 {
+			compatible = "mediatek,mt8173-i2c";
+			reg = <0 0x11008000 0 0x70>,
+			      <0 0x11000180 0 0x80>;
+			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
+			clock-div = <16>;
+			clocks = <&pericfg CLK_PERI_I2C1>,
+				 <&pericfg CLK_PERI_AP_DMA>;
+			clock-names = "main", "dma";
+			status = "disabled";
+		};
+
+		i2c2: i2c@11009000 {
+			compatible = "mediatek,mt8173-i2c";
+			reg = <0 0x11009000 0 0x70>,
+			      <0 0x11000200 0 0x80>;
+			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+			clock-div = <16>;
+			clocks = <&pericfg CLK_PERI_I2C2>,
+				 <&pericfg CLK_PERI_AP_DMA>;
+			clock-names = "main", "dma";
+			status = "disabled";
+		};
+
+		i2c3: i2c3@11010000 {
+			compatible = "mediatek,mt8173-i2c";
+			reg = <0 0x11010000 0 0x70>,
+			      <0 0x11000280 0 0x80>;
+			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
+			clock-div = <16>;
+			clocks = <&pericfg CLK_PERI_I2C3>,
+				 <&pericfg CLK_PERI_AP_DMA>;
+			clock-names = "main", "dma";
+			status = "disabled";
+		};
+
+		i2c4: i2c4@11011000 {
+			compatible = "mediatek,mt8173-i2c";
+			reg = <0 0x11011000 0 0x70>,
+			      <0 0x11000300 0 0x80>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
+			clock-div = <16>;
+			clocks = <&pericfg CLK_PERI_I2C4>,
+				 <&pericfg CLK_PERI_AP_DMA>;
+			clock-names = "main", "dma";
+			status = "disabled";
+		};
+
+		i2c6: i2c6@11013000 {
+			compatible = "mediatek,mt8173-i2c";
+			reg = <0 0x11013000 0 0x70>,
+			      <0 0x11000080 0 0x80>;
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
+			clock-div = <16>;
+			clocks = <&pericfg CLK_PERI_I2C6>,
+				 <&pericfg CLK_PERI_AP_DMA>;
+			clock-names = "main", "dma";
+			status = "disabled";
+		};
 	};
 
 };
-- 
1.8.1.1.dirty

Re: [PATCH v2 2/2] arm64: dts: mt8173: Add I2C device node

[Sascha Hauer]

Hi Eddie,

On Mon, Jun 01, 2015 at 09:08:27PM +0800, Eddie Huang wrote:
> Add MT8173 I2C device nodes, include I2C controllers and pins.
> MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
> The 6th I2C controller register base doesn't next to 5th I2C,
> and there is a hardware between 5th and 6th I2C controller. So
> SoC designer name 6th controller as "i2c6", not "i2c5".
> 
> Signed-off-by: Eddie Huang <eddie.huang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
>  arch/arm64/boot/dts/mediatek/mt8173.dtsi | 119 +++++++++++++++++++++++++++++++
>  1 file changed, 119 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index b52ec43..7003ed2 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -158,6 +158,53 @@
>  			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
>  						<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
>  						<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c0_pins_a: i2c0@0 {
> +				pins1 {
> +					pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
> +						 <MT8173_PIN_46_SCL0__FUNC_SCL0>;
> +					bias-disable;
> +				};
> +			};

The pinmux nodes should be in the board dts, not in the SoC dtsi.

Sascha

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Re: [PATCH v2 2/2] arm64: dts: mt8173: Add I2C device node

[Eddie Huang]

Hi Sascha,

On Mon, 2015-06-08 at 09:27 +0200, Sascha Hauer wrote:
> Hi Eddie,
> 
> On Mon, Jun 01, 2015 at 09:08:27PM +0800, Eddie Huang wrote:
> > Add MT8173 I2C device nodes, include I2C controllers and pins.
> > MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
> > The 6th I2C controller register base doesn't next to 5th I2C,
> > and there is a hardware between 5th and 6th I2C controller. So
> > SoC designer name 6th controller as "i2c6", not "i2c5".
> > 
> > Signed-off-by: Eddie Huang <eddie.huang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8173.dtsi | 119 +++++++++++++++++++++++++++++++
> >  1 file changed, 119 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index b52ec43..7003ed2 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -158,6 +158,53 @@
> >  			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> >  						<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> >  						<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> > +			i2c0_pins_a: i2c0@0 {
> > +				pins1 {
> > +					pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
> > +						 <MT8173_PIN_46_SCL0__FUNC_SCL0>;
> > +					bias-disable;
> > +				};
> > +			};
> 
> The pinmux nodes should be in the board dts, not in the SoC dtsi.
> 

These pins are fixed, and all boards using MT8173 SoC I2C controller
should use these pins. To reduce spread these to many board dts files,
so I put i2c pins in SoC dtsi.

Eddie
Thanks


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Re: [PATCH v2 2/2] arm64: dts: mt8173: Add I2C device node

[Matthias Brugger]

2015-06-08 13:10 GMT+02:00 Eddie Huang <eddie.huang@mediatek.com>:
> Hi Sascha,
>
> On Mon, 2015-06-08 at 09:27 +0200, Sascha Hauer wrote:
>> Hi Eddie,
>>
>> On Mon, Jun 01, 2015 at 09:08:27PM +0800, Eddie Huang wrote:
>> > Add MT8173 I2C device nodes, include I2C controllers and pins.
>> > MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
>> > The 6th I2C controller register base doesn't next to 5th I2C,
>> > and there is a hardware between 5th and 6th I2C controller. So
>> > SoC designer name 6th controller as "i2c6", not "i2c5".
>> >
>> > Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
>> > ---
>> >  arch/arm64/boot/dts/mediatek/mt8173.dtsi | 119 +++++++++++++++++++++++++++++++
>> >  1 file changed, 119 insertions(+)
>> >
>> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>> > index b52ec43..7003ed2 100644
>> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>> > @@ -158,6 +158,53 @@
>> >                     interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
>> >                                             <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
>> >                                             <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
>> > +                   i2c0_pins_a: i2c0@0 {
>> > +                           pins1 {
>> > +                                   pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
>> > +                                            <MT8173_PIN_46_SCL0__FUNC_SCL0>;
>> > +                                   bias-disable;
>> > +                           };
>> > +                   };
>>
>> The pinmux nodes should be in the board dts, not in the SoC dtsi.
>>
>
> These pins are fixed, and all boards using MT8173 SoC I2C controller
> should use these pins. To reduce spread these to many board dts files,
> so I put i2c pins in SoC dtsi.

There might be boards with MT8173 which don't use the I2C controller,
right? So this should not go into the SoC dtsi.
For now, we just have one board dts file for MT8173, so I think we can
put it in there.
If in the future more boards get added, we can evaluate if it makes
sense to share the I2C controller pins config between them.

Thanks,
Matthias

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Re: [PATCH v2 2/2] arm64: dts: mt8173: Add I2C device node

[Matthias Brugger]

On Monday, June 01, 2015 09:08:27 PM Eddie Huang wrote:
> Add MT8173 I2C device nodes, include I2C controllers and pins.
> MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
> The 6th I2C controller register base doesn't next to 5th I2C,
> and there is a hardware between 5th and 6th I2C controller. So
> SoC designer name 6th controller as "i2c6", not "i2c5".
> 
> Signed-off-by: Eddie Huang <eddie.huang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---

applied to v4.2-next/arm64

Thanks.
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Re: [PATCH v2 2/2] arm64: dts: mt8173: Add I2C device node

[Daniel Kurtz]

Hi Matthias,

On Wed, Jun 24, 2015 at 4:04 AM, Matthias Brugger
<matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> On Monday, June 01, 2015 09:08:27 PM Eddie Huang wrote:
>> Add MT8173 I2C device nodes, include I2C controllers and pins.
>> MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
>> The 6th I2C controller register base doesn't next to 5th I2C,
>> and there is a hardware between 5th and 6th I2C controller. So
>> SoC designer name 6th controller as "i2c6", not "i2c5".
>>
>> Signed-off-by: Eddie Huang <eddie.huang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>> ---
>
> applied to v4.2-next/arm64

It looks like [0] has the pinctrl changes, but lost the actual i2c nodes.

[0] https://github.com/mbgg/linux-mediatek/commit/0afbf26eda52831560e9f60427751ab8b2641eef

Thanks,
-Dan

>
> Thanks.
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Re: [PATCH v2 2/2] arm64: dts: mt8173: Add I2C device node

[Matthias Brugger]

2015-06-24 13:00 GMT+02:00 Daniel Kurtz <djkurtz-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>:
> Hi Matthias,
>
> On Wed, Jun 24, 2015 at 4:04 AM, Matthias Brugger
> <matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>> On Monday, June 01, 2015 09:08:27 PM Eddie Huang wrote:
>>> Add MT8173 I2C device nodes, include I2C controllers and pins.
>>> MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
>>> The 6th I2C controller register base doesn't next to 5th I2C,
>>> and there is a hardware between 5th and 6th I2C controller. So
>>> SoC designer name 6th controller as "i2c6", not "i2c5".
>>>
>>> Signed-off-by: Eddie Huang <eddie.huang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>>> ---
>>
>> applied to v4.2-next/arm64
>
> It looks like [0] has the pinctrl changes, but lost the actual i2c nodes.

Huh, thanks for noting that. I just fixed it.

Regards,
Matthias
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