From mboxrd@z Thu Jan 1 00:00:00 1970 From: Geert Uytterhoeven Subject: [PATCH/RFC 09/15] ARM: shmobile: r8a7793 dtsi: Add L1 cache information to CPU node Date: Thu, 4 Jun 2015 20:53:35 +0200 Message-ID: <1433444021-22167-10-git-send-email-geert+renesas@glider.be> References: <1433444021-22167-1-git-send-email-geert+renesas@glider.be> Return-path: In-Reply-To: <1433444021-22167-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Simon Horman , Magnus Damm , "Rafael J. Wysocki" , Kevin Hilman , Ulf Hansson , Lina Iyer , Mark Rutland , Pawel Moll Cc: linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sh-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Geert Uytterhoeven List-Id: devicetree@vger.kernel.org Describe the L1 instruction and data caches in the CPU node: - The L1 caches for the Cortex-A15 CPU cores are organized as 16 KiB x 2 ways. Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7793.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index cf153b9c2367a211..a7e892fe3efa7fd3 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -38,6 +38,16 @@ < 937500 1000000>, < 750000 1000000>, < 375000 1000000>; + + i-cache-size = <0x8000>; + i-cache-sets = <512>; + i-cache-block-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <512>; + d-cache-block-size = <32>; + d-cache-line-size = <32>; + next-level-cache = <&L2_CA15>; }; }; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html